CN103515351A - 器件接触、电器件封装件以及制造电器件封装件的方法 - Google Patents

器件接触、电器件封装件以及制造电器件封装件的方法 Download PDF

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CN103515351A
CN103515351A CN201310245378.3A CN201310245378A CN103515351A CN 103515351 A CN103515351 A CN 103515351A CN 201310245378 A CN201310245378 A CN 201310245378A CN 103515351 A CN103515351 A CN 103515351A
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articulamentum
parts
carrier
contact area
layer
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CN103515351B (zh
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约阿希姆·马勒
哈利勒·哈希尼
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本文公开了一种器件接触、电器件封装件以及制造电器件封装件的方法。在一个实施方式中，电器件包括：部件，包括部件接触区域；以及载体，包括载体接触区域。该电器件进一步包括第一导电连接层和第二连接层，该第一导电连接层连接部件接触区域和载体接触区域，其中，该第一导电连接层覆盖部件接触区域的第一区域，该第二连接层连接部件接触区域和载体接触区域，其中，该第二连接层覆盖部件接触区域的第二区域，并且其中，第二连接层包括聚合物层。

Description

器件接触、电器件封装件以及制造电器件封装件的方法
技术领域
本发明大体涉及一种封装电器件，特别是涉及一种包括缓冲层的封装电器件。
背景技术
封装构成单片或多片器件装配的最后阶段，并且在芯片和芯片载体之间提供必要的互连。封装还提供外壳，该外壳保护器件不受到环境的影响，比如，化学腐蚀以及热量和机械的影响或辐射造成的损害。
热机械应力引起的缺陷已经成为可靠性的焦点，影响电子器件的使用期。在芯片和芯片载体之间的接触界面处的分层以及在该界面处或附近的裂缝形成，已经被认定为造成这个问题的原因。出现这些缺陷的原因在于，在器件制造（包括组装和封装）的过程中应用高温或高压工艺。
发明内容
根据一种实施方式，一种封装电器件包括：部件，包含部件接触区域；以及载体，包含载体接触区域。该电器件还包括：第一导电连接层，连接部件接触区域与载体接触区域，其中，第一导电连接层覆盖部件接触区域的第一区；以及第二连接层，连接部件接触区域与载体接触区域，其中，所述第二连接层覆盖部件接触区域的第二区，并且其中，所述第二连接层包括聚合物层。
根据一个实施方式，一种器件封装件包括：半导体器件，包括在底部主面处的漏极接触；引线框，具有引线框接触区域；混合连接层；以及密封剂，密封半导体器件。该混合连接层连接漏极与引线框接触区域，其中，混合连接层包括焊接层和聚合物连接层，该焊接层覆盖大约多于70%的底部表面，该聚合物连接层被设置为与焊接层横向相邻并且覆盖大约少于30%的底部表面。
根据一个实施方式，一种制造封装电器件的方法包括：在载体的背面上形成背面金属化（BSM）层；在BSM层上选择性地形成导电连接层，导电连接层设置在载体的多个部件中的一个部件的中心区处；以及从载体处分离（singulating）部件。该方法还包括：将部件结合（bonding）至部件载体；以及密封该部件和该部件载体的至少一部分。
附图说明
为了更完整地理解本发明及其优点，现在参照结合附图进行的以下描述，其中：
图1示出了传统芯片的剖视图，其中，传统芯片在背面接触结构内附接至芯片载体；
图2示出了在背面接触结构内的封装电部件的第一实施方式的剖视图；
图3示出了在背面接触结构内的封装电部件的第二实施方式的剖视图；
图4示出了用于制造封装电部件的工艺流程的一个实施方式；
图5a和5b示出了在使电部件和部件载体接触之前的电器部件的剖视图和顶视图的一个实施方式；以及
图6示出了包括电部件背面的晶片的一个实施方式的详细顶视图。
具体实施方式
下面详细讨论目前优选的实施方式的制作和使用。然而，应理解的是，本发明提供多个适用的发明概念，可在多种具体背景中实现这些概念。所讨论的具体实施方式仅仅说明制作和使用本发明的具体方式，并不限制本发明的范围。
将关于具体背景中的实施方式（即，相对于附接至引线框的芯片）描述本发明。不过，本发明的实施方式可用于任何类型的载体或部件中。
图1示出了具有背面芯片结构的半导体器件10。半导体器件10包括芯片100，该芯片100设置在铜（Cu）引线框106上。芯片100通过背面金属化（BSM）层102和焊接层104与Cu引线框106电连接。模塑材料110密封芯片100。在结合处理的某些阶段期间，焊接层104可较为柔软且可延展，以在芯片100的背面和Cu引线框106的顶部表面之间建立接触。然而，在完成结合处理之后，焊接层104具有刚性并且提供牢固的机械连接。
这种传统芯片背面结构的一个问题在于，沿着芯片114的侧沿区（“边缘区”）易于分层、断裂、裂缝以及受到其他类型的损害。
本发明的一个实施方式为部件和部件载体之间的接触提供一种混合连接层设置。背面附接配置中焊接层和缓冲层可在在部件和部件载体之间提供电接触。在一个实施方式中，焊接层可覆盖大约70%或以上的接触区域，并且缓冲层可覆盖大约30%或以下的接触区域。缓冲层可具有弹性和/或包含一种合适的热膨胀系数（CTE系数）。缓冲层可包含聚合物。这种混合连接层设置的一个优点在于，相对于传统设置，大幅减少了裂缝、断裂以及分层的发生率，并因此部件更加可靠。
本发明的另一个实施方式提供了一种在晶片的背面上形成混合连接层设置的方法。
图2示出了封装电器件或封装半导体器件20的一个实施方式。封装电器件20包括设置在载体206上的部件200。该部件200可为半导体器件，比如，逻辑器件或易失性或非易失性存储器件。半导体器件可为集成电路（IC）或单个离散器件（独立式器件）。例如，半导体器件为IGBT或功率MOSFET。可选地，部件200是无源器件，比如，电阻器、电容器、MEMS器件、光电子部件、或具有其他功能的器件。其上或其内构建电器件的部件200的基板/基底可以是半导体材料，比如，硅或锗，或者可为化合物半导体，比如，SiGe、GaAs、InP、GaN或SiC，或者可包括其他无机或有机材料，比如，玻璃、陶瓷。
部件200具有第一主面或顶部表面以及第二主面或底部表面。底部表面的面积可与顶部表面的面积相同。部件200在底部表面处具有接触。部件200在其他表面上可进一步包括一个或多个接触。在一个特定的实例中，部件200在底部表面上具有漏极接触并且在顶部表面上具有栅极和源极接触。
封装电器件20进一步包括部件载体206，部件200设置在该部件载体206上。部件载体206可包括基板，比如，半导体材料、陶瓷、玻璃、或机械稳定的有机化合物。部件载体206可包括导电和/或非导电元件。例如，部件载体206可包括硅基板、印刷电路板（PCB）或引线框。PCB可以是诸如半固化片堆叠这样的层压基板，其包括交替的导电材料层和浸渍环氧树脂的玻璃层。金属引线框可包括镍（Ni）、铜（Cu）或其组合。
部件200通过背面金属化（BSM）层202和包括第一连接层204和第二连接层208的混合连接层与部件载体206电连接。
背面金属化（BSM）层202设置在部件200的背面上。BSM层202可包括包含不同材料的一层或多层。例如，BSM层202可为三层堆叠。在一个实施方式中，用于具有垂直电流的芯片的BSM层202堆叠可为Al/Ti/NiV、Al/Ti/NiV/Ag、Al/Ti/Ni/Ti、Al/Ti/Ni/Ti/Ag、Al/Ti/TiNi/Ni/Ti/Ag、Al/Ti/NiV/Ag、Al/Ti/NiV、Al/Ti、Al/Ti/Cu/Sn/Ag、Al/TiW或Al/TiW/Cu/Sn/Ag。
BSM层202的第一层可为到部件200的基板的欧姆接触。欧姆接触层可包含金属，比如，Al。BSM层202的第二层可保护电路和互连免受从接触界面到部件/基板200内的不被期望的结合相关的金属扩散。此外，第二层可增强焊接层与部件/基板200的粘附力。第二层可包括金属，比如Cr、Ti或Ta。第二层可大约为200nm到大约300nm厚。
BSM层202的第三层可被配置成具有对相邻的混合连接层的高扩散系数，以提供强界面结合。最后一层可包含金属，比如，金（Au）、银（Ag）、镍（Ni）、铜（Cu）或这些材料的组合。最后一层可为大约100nm到大约10μm厚，而BSM层的总厚度可为大约500nm到大约15um。在一个实施方式中，在部件200附接至载体206时，BSM层部分地与载体的金属层发生作用。
第一连接层204设置在BSM层202和部件载体206之间。第一连接层204可设置在部件200的底部表面的第一区上。第一连接层204可包括部件200的底部主面的多于70%或者多于90%的面积。在一个实例中，第一连接层204可包括部件200的底部主面的面积的大约70%到大约90%。第一连接层204可覆盖底部表面的中心区域。
第一连接层204可包括无机或有机材料，该材料被配置成向BSM层202和部件载体206提供强化学结合。第一连接层204包含导电材料，比如，金属或金属合金。在一个实施方式中，第一连接层204为焊接层。例如，焊接层可包括二元或三元合金，比如，Pb/Sn、Au/Sn、Ag/Sn、Cu/Sn、Au、Si、Sn/Sb或Sn/Ag/Sb。焊接材料可为无Pb材料。在一个实施方式中，焊接材料在半导体片（die）和金属引线框之间提供低电阻接触。
第二连接层（比如，缓冲层）208设置在BSM层202和部件载体206之间。第二连接层208设置成与第一连接层204相邻。第二连接层208可设置在部件200的底部表面的第二区内。第二连接层208可包括部件200的底部表面的少于约10%或者少于约30%的面积。在一个实例中，第二连接层208可包括部件200的底部表面的大约10%到大约30%。第二连接层208可覆盖部件200的底部表面的外围区。
在一个实施方式中，第二连接层208为弹性材料，比如，聚合物。弹性表示第二连接层208比第一连接层204的弹性大的多。第二连接材料208的弹性系数值可明显高于第一连接材料204的弹性系数，例如，1MPa到50GPa，比如，100MPa到10GPa。由于第二连接层208具有弹性，所以该层能够消除或减轻在部件200与部件载体206之间的接触的外围以及芯片边缘区域214内发生的应力的影响。第二连接层可以是聚合物材料连接层。
在一个实例中，第二连接层208被关于其热膨胀系数（CTE）优化，以将部件边缘区214内的热机械应力最小化。第二连接层208可减小相关材料的CTE系数的较大差异。例如，主要诱因材料为部件200材料和部件载体206材料。例如，Si基板的CTE值为大约2.5ppm/K，而Cu引线框的CTE值为16.5ppm/K。在一个实施方式中，第二连接层208具有的CTE值在大约5ppm/K到大约200ppm/K的范围内，比如，大约20ppm/K到大约100ppm/K，以便在形成接触之后，为所产生的器件消除应力。
第二连接层208可包括有机非导电材料。例如，第二连接层可包括聚合物。第二连接层208可为弹性聚合物绝缘连接层。在一个实施方式中，第二连接层208包括短期热稳定性高达大约400°C的聚合物，以便耐受高焊接温度。第二连接层208材料可包括高度交联（cross-linked）的环氧或丙烯酸酯树脂、聚酰亚胺、或高性能的热塑性材料，比如，聚苯硫（PPS）、聚砜（PSU）或液晶聚合物（LCP）。第二连接层可包括非导电填充颗粒。第二连接层208可提供良好的粘附力以及良好的润湿特性。
在一个实施方式中，第二连接材料208可导电。例如，导电材料可为一种与上述相同类型的具有足够高的导电填充材料浓度的聚合物。导电填充材料可为均匀地分布在聚合物内的较小导电颗粒（<5μm）。例如，这些填充颗粒可包括银（Ag）或铜（Cu）。可选地，填充颗粒可为类碳石墨烯或碳纳米管（CNTs）。其他导电连接材料可包括上述基础聚合物与诸如聚苯胺、聚乙炔、或聚噻吩这样的具有内在导电性的化合物的聚合物或共聚物。第二连接层208可为弹性导电聚合物连接层。第二导电连接层208可不为金属层。
第一和第二连接层204和208形成混合连接层。混合连接层在第一连接层204与第二连接层208之间可具有大约9/1到大约7/3的比率。混合连接层可不覆盖部件200的整个底部表面，而是仅仅覆盖部件200的底部表面的一部分。
封装电器件20进一步包括密封剂210。密封剂210的密封材料可为模塑料或层压材料。例如，密封材料可包括热固材料，比如，环氧树脂、聚氨酯、或聚丙烯酸酯化合物。可选地，封装材料可包括热塑性材料，比如，聚砜、聚苯硫、或聚醚酰亚胺。在一个实例中，密封剂210可包括聚酰亚胺，比如，Si改性聚酰亚胺。
图3示出了封装电器件30的另一个实施方式。封装电器件30包括部件300、BSM层302、第一连接层304、载体306以及密封剂310。这些元件包括与图2的实施方式相同或相似的材料。但是，第二连接层包括密封剂310的密封材料。密封材料可包括合适的弹性系数、CTE系数或其组合。密封材料可提供保护，不受到机械或腐蚀性损害。图3的实施方式的一个优点在于，由于在制造封装电器件30时，需要较少的处理步骤，所以非常划算。
图4示出了制造封装电部件的流程图400的一个实施方式。在第一步骤405中，提供载体。该载体可为工件、基板、晶片、或印刷电路板（PCB）。可选地，该载体是具有放置其上的未封装的芯片或部件的基板。在一个实施方式中，晶片可包括半导体材料或化合物材料以及设置在其上的一个或多个互连金属化层。钝化层被设置在互连金属化层之上，并且芯片接触垫设置在钝化层上或者由该钝化层所定义。
在步骤410中，背面金属化（BSM）层形成在载体的背面之上。载体的背面可以是相对于载体的正面来说少数部件所在的面。BSM层可为一层或多层。例如，可通过电镀、化学气相沉积（CVD）、离子束溅射或反应溅射来沉积BSM层。
在另一个步骤415中，第一连接层或导电连接层（比如，焊料）形成在BSM层之上。在覆盖层（blanket）沉积处理中，可形成第一连接层。通过电镀、气相沉积、蒸镀溅射、喷射、喷洒、或起泡（beading），可沉积第一连接层的材料（比如，焊接材料）。可选地，该材料可被印刷或散布在BSM层上，或者以焊膏的形式被沉积。
在步骤420中，使第一连接层图案化。将第一连接层图案化为使第一连接层保持在设置在载体或BSM层之内或之上的多个部件中的一个部件的第一区（比如，中心区）之上。在部件背面或BSM层的第二区（比如，外围区）之上去除第一连接层。在一个实施方式中，在该部件或BSM层的背面区域上的高达30%的第一连接层被去除。可选地，在该部件或BSM层的背面区域上的高达10%的第一连接层被去除。没有第一连接层的第二区（比如，外围区）形成在BSM层之上。
图5a和5b示出了单个部件的背面层设置的一个实施方式的剖视图和顶视图。BSM层502覆盖部件500的整个背面区域，而第一连接层504仅仅覆盖部件500的背面区域的中心区。在部件500的背面区域的外围区内去除第一连接层504。
在一个实施方式中，通过激光烧蚀，可局部地或区域选择性地去除第一连接层。通过使用产生193或248nm波长的紫外光的Nd:YAG和受激准分子激光器，可去除第一连接层。通过高度聚焦的激光束或者通过光学屏蔽边缘区域，可实现区域选择性去除第一连接层（比如，焊料）。在激光烧蚀的过程中使部件背面堆叠退火，可协助蒸镀焊接材料，并且最小化边缘区内不需要的第一连接层（比如，焊料）的重新沉积，该边缘区应保持没有第一连接层（比如，焊料）。
在一个实施方式中，通过湿法或干法蚀刻步骤，可部分去除第一连接层。蚀刻步骤允许以高对准精度以及高剖面质量将覆盖第一连接层（比如，焊料）和没有第一连接层（比如，焊料）的区域之间的边界线图案化。基于光刻的图案化处理和随后的蚀刻处理理想地适合于构造具有无焊料边缘区的多个焊接图案。
图6示出了包括四个相邻的矩形部件的载体（比如，晶片）的背面的一个实施方式的详细顶视图。这四个部件620-650为在整个载体（比如，晶片）上延伸的多个部件的一部分。载体（比如，晶片）的背面由BSM层覆盖。仍由第一连接层（比如，焊料）604覆盖的BSM层的区域被没有第一连接层（比如，焊料）的区域602包围，其中，区域602的宽度在x方向为d1608并且在y方向为d2606。宽度d1和宽度d2可相同或者可不同。
分离个体部件620到640的十字条对应于载体（比如，晶片）在切割的过程中会失去的区域。切割条610的宽度标记为ddice。因此，在相邻的焊料覆盖的区之间的图案化距离在x方向可为2d1+ddice，并且在y方向可为2d2+ddice。
由湿法或干法蚀刻（在图案化光致抗蚀剂之后）在外围区上去除第一连接层。例如，在湿法蚀刻中，利用HCl/HF（1:1）或HCl/HNO3（1:1）的水溶液去除焊接材料。湿法蚀刻处理在本质上具有各向同性。例如，在干法蚀刻中，由RIE去除焊料。金属的蚀刻气体可包含诸如CF4、CHF3、CH2F2、C4F8、C4F6、SiF4、或SF6这样的含氟化合物、或者含氯化合物（比如，Cl2、CCl4、HCl），还通常添加有N2、惰性气体（He、Ar）或O2。添加有O2的含氟和氯气体的混合物可成功地用于多种焊接去除处理。完成湿法或干法蚀刻处理之后，去除光致抗蚀剂。
在一个实施方式中，在BSM层上选择性地将第一连接（比如，焊料）层形成为使第一连接层仅仅覆盖这些部件的背面区域的中心区，而不覆盖这个背面区域的外围区。经由机械边缘屏蔽、喷射/喷洒焊料、或模板印刷焊膏选择性沉积的焊料可形成第一连接层。
接下来，在步骤425处，在去除第一连接层的区域内，形成第二连接层（比如，诸如聚合物层这样的缓冲层）。第二连接层可沉积在第一连接层和露出的BSM层之上。可选地，第二连接层可选择性地设置在露出的BSM层之上。第二连接层可填充去除第一连接层的区域。第二连接层可直接形成在BSM层上。通过旋转涂布、分配有机材料或印刷材料的溶液，可形成第二连接层。在涂覆后的烘焙过程中，可蒸镀溶剂。通过化学机械抛光（CMP）或其他方法（比如，研磨/抛光），去除第二连接层不需要的材料。
在一个实施方式中，在去除第一连接层的区域内可挤压第二连接层材料。可选地，第二连接层设置成与选择性设置的第一连接层相邻。通过激光烧蚀等方法可去除从该部件外围中突出的第二连接层的多余材料。
在可选的步骤430中，预先固化（pre-cure）第二连接层或缓冲层（比如，聚合物材料连接层），以更容易处理载体（比如，晶片），比如，分割载体以及运输载体。在大约80°C到大约200°C的温度下可进行预先硫化。
在步骤435中，载体被切割形成多个个体部件，每个部件具有包括第一连接层和第二连接层的背面混合连接层设置。然后，在440中，在部件载体上倒装和组装单独部件。具体地，个体部件放置在部件载体的部件附接区域上。
在一个实施方式中，该部件通过扩散结合可附接至部件载体。例如，在部件背面上的混合连接层接触表面与部件载体（比如，引线框）表面进行物理接触。为了沿着第一连接（比如，焊料）材料和部件载体（比如，引线框）金属（比如，Cu）之间的接触表面产生金属间晶粒生长，该温度可设为比第一连接（比如，焊料）材料的熔点高大约20°C到大约50°C。在使用共晶的第一连接（比如，焊料）材料时，可降低结合温度。例如，共晶合金的共晶温度对于Au/Sn而言大约为231°C，对于Au/Si而言大约为370°C，或者对于Au/In而言大约为156°C。在还原性气氛中（在N2中具有4%的H2），可进行结合。在大约300°C到大约400°C的范围内的温度可足以在部件载体（比如，引线框）表面和缓冲（比如，聚合物）层之间形成强化学键（bond）（比如，通过金属O-C或金属O-Si键）。
可选地，可通过反应结合（reactive bonding）附接该部件。在使该部件背面的混合连接层与部件载体进行物理接触后，可从多层反应结合堆叠的外围开始在BSM层内进行自传播的放热反应，这就造成在整个接触区域上的生热扩散，引起上覆焊接层熔化。例如，可通过热量、压力所产生的能量脉冲或激光脉冲开始自传播的放热反应。
在步骤445中，该部件被结合至部件载体。例如，该部件的顶部表面的部件接触垫被结合至部件载体的载体接触垫。该部件的部件接触垫引线结合、球形结合或通过其他方式结合至载体接触垫。引线为金属，比如，铝（Al）、铜（Cu）、银（Ag）或金（Au）。
在步骤450中，使用模塑料密封该部件。模塑料可包括热固性材料或热塑性材料。模塑料可包括粗粒材料。在一个实施方式中，可应用传递模塑来密封部件/载体单元。在压力下，将模塑材料（比如，热固性模塑材料）传递到模塑腔内，并且填充铸模型腔，随后可执行二次固化步骤。
可选地，可使用注射模塑。例如，塑料小球可穿过几个加热区，直到这些塑料小球离开最终的加热区，进入熔化状态中。从该状态中，将模塑材料注入进行凝固的模塑腔内。注射模塑可用于热塑性和热固性塑料材料中。无需考虑所应用的模塑方法，所产生的封装随后进行飞边清除操作，以便去除多余的树脂。结合高压空气或高压水浆，使用精细的磨料颗粒的混合物，进行飞边清除。
最后，在455中，将密封的部件载体分割成封装的电部件，每个电部件包括一个部件。例如，使用切割锯分离被个体封装的电部件。
虽然已经详细地描述了本发明及其优点，但是应理解的是，在不背离所附权利要求书所限定的本发明的精神和范围的前提下，可在其内进行各种改变、替代以及变更。
而且，本应用的范围并非旨在限于在本说明书中所描述的处理、机器、制造、物质的组合物、器件、方法以及步骤的特定实施方式。通过本发明的公开内容，本领域的技术人员容易理解的是，根据本发明，可使用目前已有的或随后要研制的处理、机器、制造、物质的组合物、器件、方法、或步骤，其与本文中所描述的相应实施方式执行大致相同的功能或实现大致相同的结果。因此，所附权利要求书旨在，在其范围内包括这样的处理、机器、制造、物质的组合物、器件、方法、或步骤。

Claims (22)

1.一种封装电器件，包括：
部件，包括部件接触区域；
载体，包括载体接触区域；
第一导电连接层，连接所述部件接触区域与所述载体接触区域，其中，所述第一导电连接层覆盖所述部件接触区域的第一区；以及
第二连接层，连接所述部件接触区域与所述载体接触区域，其中，所述第二连接层覆盖所述部件接触区域的第二区，并且其中，所述第二连接层包括聚合物层。
2.根据权利要求1所述的电器件，其中，所述第一导电连接层覆盖约70%到约90%的所述部件接触区域，并且，其中，所述第二连接层覆盖约30%到约10%的所述部件接触区域。
3.根据权利要求1所述的电器件，其中，所述第二连接层包括在约1MPa到约50MPa之间的弹性部件。
4.根据权利要求1所述的电器件，其中，所述第二连接层包括在约5ppm/K到约200ppm/K之间的CTE部件。
5.根据权利要求1所述的电器件，其中，所述第二连接层包括弹性聚合物导电连接层。
6.根据权利要求5所述的电器件，其中，所述弹性聚合物导电连接层包括导电填充颗粒。
7.根据权利要求1所述的电器件，其中，所述第二连接层为弹性聚合物绝缘连接层。
8.根据权利要求7所述的电器件，其中，所述弹性聚合物绝缘连接层包括非导电填充颗粒。
9.根据权利要求1所述的电器件，其中，所述第二连接层沿着所述部件的外围减小机械应力。
10.根据权利要求1所述的电器件，其中，所述载体包括引线框，并且其中，所述部件包括具有背面金属化层的半导体芯片。
11.一种半导体器件封装件，包括：
半导体器件，包括在底部主面处的漏极接触；
引线框，具有引线框接触区域；
混合连接层，连接所述漏极与所述引线框接触区域，其中，所述混合连接层包括焊接层和聚合物连接层，所述焊接层覆盖多于约70%的所述底部主面，所述聚合物连接层设置成与所述焊接层横向相邻并且覆盖少于约30%的所述底部主面；以及
密封剂，密封所述半导体器件。
12.根据权利要求11所述的半导体器件，其中，所述焊接层覆盖约70%到约90%的所述底部表面，并且其中，所述聚合物连接层覆盖约10%到约30%的所述底部表面。
13.根据权利要求12所述的半导体器件，其中，所述焊接层具有机械刚性，并且其中，所述聚合物连接层具有机械弹性。
14.根据权利要求13所述的半导体器件，其中，所述半导体器件进一步包括覆盖所述底部表面的背面金属化层，并且其中，所述引线框为铜引线框。
15.一种制造电器件的方法，所述方法包括：
在载体的背面上形成背面金属化（BSM）层；
在所述背面金属化层上选择性地形成导电连接层，所述导电连接层被设置在所述载体的多个部件中的一个部件的中心区处；
从所述载体处分离部件；
将所述部件与部件载体结合；以及
密封所述部件与所述部件载体的至少一部分。
16.根据权利要求15所述的方法，进一步包括在所述部件的外围区内形成聚合物材料连接层。
17.根据权利要求16所述的方法，其中，所述聚合物材料连接层包括导电填充颗粒。
18.根据权利要求16所述的方法，其中，所述聚合物材料连接层包括非导电填充颗粒。
19.根据权利要求16所述的方法，其中，预先固化所述聚合物材料连接层。
20.根据权利要求16所述的方法，其中，使所述部件与所述部件载体结合包括固化所述聚合物材料连接层。
21.根据权利要求15所述的方法，其中，选择性地形成所述导电连接层包括在所述载体的背面上形成所述导电连接层以及去除所述导电连接层的一部分。
22.根据权利要求15所述的方法，其中，密封所述部件和所述部件载体包括模塑所述部件和所述部件载体或者层压所述部件和所述部件载体。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206518A (zh) * 2015-05-29 2016-12-07 英飞凌科技股份有限公司 焊料金属化堆叠以及其形成方法
CN107958857A (zh) * 2017-11-28 2018-04-24 北方电子研究院安徽有限公司 一种压块触发装置和环氧树脂真空低压封装工艺方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016117826B4 (de) 2016-09-21 2023-10-19 Infineon Technologies Ag Elektronikmodul und herstellungsverfahren dafür
DE102018131775A1 (de) * 2018-12-11 2020-06-18 Osram Opto Semiconductors Gmbh Elektronisches Bauelement und Verfahren zur Herstellung eines elektronischen Bauelements
DE102022108571A1 (de) * 2022-04-08 2023-10-12 Ams-Osram International Gmbh Zusammensetzung, verfahren zum verbinden eines trägers und einer elektronischen komponente und elektronisches bauelement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08124615A (ja) * 1994-10-24 1996-05-17 Hitachi Chem Co Ltd 電気部材の接続構造
JP2004221293A (ja) * 2003-01-15 2004-08-05 Sony Corp 半導体装置とその製造方法
US20070210429A1 (en) * 2006-03-07 2007-09-13 Industrial Technology Research Institute Package structure for electronic device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW583757B (en) * 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
US7148554B2 (en) * 2004-12-16 2006-12-12 Delphi Technologies, Inc. Discrete electronic component arrangement including anchoring, thermally conductive pad
US7982307B2 (en) * 2006-11-22 2011-07-19 Agere Systems Inc. Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate
US8283756B2 (en) 2007-08-20 2012-10-09 Infineon Technologies Ag Electronic component with buffer layer
US8633586B2 (en) * 2008-03-26 2014-01-21 Stats Chippac Ltd. Mock bump system for flip chip integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08124615A (ja) * 1994-10-24 1996-05-17 Hitachi Chem Co Ltd 電気部材の接続構造
JP2004221293A (ja) * 2003-01-15 2004-08-05 Sony Corp 半導体装置とその製造方法
US20070210429A1 (en) * 2006-03-07 2007-09-13 Industrial Technology Research Institute Package structure for electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206518A (zh) * 2015-05-29 2016-12-07 英飞凌科技股份有限公司 焊料金属化堆叠以及其形成方法
US10115688B2 (en) 2015-05-29 2018-10-30 Infineon Technologies Ag Solder metallization stack and methods of formation thereof
CN106206518B (zh) * 2015-05-29 2019-02-26 英飞凌科技股份有限公司 焊料金属化堆叠以及其形成方法
US10573611B2 (en) 2015-05-29 2020-02-25 Infineon Technologies Ag Solder metallization stack and methods of formation thereof
CN107958857A (zh) * 2017-11-28 2018-04-24 北方电子研究院安徽有限公司 一种压块触发装置和环氧树脂真空低压封装工艺方法
CN107958857B (zh) * 2017-11-28 2024-03-19 北方电子研究院安徽有限公司 一种压块触发装置和环氧树脂真空低压封装工艺方法

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