CN103403865B - 具有静态弯曲部的斜坡堆栈芯片封装 - Google Patents

具有静态弯曲部的斜坡堆栈芯片封装 Download PDF

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Publication number
CN103403865B
CN103403865B CN201180042191.2A CN201180042191A CN103403865B CN 103403865 B CN103403865 B CN 103403865B CN 201180042191 A CN201180042191 A CN 201180042191A CN 103403865 B CN103403865 B CN 103403865B
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ramp assembly
semiconductor dies
chip package
semiconductor die
semiconductor
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Chinese (zh)
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CN103403865A (zh
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J·A·哈拉达
D·C·道格拉斯
R·J·德罗斯特
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Oracle International Corp
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Oracle International Corp
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    • H10W90/00—Package configurations
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
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    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
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    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
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    • H10W72/221—Structures or relative sizes
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    • H10W72/221—Structures or relative sizes
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
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    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201180042191.2A 2010-09-02 2011-08-04 具有静态弯曲部的斜坡堆栈芯片封装 Active CN103403865B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/874,446 US8283766B2 (en) 2010-09-02 2010-09-02 Ramp-stack chip package with static bends
US12/874,446 2010-09-02
PCT/US2011/046519 WO2012030470A2 (en) 2010-09-02 2011-08-04 Ramp-stack chip package with static bends

Publications (2)

Publication Number Publication Date
CN103403865A CN103403865A (zh) 2013-11-20
CN103403865B true CN103403865B (zh) 2016-08-03

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Country Status (7)

Country Link
US (1) US8283766B2 (https=)
EP (1) EP2612356B1 (https=)
JP (1) JP6000952B2 (https=)
KR (1) KR101853754B1 (https=)
CN (1) CN103403865B (https=)
TW (1) TWI527132B (https=)
WO (1) WO2012030470A2 (https=)

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WO2014003533A1 (en) * 2012-06-25 2014-01-03 Intel Corporation Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
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KR101994930B1 (ko) 2012-11-05 2019-07-01 삼성전자주식회사 일체형 단위 반도체 칩들을 갖는 반도체 패키지
JP6129605B2 (ja) * 2013-03-25 2017-05-17 本田技研工業株式会社 電力変換装置の製造方法及びそれに用いられる治具
JP6133093B2 (ja) * 2013-03-25 2017-05-24 本田技研工業株式会社 電力変換装置
KR20150018099A (ko) * 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 적층 반도체 장치
US9209165B2 (en) * 2013-10-21 2015-12-08 Oracle International Corporation Technique for controlling positions of stacked dies
US9825002B2 (en) * 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9837394B2 (en) 2015-12-02 2017-12-05 International Business Machines Corporation Self-aligned three dimensional chip stack and method for making the same
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9929290B2 (en) 2016-06-20 2018-03-27 Globalfoundries Inc. Electrical and optical via connections on a same chip
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN107993997B (zh) 2016-10-26 2020-06-16 晟碟信息科技（上海）有限公司 半导体器件
CN108933109B (zh) 2017-05-27 2020-07-07 晟碟信息科技（上海）有限公司 成角度的裸芯的半导体器件
US10963780B2 (en) 2017-08-24 2021-03-30 Google Llc Yield improvements for three-dimensionally stacked neural network accelerators
KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
US20190279962A1 (en) * 2018-03-09 2019-09-12 Oracle International Corporation Method and apparatus for stacking warped chips to assemble three-dimensional integrated circuits
US11222865B2 (en) * 2020-05-12 2022-01-11 Western Digital Technologies, Inc. Semiconductor device including vertical bond pads
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US8283766B2 (en) 2012-10-09
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US20120056327A1 (en) 2012-03-08
JP6000952B2 (ja) 2016-10-05
WO2012030470A3 (en) 2012-05-03
CN103403865A (zh) 2013-11-20
EP2612356A2 (en) 2013-07-10
TW201234501A (en) 2012-08-16
KR101853754B1 (ko) 2018-06-20
TWI527132B (zh) 2016-03-21
KR20130136446A (ko) 2013-12-12

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