TWI527132B - 晶片封裝，電子計算裝置及用以傳遞信號之方法 - Google Patents

晶片封裝，電子計算裝置及用以傳遞信號之方法 Download PDF

Info

Publication number
TWI527132B
TWI527132B TW100128699A TW100128699A TWI527132B TW I527132 B TWI527132 B TW I527132B TW 100128699 A TW100128699 A TW 100128699A TW 100128699 A TW100128699 A TW 100128699A TW I527132 B TWI527132 B TW I527132B
Authority
TW
Taiwan
Prior art keywords
semiconductor dies
semiconductor
ramp
ramp assembly
semiconductor die
Prior art date
Application number
TW100128699A
Other languages
English (en)
Chinese (zh)
Other versions
TW201234501A (en
Inventor
約翰 哈瑞達
大衛 道格拉斯
羅伯特 多斯特
Original Assignee
奧瑞可國際公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 奧瑞可國際公司 filed Critical 奧瑞可國際公司
Publication of TW201234501A publication Critical patent/TW201234501A/zh
Application granted granted Critical
Publication of TWI527132B publication Critical patent/TWI527132B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07237—Techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07323—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/225—Bumps having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/285—Alignment aids, e.g. alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW100128699A 2010-09-02 2011-08-11 晶片封裝，電子計算裝置及用以傳遞信號之方法 TWI527132B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/874,446 US8283766B2 (en) 2010-09-02 2010-09-02 Ramp-stack chip package with static bends

Publications (2)

Publication Number Publication Date
TW201234501A TW201234501A (en) 2012-08-16
TWI527132B true TWI527132B (zh) 2016-03-21

Family

ID=44630458

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100128699A TWI527132B (zh) 2010-09-02 2011-08-11 晶片封裝，電子計算裝置及用以傳遞信號之方法

Country Status (7)

Country Link
US (1) US8283766B2 (https=)
EP (1) EP2612356B1 (https=)
JP (1) JP6000952B2 (https=)
KR (1) KR101853754B1 (https=)
CN (1) CN103403865B (https=)
TW (1) TWI527132B (https=)
WO (1) WO2012030470A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI698809B (zh) * 2017-08-24 2020-07-11 美商谷歌有限責任公司 用於三維堆疊式神經網路加速器之良率改善

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8390109B2 (en) * 2011-02-17 2013-03-05 Oracle America, Inc. Chip package with plank stack of semiconductor dies
US8786080B2 (en) * 2011-03-11 2014-07-22 Altera Corporation Systems including an I/O stack and methods for fabricating such systems
US9082632B2 (en) * 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
WO2014003533A1 (en) * 2012-06-25 2014-01-03 Intel Corporation Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
KR101880173B1 (ko) * 2012-07-11 2018-07-19 에스케이하이닉스 주식회사 멀티 칩 패키지
KR101994930B1 (ko) 2012-11-05 2019-07-01 삼성전자주식회사 일체형 단위 반도체 칩들을 갖는 반도체 패키지
JP6129605B2 (ja) * 2013-03-25 2017-05-17 本田技研工業株式会社 電力変換装置の製造方法及びそれに用いられる治具
JP6133093B2 (ja) * 2013-03-25 2017-05-24 本田技研工業株式会社 電力変換装置
KR20150018099A (ko) * 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 적층 반도체 장치
US9209165B2 (en) * 2013-10-21 2015-12-08 Oracle International Corporation Technique for controlling positions of stacked dies
US9825002B2 (en) * 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9837394B2 (en) 2015-12-02 2017-12-05 International Business Machines Corporation Self-aligned three dimensional chip stack and method for making the same
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9929290B2 (en) 2016-06-20 2018-03-27 Globalfoundries Inc. Electrical and optical via connections on a same chip
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN107993997B (zh) 2016-10-26 2020-06-16 晟碟信息科技（上海）有限公司 半导体器件
CN108933109B (zh) 2017-05-27 2020-07-07 晟碟信息科技（上海）有限公司 成角度的裸芯的半导体器件
KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
US20190279962A1 (en) * 2018-03-09 2019-09-12 Oracle International Corporation Method and apparatus for stacking warped chips to assemble three-dimensional integrated circuits
US11222865B2 (en) * 2020-05-12 2022-01-11 Western Digital Technologies, Inc. Semiconductor device including vertical bond pads
US20230247795A1 (en) 2022-01-28 2023-08-03 The Research Foundation For The State University Of New York Regenerative preheater for phase change cooling applications

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
DK174111B1 (da) 1998-01-26 2002-06-24 Giga As Elektrisk forbindelseselement samt fremgangsmåde til fremstilling af et sådant
TW460927B (en) 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
JP2001036309A (ja) 1999-07-15 2001-02-09 Nec Eng Ltd マルチチップモジュール接続構造
US6376904B1 (en) 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
CN1207785C (zh) * 2000-03-21 2005-06-22 三菱电机株式会社 半导体器件、电子装置的制造方法、电子装置和携带式信息终端
JP2001313314A (ja) * 2000-04-28 2001-11-09 Sony Corp バンプを用いた半導体装置、その製造方法、および、バンプの形成方法
JP2002009221A (ja) * 2000-06-26 2002-01-11 Rohm Co Ltd 半導体装置及びその製造方法
US6921867B2 (en) * 2002-11-29 2005-07-26 Nokia Corporation Stress release feature for PWBs
KR100498488B1 (ko) * 2003-02-20 2005-07-01 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
JP4215689B2 (ja) * 2004-06-17 2009-01-28 株式会社新川 ワイヤボンディング方法及びバンプ形成方法
DE102005051332B4 (de) * 2005-10-25 2007-08-30 Infineon Technologies Ag Halbleitersubstrat, Halbleiterchip, Halbleiterbauteil und Verfahren zur Herstellung eines Halbleiterbauteils
JP4191204B2 (ja) * 2006-05-12 2008-12-03 エルピーダメモリ株式会社 半導体装置およびその製造方法
US7829438B2 (en) * 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
TW200820402A (en) * 2006-10-26 2008-05-01 Chipmos Technologies Inc Stacked chip packaging with heat sink struct
US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US20090065902A1 (en) * 2007-09-11 2009-03-12 Cheemen Yu Method of forming a semiconductor die having a sloped edge for receiving an electrical connector
KR20090055316A (ko) * 2007-11-28 2009-06-02 삼성전자주식회사 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
JP2009164160A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体デバイス積層体および実装方法
US8178978B2 (en) * 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
KR100997787B1 (ko) 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
JP4776675B2 (ja) * 2008-10-31 2011-09-21 株式会社東芝 半導体メモリカード
US8476749B2 (en) * 2009-07-22 2013-07-02 Oracle America, Inc. High-bandwidth ramp-stack chip package
US8290319B2 (en) * 2010-08-25 2012-10-16 Oracle America, Inc. Optical communication in a ramp-stack chip package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI698809B (zh) * 2017-08-24 2020-07-11 美商谷歌有限責任公司 用於三維堆疊式神經網路加速器之良率改善
US10963780B2 (en) 2017-08-24 2021-03-30 Google Llc Yield improvements for three-dimensionally stacked neural network accelerators
US11836598B2 (en) 2017-08-24 2023-12-05 Google Llc Yield improvements for three-dimensionally stacked neural network accelerators
US12292473B2 (en) 2017-08-24 2025-05-06 Google Llc Yield improvements for three-dimensionally stacked neural network accelerators

Also Published As

Publication number Publication date
EP2612356B1 (en) 2015-04-22
US8283766B2 (en) 2012-10-09
WO2012030470A2 (en) 2012-03-08
JP2013536999A (ja) 2013-09-26
US20120056327A1 (en) 2012-03-08
JP6000952B2 (ja) 2016-10-05
WO2012030470A3 (en) 2012-05-03
CN103403865A (zh) 2013-11-20
EP2612356A2 (en) 2013-07-10
TW201234501A (en) 2012-08-16
CN103403865B (zh) 2016-08-03
KR101853754B1 (ko) 2018-06-20
KR20130136446A (ko) 2013-12-12

Similar Documents

Publication Publication Date Title
TWI527132B (zh) 晶片封裝，電子計算裝置及用以傳遞信號之方法
TWI520305B (zh) 斜坡堆疊晶片封裝中之光學通訊
KR101807743B1 (ko) 램프 스택 칩 패키지를 위한 픽스쳐 제조
US8390109B2 (en) Chip package with plank stack of semiconductor dies
US8772920B2 (en) Interconnection and assembly of three-dimensional chip packages
CN102484108B (zh) 高带宽倾斜叠层芯片封装
US7932607B2 (en) Composite conductive film and semiconductor package using such film
CN111223829A (zh) 半导体封装
GB2500380A (en) Arrangement and method of making electrical connections
US20250210568A1 (en) Redistribution layer structure for high-density semiconductor package assembly
CN119480825B (zh) 中介层及其制造方法、立体封装结构及其制造方法