CN103378168A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN103378168A
CN103378168A CN2013101288717A CN201310128871A CN103378168A CN 103378168 A CN103378168 A CN 103378168A CN 2013101288717 A CN2013101288717 A CN 2013101288717A CN 201310128871 A CN201310128871 A CN 201310128871A CN 103378168 A CN103378168 A CN 103378168A
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理崎智光
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Ablic Inc
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Abstract

本发明提供一种半导体装置,该半导体装置包含钳位二极管,并具有:设置在半导体衬底(6)上的耐压调整用第一导电型低浓度区域(5);圆形的第二导电型高浓度区域(1),其设置在耐压调整用第一导电型低浓度区域(5)内;环状的元件分离用绝缘膜(2),其在耐压调整用第一导电型低浓度区域(5)内,被设置成以不与第二导电型高浓度区域(1)相接的方式围住第二导电型高浓度区域(1);第一导电型高浓度区域(3),其在耐压调整用第一导电型低浓度区域(5)内,设置在元件分离用绝缘膜(2)的环以外。提供一种具有钳位二极管的半导体装置,该钳位二极管的经时劣化、晶片面内偏差、晶片间偏差、批次间偏差以及击穿前的泄漏小。

Description

半导体装置
技术领域
本发明涉及半导体装置。尤其涉及在半导体装置中使用的钳位二极管。
背景技术
在半导体装置中使用的钳位二极管是利用p型半导体和n型半导体之间的结耐压来使提供给电路的电压固定(钳位)的器件。钳位二极管是能够简便地限制电压的器件,其需求较大,在电子设备中被广泛使用。
在钳位二极管的制造中,在固定地限制电压的钳位二极管中,耐压的晶片(wafer)面内偏差、晶片间偏差以及批次(lot)间偏差较小,经时变化较小的这一点显得非常重要。此外,减小击穿前的漏电流也是重要的一点。虽然是简单的结构,但以满足全部上述特性的方式制造钳位二极管并非易事。
在专利文献1中公开了用于改善上述经时变化的发明。图7表示在专利文献1的图1中所示的结构的剖视图。如图7所示,记载有:使第二导电型高浓度区域1距离元件分离用绝缘膜2预定的距离,此外,经由绝缘膜9设置电极8,调整所述电极8的电压,由此,可以改善钳位二极管的经时变化。此外,图8示出该文献的图6所示的结构的剖视图。如该结构所示,记载有即使在没有图7中的电极8的情况下,也得到相同的效果。
在先技术文献
专利文献
专利文献1:日本特开平11-307787号公报
发明内容
但是,虽然专利文献1所示的发明改善了经时变化,但是专利文献1并没有涉及晶片面内偏差、晶片间偏差和批次间偏差大小以及击穿前有无泄漏。实际上,在专利文献1所示的发明中,由于以下的理由,晶片面内偏差、晶片间偏差以及批次间偏差并未减少。
在图7的结构中,将与施加于电极8的电压对应的电场经由氧化膜9施加于pn结,因此,电场是固定的,看起来pn结耐压不变动。认为理想的是如果将相同大小的电压施加于电极8则耐压相同,但是实际上,在晶片面内、晶片之间以及批次之间,氧化膜9的厚度并不相同,在电极8的电压施加于pn结而形成的电场中会产生偏差。因此,pn结耐压具有偏差。
此外,在图7以及图8中所具有的元件分离用绝缘膜2的下面,存在第一导电型区域7,因此,该杂质会给pn结附近的杂质分布带来影响,使pn结的耐压发生变化。这是因为,在理想情况下,如果在相同的条件下作成第一导电型区域7,则pn结的耐压应该相同,但是实际上,由于在晶片面内、晶片之间以及批次之间,第一导电型区域7的浓度并不相同,所以对pn结耐压的影响程度具有偏差,其结果是,pn结耐压具有偏差。
此外,根据专利文献1的话,图7的第二导电型高浓度区域1的平面形状是8边形(本说明书中未图示)。在这样存在折角的结构中,由于电场强度在折角部变强,所以根据其折角部决定耐压。图9示出第二导电型高浓度区域1的平面形状为矩形的情况下以及圆形的情况下的耐压。这样,很清楚的是,与圆形相比,具有矩形的第二导电型区域1的钳位二极管的耐压较低。也就是说,很清楚的是,电场集中于矩形的折角部,其折角部决定耐压。理想的是,如果在相同的条件下进行光刻,则折角部的形状始终相同,因此pn结的耐压应相同,但是实际上,在晶片面内、晶片之间以及批次之间,折角部的电场强度具有偏差,结果pn结耐压具有偏差。
这样,使pn结的耐压具有偏差的因素较多,为了抑制这些偏差,需要尽可能地简化结构,将成为偏差的主要原因的要素减少到极限。
本发明是鉴于上述课题而完成的,提供一种钳位二极管,该钳位二极管抑制了经时劣化、晶片面内偏差、晶片间偏差、批次偏差以及击穿前的泄漏。
为了解决上述课题,包含本发明所涉及的钳位二极管的半导体装置具有:设置在半导体衬底上的耐压调整用第一导电型低浓度区域;圆形的第二导电型高浓度区域,其设置在所述耐压调整用第一导电型低浓度区域内;环状的元件分离用绝缘膜,其在所述耐压调整用第一导电型低浓度区域内,被设置成以不与所述第二导电型高浓度区域相接的方式围住所述第二导电型高浓度区域;第一导电型高浓度区域,其在所述耐压调整用第一导电型低浓度区域内,设置在元件分离用绝缘膜的环以外。
通过使用上述的单元,能够提供一种经时劣化、晶片面内、晶片间、批次间偏差以及击穿前的泄漏小的钳位二极管。
附图说明
图1是示出本发明的代表例的图。
图2是示出钳位二极管中的泄漏特性的图。
图3是示出本发明的变形例1的图。
图4是示出本发明的变形例2的图。
图5是示出本发明的变形例4的图。
图6是示出本发明的变形例5的图。
图7是示出现有技术的实施例的图。
图8是示出现有技术的其它实施例的图。
图9是示出钳位二极管中的电流电压特性与第二导电型高浓度区域1形状的依赖性的图。
标号说明
1第二导电型高浓度区域
2元件分离用绝缘膜
3第一导电型高浓度区域
4触点
5耐压调整用第一导电型低浓度区域
6半导体衬底
7第一导电型区域
8电极
9绝缘膜
具体实施方式
以下,使用附图对用于实施发明的方式进行说明。
图1是示出半导体装置中的钳位二极管的第一实施方式的图。图1(a)示出俯视图,图1(b)示出沿着该图(a)的线A-A’的剖视图。
耐压调整用第一导电型低浓度区域5设置在半导体衬底6的表面,具有与耐压调整用第一导电型低浓度区域5相反的导电型的第二导电型高浓度区域1在耐压调整用第一导电型低浓度区域5的表面的部分,在俯视图中设置成圆形。在耐压调整用第一导电型低浓度区域5的表面上以不与第二导电型高浓度区域1相接的方式围住第二导电型高浓度区域1地设置有环(ring)状的元件分离用绝缘膜2。此处,环状并非一定是圆环形状或者圈(doughnut)形状,元件分离用绝缘膜2的环状的内侧部分的形状为圆形,但是其外形在本实施例中为矩形。此外,在耐压调整用第一导电型低浓度区域5上,以围住元件分离用绝缘膜2的方式设置有矩形的第一导电型高浓度区域3。第二导电型高浓度区域1和第一导电型高浓度区域3的表面被绝缘膜覆盖,并分别经由触点4与不同的配线连接。
当在第一导电型高浓度区域3与第二导电型高浓度区域1之间施加电压时,由于第二导电型高浓度区域1与耐压调整用第一导电型低浓度区域5之间的pn结的击穿而将电压钳位于固定的电压。根据目的,半导体装置可以仅包含钳位二极管,有时也可以包含由钳位二极管以外的晶体管等构成的电路。
<效果1>发明人发现:如本发明的图1所示,由于第二导电型高浓度区域1被设置为不与元件分离用绝缘膜2相接,所以如专利文献1中所述那样,得到抑制经时劣化的效果,但是不仅如此,还能够得到抑制pn结的耐压以下的电压下的泄漏电流的效果。图2是示出钳位二极管的电压电流特性的曲线图。图2的曲线图中的“不相接”示出图1所示的第二导电型高浓度区域1不与元件分离用绝缘膜2相接的结构,“相接”示出第二导电型高浓度区域1与元件分离用绝缘膜2相接的结构。这样,“不相接”结构与“相接”结构相比,泄漏电流小。发明者推测,其原因是,如果形成与第二导电型高浓度区域1相接的元件分离用绝缘膜2,则在元件分离用绝缘膜2与耐压调整用第一导电型低浓度区域5之间会产生形变,从而在耐压调整用第一导电型低浓度区域5的禁帯中生成能级,该能级消解而产生电流,因此,在第二导电型高浓度区域1与元件分离用绝缘膜2相接的结构中,泄漏电流大。
因此,在本发明的图1中,不但得到专利文献1的经时劣化的抑制效果,还得到抑制作为课题之一的、泄漏电流的效果。
<效果2>在本发明的图1中,由于不存在现有结构的图7所示的电极8以及绝缘膜9,所以不再存在作为课题之一的从电极8传给pn结耐压的电场偏差,结果pn结耐压的偏差减小。
<效果3>在本发明的图1中,由于不存在现有结构的图7以及图8中所具有的第一导电型区域7,所以消除了作为课题之一的、对第一导电型区域7的pn结耐压的影响程度的偏差,结果pn结耐压的偏差结合效果2而进一步减小。
<效果4>在本发明的图1中,由于第二导电型高浓度区域1的平面形状是圆形而不存在折角,所以消除了作为课题之一的、第二导电型高浓度区域1的折角部中的偏差所导致的电场强度的偏差,结果pn结耐压的偏差结合效果2和3而进一步减小。
<变形例1>图3示出本发明的变形例1的俯视图。图3是元件分离绝缘膜2面向第二导电型高浓度区域1的部分的平面形状为矩形的情况。这样,只要第二导电型高浓度区域1不与元件分离绝缘膜2相接,即使元件分离离绝缘膜2的平面形状不是图1所示的圆形而是矩形或6边形等,也能得到上述效果1至4。
<变形例2>图4(a)示出本发明的变形例2的俯视图,图4(b)示出沿该图(a)的线段B-B’的剖视图。在图4所示的例中,不存在图3所示的元件分离绝缘膜2。这样,即使在不存在元件分离离绝缘膜2的情况下,也能得到上述效果1至4。
<变形例3>在图1、图3以及图4中,第一导电型高浓度区域3被配置为矩形的环状。即使第一导电型高浓度区域3是矩形以外的形状、或者不是环状,也能得到上述效果1~效果4的效果。
<变形例4>此外,在钳位二极管中,为了在任何电流带下都固定于相同的电压,要求陡峭的击穿特性。为了得到该陡峭的击穿特性,减少寄生电阻即可,但是,在本发明中,通过缩短第二导电型高浓度区域1与第一导电型高浓度区域3之间的距离来减少耐压调整用第一导电型低浓度区域5的寄生电阻,从而能够得到陡峭的击穿特性。
图5(a)示出将该耐压调整用第一导电型低浓度区域5的寄生电阻减少到极限的图1的型的钳位二极管的俯视图,图5(b)示出图4的类型的钳位二极管的俯视图。
如图所示,元件分离绝缘膜2和第一导电型高浓度区域3的环状均为由圆形构成的圆环形状,并将各自的尺寸设定为设计规格的最小值,由此,能够将耐压调整用第一导电型低浓度区域5的寄生电阻减少至极限,从而能够得到最陡峭的击穿特性。
<变形例5>图6(a)和(b)是对图5(a)和(b)进行变形后的钳位二极管的俯视图。这样,即使第一导电型高浓度区域3的环状的外侧的部分成为圆形以外的形状,由于耐压调整用第一导电型低浓度区域5的寄生电阻与图5相同,所以得到与变形例4相同的效果。
<变形例6>在上述全部的本发明中,元件分离绝缘膜2假定为LOCOS,但是即使该元件分离绝缘膜2为STI(Shallow Trench Isolation:浅沟槽隔离),也得到相同的效果。这样,本发明不限于上述实施方式,在不脱离其要旨的范围内,可进行变形来实施本发明。

Claims (6)

1.一种半导体装置,其特征在于,具有:
半导体衬底;
设置在所述半导体衬底上的耐压调整用第一导电型低浓度区域;
圆形的第二导电型高浓度区域,其设置在所述耐压调整用第一导电型低浓度区域内的表面附近;
具有环形状的元件分离用绝缘膜,其在所述耐压调整用第一导电型低浓度区域内的表面上,被设置成以不与所述第二导电型高浓度区域相接的方式围住所述第二导电型高浓度区域;以及
第一导电型高浓度区域,其在所述耐压调整用第一导电型低浓度区域内,设置在所述元件分离用绝缘膜的外侧。
2.根据权利要求1所述的半导体装置,其特征在于,
所述第一导电型高浓度区域被设置成具有环形状、且围住所述元件分离用绝缘膜。
3.根据权利要求2所述的半导体装置,其特征在于,
所述元件分离用绝缘膜的环形状是圆环形状,
所述第一导电型高浓度区域的环形状的至少内侧部分是圆形。
4.一种半导体装置,其特征在于,具有:
半导体衬底;
设置在所述半导体衬底上的耐压调整用第一导电型低浓度区域;
圆形的第二导电型高浓度区域,其设置在所述耐压调整用第一导电型低浓度区域内的表面附近;以及
第一导电型高浓度区域,其在所述耐压调整用第一导电型低浓度区域内的表面上,被设置成不与所述第二导电型高浓度区域相接。
5.根据权利要求4所述的半导体装置,其特征在于,
所述第一导电型高浓度区域具有环形状,并被设置成围住所述第二导电型高浓度区域。
6.根据权利要求5所述的半导体装置,其特征在于,
所述第一导电型高浓度区域的环形状的至少内侧部分是圆形。
CN201310128871.7A 2012-04-17 2013-04-15 半导体装置 Active CN103378168B (zh)

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JPH06104455A (ja) * 1992-09-21 1994-04-15 Hitachi Ltd pn接合ダイオードおよびこれを用いた半導体集積回路装置
EP0643418B1 (en) * 1993-09-10 1998-12-02 STMicroelectronics S.r.l. Process for the manufacture of a Zener Diode for flash-EEPROM devices
JPH08227999A (ja) * 1994-12-21 1996-09-03 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタ及びその製造方法並びに半導体集積回路及びその製造方法
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JP3730394B2 (ja) * 1997-03-18 2006-01-05 株式会社東芝 高耐圧半導体装置
JP3472476B2 (ja) 1998-04-17 2003-12-02 松下電器産業株式会社 半導体装置及びその駆動方法
JP3905981B2 (ja) * 1998-06-30 2007-04-18 株式会社東芝 高耐圧半導体装置
JP4016595B2 (ja) * 2000-12-12 2007-12-05 サンケン電気株式会社 半導体装置及びその製造方法
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
TW560042B (en) * 2002-09-18 2003-11-01 Vanguard Int Semiconduct Corp ESD protection device
JP4469584B2 (ja) * 2003-09-12 2010-05-26 株式会社東芝 半導体装置
JP2007134596A (ja) * 2005-11-11 2007-05-31 Matsushita Electric Ind Co Ltd サージ保護用半導体装置
JP5493435B2 (ja) * 2009-04-08 2014-05-14 富士電機株式会社 高耐圧半導体装置および高電圧集積回路装置
JP5012978B2 (ja) * 2009-09-30 2012-08-29 株式会社デンソー 半導体装置およびその製造方法

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