CN103314649A - 将高密度多层薄膜转移及电接合至电路化且柔性的有机衬底的方法及相关联装置 - Google Patents

将高密度多层薄膜转移及电接合至电路化且柔性的有机衬底的方法及相关联装置 Download PDF

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CN103314649A
CN103314649A CN2011800645985A CN201180064598A CN103314649A CN 103314649 A CN103314649 A CN 103314649A CN 2011800645985 A CN2011800645985 A CN 2011800645985A CN 201180064598 A CN201180064598 A CN 201180064598A CN 103314649 A CN103314649 A CN 103314649A
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layer
electric conductor
substrate
lcp
interconnection layer
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CN103314649B (zh
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迈克尔·韦瑟斯庞
戴维·尼科尔
路易斯·约瑟夫·小伦代克
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L3 Hershey Technology Co
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Harris Corp
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种方法用于制造电子装置且包含形成互连层堆叠，所述互连层堆叠在牺牲衬底上，且具有多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层。所述方法还包含在所述互连层堆叠的与所述牺牲衬底相对的一侧上将液晶聚合物LCP衬底层压至且经由金属间结合电接合至所述互连层堆叠。所述方法进一步包含移除所述牺牲衬底以暴露最下的经图案化的电导体层，以及将至少一个第一装置电耦合至所述最下的经图案化的电导体层。

Description

将高密度多层薄膜转移及电接合至电路化且柔性的有机衬底的方法及相关联装置
技术领域
本发明涉及电子装置制造的领域，且更特定来说，涉及在牺牲衬底上形成电子装置的部分且将电子装置的所述部分电接合至电路化的薄柔性有机衬底的方法。
背景技术
随着半导体及集成电路技术进步，已存在朝着具有众多输入及输出(I/O)衬垫的高功能性集成电路组件发展的趋势，以及对减小的芯片大小、重量及功率消耗的需求。因此，随着集成电路变得更小，集成电路日益具有比先前更紧密地配置在一起的更小I/O衬垫。
为了匹配这些高功能性集成电路，存在对具有用于集成电路组件附接的紧密配置的衬垫的印刷线路板的需求。至今，制造具有足够细微的间距的组件附接衬垫的衬底的能力已不能够跟上集成电路组件的小型化。因此，对于一些现代装置来说，存在互连技术差距。
为了使所述装置起作用，印刷线路板可具有用以处置集成电路的衬垫的额外布线层或利用扇出封装。此情形导致集成电路的封装大小比集成电路自身大，此情形可限制系统小型化。除对小型化装置的这些需求之外，在一些状况下还需要由柔性而非硬质的衬底来建构这些装置。
现用作衬底(由所述衬底来建构薄的且柔性的印刷线路板)的材料为双轴定向的液晶聚合物(LCP)。LCP中的分子具有硬质、杆状形状，且在处于液相中时或在加热及熔化时维持结晶次序。液晶聚合物印刷电路的处理及组装(The Processing and Assembly ofLiquid Crystalline Polymer Printed Circuits)(T.Zhang、W.Johnson、B.Farrell及M.St.Lawrence，“液晶聚合物印刷电路的处理及组装(The processing and assembly of liquidcrystalline polymer printed circuits)”，2002年，国际微电子研讨会2002)论述了使用LCP作为衬底的印刷电路板的建构。首先将光阻剂涂覆至覆铜叠层，将所述光阻剂暴露且显影以界定所要的电路图案。通过任何经暴露的铜的蚀刻移除来界定实际电路。经由机械或激光钻孔在衬底中形成孔或通孔。执行去污步骤以自通孔或孔移除碎屑，由此制备用于金属沉积的LCP材料。接下来执行金属化步骤，且将常规焊料光罩施加至LCP衬底。接着经由常规焊料光罩涂覆焊料以完成LCP印刷电路板的建构。
虽然此设计确实允许形成薄的柔性印刷电路板，但其仍遭受与上文关于具有紧密隔开的衬垫的集成电路的附接所描述的缺点相同的缺点。
传统半导体处理技术允许制造硬质晶片衬底，所述硬质晶片衬底将支撑上文所参考的所附接组件的层级。在此工艺中，将金属自气相沉积为极薄的膜，且以类似于针对印刷电路板所描述的方式的方式来光刻图案化及蚀刻所述金属。经由旋涂或气相沉积工艺在金属层之间形成介电层。虽然允许细微间距的组件的附接，但此方法归因于用于半导体处理的硬质晶片衬底要求而缺乏达成柔性电路的能力。因而，需要将集成电路连接至柔性印刷电路板的额外方法。
发明内容
鉴于前述背景，因此，本发明的目标为提供一种将制造于牺牲硬质晶片衬底上的高密度多层薄膜转移及电接合至柔性电路化液晶聚合物衬底的方法。
通过一种制造电子装置的方法来提供根据本发明的此目标、特征及优点及其它目标、特征及优点，所述方法包含在牺牲衬底上形成互连层堆叠，所述互连层堆叠包括多个交替图案化的导电层及介电层。所述方法还包含在所述互连层堆叠的与所述牺牲衬底相对的一侧上将电路化的液晶聚合物(LCP)衬底层压至且电接合至所述互连层堆叠，以及移除所述牺牲衬底以暴露最下的经图案化的电导体层。所述方法进一步包含将至少一个第一装置电耦合至所述最下的经图案化的电导体层。此方法有利地允许在难以形成于电路化的LCP衬底上的互连层堆叠上形成电子装置。
将所述LCP衬底与所述互连层堆叠层压在一起可包括将热及压力施加至所述LCP衬底及所述互连层堆叠。所述热及压力可在高压釜中施加。
形成所述互连层堆叠可通过以薄膜沉积形成所述多个经图案化的电导体层来执行。另外，所述LCP衬底可相对较薄，也就是说，所述LCP衬底可具有小于0.0025英寸的厚度。另外，所述至少一个第一装置可包含呈倒装芯片布置的第一集成电路(IC)裸片。
可在所述LCP衬底中形成至少一个电导体通孔。可将至少一个第二装置连接至所述LCP衬底，且可使用所述至少一个电导体通孔将所述至少一个第二装置电耦合至最上的经图案化的电导体层。
所述牺牲衬底可为玻璃或任何原子平滑材料。所述LCP衬底中可具有至少一个电导体通孔，且所述方法还可包含形成另一互连层堆叠，所述另一互连层堆叠在另一牺牲衬底上，且包括多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层。可在所述LCP衬底的与所述另一牺牲衬底相对的一侧上将所述另一互连层堆叠层压至且电接合至所述LCP衬底。
可移除所述另一牺牲衬底以暴露最下的经图案化的电导体层。所述方法可进一步包含将至少一个其它装置电耦合至所述最下的经图案化的电导体层，以及将所述互连层堆叠与所述另一互连层堆叠电耦合在一起。
在一些应用中，所述LCP衬底可具有大于所述牺牲衬底的面积的面积，且可将至少一个其它LCP衬底层压至所述LCP衬底，所述至少一个其它LCP衬底中具有与所述至少一个第一装置对准的孔隙。
可在所述至少一个额外LCP衬底中形成至少一个电导体通孔。可形成另一互连层堆叠，所述另一互连层堆叠在另一牺牲衬底上，且包括多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层。可在另一LCP衬底的与所述另一牺牲衬底相对的一侧上将所述另一互连层堆叠层压至且电接合至所述另一LCP衬底，且可移除所述另一牺牲衬底以暴露最下的经图案化的电导体层。
可将至少一个其它装置电耦合至所述最下的经图案化的电导体层。可将所述另一LCP衬底层压至所述至少一个额外LCP衬底。可使用所述至少一个额外LCP衬底中的所述至少一个电导体通孔来电耦合所述互连层堆叠与所述另一互连层堆叠。
所述LCP衬底可包括在多个LCP层中的每一者中的至少一个导体通孔，且所述方法可包括使所述LCP衬底与所述互连层堆叠对准，将所述LCP衬底层压至及电接合至所述互连层堆叠。可将所述多个LCP层中的其余LCP层层压至已层压至所述互连堆叠的所述LCP层。可使用所述多个LCP层中的每一者的所述至少一个电导体通孔将至少一个第二装置电耦合至所述最上的经图案化的电导体层。
一装置方面是针对一种电子装置，所述电子装置包括液晶聚合物(LCP)衬底。在所述LCP衬底上存在互连层堆叠，所述互连层堆叠包括多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层，所述介电层包括不同于LCP的材料。在所述LCP衬底与所述互连层堆叠之间存在熔融接缝。另外，在所述LCP衬底与所述所附接的互连层堆叠之间存在电互连。至少一个第一装置电耦合至最下的经图案化的电导体层。
附图说明
图1为根据本发明的制造电子装置的方法的流程图。
图2A至2D为如经由图1中所展示的方法所形成的本发明的电子装置的连续示意性横截面图。
图3为根据本发明的制造电子装置的方法的另一实施例的流程图。
图4A至4E为如经由图3中所展示的方法所形成的本发明的电子装置的连续示意性横截面图。
图5为根据本发明的制造电子装置的方法的另一实施例的流程图。
图6A至6E为如经由图5中所展示的方法所形成的本发明的电子装置的连续示意性横截面图。
图7为根据本发明的制造电子装置的方法的又一实施例的流程图。
图8A至8E为如经由图7中所展示的方法所形成的本发明的电子装置的连续示意性横截面图。
图9为根据本发明的制造电子装置的方法的再一实施例的流程图。
图10A至10E为如经由图9中所展示的方法所形成的本发明的电子装置的连续示意性横截面图。
具体实施方式
现将在下文中参看随附图式来更完全地描述本发明，本发明的优选实施例展示于所述随附图式中。然而，本发明可以许多不同形式来体现且不应被解释为限于本文中所阐述的实施例。确切地说，提供这些实施例以使得本发明将为详尽的及完整的，且将本发明的范围完全地传达给所属领域的技术人员。贯穿各图，相同数字指代相同元件。
最初参看图1的流程图50及图2A至2D，现描述制造电子装置的方法。如图2A中所展示，在开始(框51)之后，在牺牲衬底12上形成互连层堆叠14(在框52处)。所述互连层堆叠14包括多个交替图案化的电导体层16与在邻近的经图案化的电导体层之间的介电层17。介电层17可为聚酰亚胺。牺牲衬底12提供用于形成互连层堆叠14的尺寸稳定性及原子平滑度。
举例来说，互连层堆叠14可薄于0.0004英寸，其中经图案化的电导体层16小至(或甚至小于)0.00004英寸，且介电层17小至(或小于)0.00016英寸。牺牲衬底12优选为玻璃，但也可使用具有足够平滑的表面的其它材料。可通过半导体薄膜沉积工艺来形成互连层堆叠14及(因此)所述多个经图案化的电导体层16。
如图2B中所展示，在互连层堆叠14的与牺牲衬底12相对的侧上将液晶聚合物(LCP)衬底18层压至互连层堆叠14(在框53处)。举例来说，LCP衬底18可具有小于0.0025英寸的厚度。此层压是经由将热及压力施加至LCP衬底18及互连层堆叠14(例如，在高压釜中)来执行。高压釜有利地提供均衡压力(也就是说，来自所有方向的相等压力)，且帮助阻止LCP在层压工艺期间变形。虽然将高压釜用于层压是优选的，但也可使用压机(有可能在惰性气氛下)来执行层压。所述层压优选在约260℃及100psi下执行。
出于多种原因，LCP为用以形成印刷电路板的特别有利的材料，所述多种原因包含以下事实：LCP具有高拉伸强度，从而提供高耐磨损性及高耐损害性。通常，LCP还具有高温下的高机械强度、高耐化学性、固有的阻燃性及良好的耐气候性。另外，LCP相对来说较具惰性。LCP耐受在高温下在存在大多数化学物质的情况下的应力破裂性，所述化学物质包含芳族烃或卤化烃、强酸、碱、酮及其它侵蚀性工业物质。所属领域的技术人员应理解，存在可用于生产根据本发明的电子装置的多种LCP。将LCP用作衬底18有利地允许在无黏着层的情况下的层压，由此减小所得电子装置10的总厚度。
接下来，如图2C中所展示，移除牺牲衬底12，由此暴露最下的经图案化的电导体层16(框54)。举例来说，此牺牲衬底12的移除是通过在氢氟酸中的溶解、机械抛光或化学机械抛光的组合来执行。
如图2D中所展示，将至少一个第一装置20(说明性地为三个装置)耦合至所述最下的经图案化的电导体层16(框55)。如所属领域的技术人员将了解，此装置20可为集成电路(IC)裸片，且可耦合成倒装芯片布置。框56指示所述方法的结束。
所述方法因此产生电子装置10，所述电子装置10包括LCP衬底18与形成于LCP衬底18上的互连层堆叠14。所述互连层堆叠14包括多个经图案化的电导体层16与在邻近的经图案化的电导体层之间的介电层17。在互连层堆叠14与LCP衬底18之间存在熔融接缝。此熔融接缝是在LCP衬底及互连层堆叠14的软化及接合期间形成，且在经横截的装置的像片中可容易地见到。三个集成电路裸片20以倒装芯片布置耦合至最下的经图案化的电导体层16。应了解，可改为存在任何数目个装置20，且所述装置20无需为集成电路裸片。
参看图3的流程图150及图4A至4E，现描述根据本发明的制造电子装置110的方法的另一实施例。应理解，可以类似于图1的流程图50中的步骤的方式来执行此方法中的步骤，且那些步骤的详细描述因此为不必要的。
如图4A中所展示，在开始(框151)之后，使用薄膜沉积在牺牲衬底112上形成互连层堆叠114(在框152处)。所述互连层堆叠114包括多个经图案化的电导体层116以及在邻近的经图案化的电导体层之间的介电层117。在最上的介电层117中界定孔隙，以便通过所述孔隙暴露最上的经图案化的电导体层116的衬垫。
接下来，如图4B中所展示，在LCP衬底118中形成至少一个电导体通孔122(说明性地为多个电导体通孔)(框153)。通过对所述LCP衬底118进行机械或激光钻孔而形成电导体通孔122，接着在所得孔中选择性地沉积铜。接着在电导体通孔122的最下层上沉积锡。
在层压之前，可使LCP衬底118与互连层堆叠114对准。将对准定义为：使导电通孔122定中心于最上的经图案化的电导体层116的衬垫中。此对准可通过以下操作来执行：首先使用夹具或导引件来使LCP衬底118与互连层堆叠114粗略对准，且接着在显微镜下精细地调整所述对准以达到最终对准。此情形有利地允许在0.0005英寸至0.001英寸的范围中的位置对准准确度。
如图4C中所展示，接着在互连层堆叠114的与牺牲衬底112相对的侧上将LCP衬底118层压至且电接合至互连层堆叠114(框154)。在层压工艺步骤期间，温度达到例如260℃等合适水平，所述温度水平为锡的熔点且在所述点处，铜及锡扩散且起反应以形成例如Cu3Sn等金属间化合物。负责建立LCP衬底与互连层堆叠之间的电连接的此金属间化合物在其至少600℃的熔点以下为热稳定的。有利地，成功层压与金属间化合物形成所需要的温度属于相同范围内。
如图4D中所展示，接着移除牺牲衬底112以暴露最下的经图案化的电导体层116(框155)。如图4E中所展示，将至少一个第一装置120(说明性地为三件组装置)电耦合至最下的经图案化的电导体层116(框156)。三件组装置120可为呈倒装芯片布置的集成电路裸片，但也可为其它装置。使用电导体通孔122将至少一个第二装置124电耦合至互连层堆叠114的最上的经图案化的电导体层116(框157)。此情形提供装置120、124之间的连接性。
应了解，装置120、124可为不同种类的装置。举例来说，装置120可为数字逻辑电路，而装置124可为模拟射频电路。框158指示所述方法的结束。
此方法因此产生电子装置110，电子装置110包括LCP衬底118，LCP衬底118中形成有多个导体通孔122。互连层堆叠114形成于LCP衬底118上。互连层堆叠114包括多个经图案化的电导体层116与在邻近的经图案化的电导体层之间的介电层117。在互连层堆叠114与LCP衬底118之间存在熔融接缝。三个集成电路裸片120以倒装芯片布置耦合至最下的经图案化的电导体层116。射频装置124经由电导体通孔122而电耦合至最上的经图案化的电导体层116且电耦合至集成电路裸片120。
参看图5的流程图250及图6A至6E，现描述根据本发明的制造电子装置210的方法的另一实施例。应理解，以类似于图1及3的流程图50及150中的步骤的方式来执行此方法中的步骤，且那些步骤的详细描述因此为不必要的。
如图5A中所展示，在开始(框251)之后，使用薄膜沉积在牺牲衬底212上形成互连层堆叠214(在框252处)。所述互连层堆叠214包括多个经图案化的电导体层216，及在邻近的经图案化的电导体层之间的介电层217。在最上的介电层217中界定孔隙，以便通过所述孔隙暴露最上的经图案化的电导体层216的衬垫。
接下来，如图5B中所展示，在LCP衬底218中形成至少一个电导体通孔222(说明性地为多个电导体通孔)(框253)。如图6C中所展示，接着经由金属间结合在互连层堆叠214的与牺牲衬底212相对的侧上将LCP衬底218层压至且电接合至互连层堆叠214(框254)。
如图6C中所展示，在另一牺牲衬底232上形成另一互连层堆叠234(框255)。此另一互连层堆叠234同样包括多个经图案化的电导体层236以及在邻近的经图案化的电导体层之间的介电层237。接着在LCP衬底218的与互连层堆叠214相对的侧上将此另一互连层堆叠235层压至且电接合至LCP衬底218(框256)，由此将所述互连层堆叠与所述另一互连层堆叠电耦合在一起。如图6D中所展示，接着分别移除牺牲衬底212、232两者以暴露互连层堆叠214及互连层堆叠234的最下的经图案化的电导体层216、236(框257)。
如图6E中所展示，将至少一个第一装置220电耦合至互连层堆叠214的最下的经图案化的电导体层216(框258)。接着将至少一个其它装置250(说明性地为两个装置)电耦合至互连层堆叠234的最上的经图案化的电导体层236(框259)。
如图6E中所展示，此方法因此产生电子装置210，所述电子装置210包括LCP衬底218，所述LCP衬底218中形成有多个导体通孔222。互连层堆叠214及另一互连层堆叠234形成于LCP衬底218的相对侧上。所述互连层堆叠214、234各自包括多个经图案化的电导体层216、236与在邻近的经图案化的电导体层之间的介电层217、237。在每一互连层堆叠214、234与LCP衬底218之间存在熔融接缝。集成电路裸片220以倒装芯片布置耦合至最下的经图案化的电导体层216。一对集成电路裸片250经由电导体通孔222而电耦合至最上的经图案化的电导体层236且电耦合至集成电路裸片220。
参看图7的流程图350及图8A至8E，现描述根据本发明的制造电子装置310的方法的另一实施例。应理解，以类似于图1、图3、图5的流程图50、150、250中的步骤的方式来执行此方法中的步骤，且那些步骤的详细描述因此为不必要的。
如图8A中所展示，在开始(框351)之后，使用薄膜沉积在牺牲衬底312上形成互连层堆叠314(在框352处)。所述互连层堆叠314包括多个经图案化的电导体层316以及在邻近的经图案化的电导体层之间的介电层317。暴露最上的经图案化的电导体层316。
如图8B中所展示，形成液晶聚合物(LCP)衬底318(框353)。在LCP衬底318上选择性地图案化铜特征，且接着在铜上选择性地沉积锡以由此形成电路层324。
如图8C中所展示，层压LCP衬底318且在互连层堆叠314的与牺牲衬底312相对的侧上将LCP衬底318的涂布有锡的铜特征以金属间方式结合至互连层堆叠314(框354)。优选在290℃及100psi下执行层压，但当然可使用其它温度及压力。
移除牺牲衬底312以暴露最下的经图案化的电导体层316(框355)。如图8D中所展示，将至少一个第一装置320电耦合至所述最下的经图案化的电导体层316(框356)。
在至少一个额外LCP衬底328(说明性地为三个额外LCP衬底)中形成至少一个电导体通孔326(框357)。所述额外LCP衬底328中具有与装置320对准的孔隙，所述孔隙是通过激光研磨或机械冲压而形成。将所述额外LCP衬底328层压至LCP衬底318(框358)，优选在270℃及200psi下进行，但可使用其它温度及压力。
在另一牺牲衬底350上形成另一互连层堆叠334。此另一互连层堆叠334也包括多个经图案化的电导体层336以及在邻近的经图案化的电导体层之间的介电层337(框359)。接着将所述另一互连层堆叠334层压至形成有电路层344的另一LCP衬底338且使所述另一互连层堆叠334与所述另一LCP衬底338以金属间方式结合(框360)。接着移除牺牲衬底以暴露最下的经图案化的电导体层336(框361)。
接着将所述另一LCP衬底338层压(框362)至最底的额外LCP衬底328，由此经由电导体通孔326及电路层324、344使互连层堆叠314与所述另一互连层堆叠334电耦合。此情形气密地密封装置320使其免受湿气、灰尘及碎屑影响。接着将至少一个其它装置350耦合至最下的经图案化的电导体层(框363)。
如图8E中所展示，此方法因此产生电子装置310，所述电子装置310包括LCP衬底318，所述LCP衬底318上形成有电路层324。互连层堆叠314与LCP衬底318耦合。所述互连层堆叠314包括多个经图案化的电导体层316与在邻近的经图案化的电导体层之间的介电层317。在每一互连层堆叠314与LCP衬底318之间存在熔融接缝。集成电路裸片320以倒装芯片布置耦合至最下的经图案化的电导体层316。
三个额外LCP衬底层328在与互连层堆叠314相同的侧上层压至LCP衬底318，且所述三个额外LCP衬底层328中界定有与集成电路裸片320对准的孔隙。LCP衬底层328中形成有电导体通孔326。在所述三个额外LCP衬底层328中的每一者之间且在最顶的额外LCP衬底层与LCP衬底318之间存在熔融接缝。
另一LCP衬底338层压至最底的额外LCP衬底层328，且在所述另一LCP衬底338与最底的额外LCP衬底层328之间存在熔融接缝。另一互连层堆叠334层压至所述另一LCP衬底338，且在所述另一互连层堆叠334与所述另一LCP衬底338之间也存在熔融接缝。所述另一互连层堆叠334包括多个经图案化的电导体层336与在邻近的经图案化的电导体层之间的介电层337。另一集成电路裸片350耦合至最下的经图案化的电导体层336。因此，集成电路裸片320与另一集成电路裸片350经由电路层324、344及电导体通孔326而电耦合。集成电路裸片320因此通过环绕的LCP衬底318、328、338而气密地密封。
参看图9的流程图450及图10A至10E，现描述根据本发明的制造电子装置410的方法的另一实施例。应理解，以类似于图1、图3、图5、图7的流程图50、150、250、350中的步骤的方式来执行此方法中的步骤，且那些步骤的详细描述因此为不必要的。
如图10A中所展示，在开始(框451)之后，使用薄膜沉积在牺牲衬底412上形成互连层堆叠414(在框452处)。所述互连层堆叠414包括多个经图案化的电导体层416以及在邻近的经图案化的电导体层之间的介电层417。在最上的介电层417中界定孔隙，以便通过所述孔隙暴露最上的经图案化的电导体层416的衬垫。
接下来，如图10B中所展示，在LCP衬底418的多个LCP层中的每一者中形成至少一个电导体通孔422(说明性地为多个电导体通孔)(框453)。
如图10C中所展示，在互连层堆叠414的与牺牲衬底412相对的侧上将LCP衬底的层418层压至互连层堆叠414(框454)。此结合工艺还用以以金属间方式结合通孔422与经图案化的电导体层416。在层压之前，可使LCP衬底418与互连层堆叠414对准。接着将其余LCP层418层压至已层压至互连层堆叠414的LCP层(框455)。
如图10D中所展示，接着移除牺牲衬底412以暴露最下的经图案化的电导体层416(框456)。如图10E中所展示，将至少一个第一装置420(说明性地为三件组集成电路裸片)电耦合至最下的经图案化的电导体层416(框457)。将至少一个第二装置429(说明性地为RF装置)电耦合至LCP衬底418的导体通孔422，且所述至少一个第二装置429驻留于LCP衬底418的与互连层堆叠414相对的侧上(框458)。框459指示所述方法的结束。
此方法因此产生电子装置410，所述电子装置410包括LCP衬底418，所述LCP衬底418中形成有多个导体通孔422。LCP衬底418包括一对LCP层。互连层堆叠414形成于LCP衬底418上。所述互连层堆叠414包括多个经图案化的电导体层416与在邻近的经图案化的导电层之间的介电层417。在互连层堆叠414与LCP衬底418之间及在LCP层之间存在熔融接缝。
三个集成电路裸片420以倒装芯片布置耦合至最下的经图案化的电导体层416。射频装置429耦合至LCP衬底418的与互连层堆叠414相对的侧，且经由电导体通孔422而电耦合至最上的经图案化的电导体层416及集成电路裸片420。在LCP衬底418与第二装置429之间也存在熔融接缝。

Claims (10)

1.一种制造电子装置的方法，其包括：
形成互连层堆叠，所述互连层堆叠在牺牲衬底上，且包括多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层；
在所述互连层堆叠的与所述牺牲衬底相对的一侧上将液晶聚合物LCP衬底层压至且以金属间方式结合至所述互连层堆叠；
移除所述牺牲衬底以暴露最下的经图案化的电导体层；以及
将至少一个第一装置电耦合至所述最下的经图案化的电导体层。
2.根据权利要求1所述的方法，其中将所述LCP衬底与所述互连层堆叠层压在一起包括将热及压力施加至所述LCP衬底及所述互连层堆叠。
3.根据权利要求2所述的方法，其中施加热及压力是在高压釜中执行。
4.根据权利要求1所述的方法，其中形成所述互连层堆叠包括通过薄膜沉积形成所述多个经图案化的电导体层。
5.根据权利要求1所述的方法，其中所述LCP衬底具有小于0.0025英寸的厚度。
6.根据权利要求1所述的方法，其中所述至少一个第一装置包括呈倒装芯片布置的第一集成电路IC裸片。
7.一种电子装置，其包括：
液晶聚合物LCP衬底；
互连层堆叠，其在所述LCP衬底上，且包括多个经图案化的电导体层以及在邻近的经图案化的电导体层之间的介电层，所述介电层包括不同于LCP的材料；
在所述LCP衬底与所述互连层堆叠之间的熔融接缝；
在所述LCP衬底与所述互连层堆叠之间的金属间结合；以及
至少一个第一装置，其电耦合至最下的经图案化的电导体层。
8.根据权利要求7所述的电子装置，其中所述LCP衬底具有小于0.0025英寸的厚度。
9.根据权利要求7所述的电子装置，其中所述至少一个第一装置包括呈倒装芯片布置的第一集成电路IC裸片。
10.根据权利要求7所述的电子装置，其中所述LCP衬底中具有至少一个电导体通孔；且所述电子装置进一步包括至少一个第二装置，所述至少一个第二装置在所述LCP衬底上且使用所述至少一个电导体通孔而电耦合至最上的经图案化的电导体层。
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US20140376197A1 (en) 2014-12-25
US8867219B2 (en) 2014-10-21
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