US8536459B2 - Coreless layer buildup structure with LGA - Google Patents

Coreless layer buildup structure with LGA Download PDF

Info

Publication number
US8536459B2
US8536459B2 US12/764,994 US76499410A US8536459B2 US 8536459 B2 US8536459 B2 US 8536459B2 US 76499410 A US76499410 A US 76499410A US 8536459 B2 US8536459 B2 US 8536459B2
Authority
US
United States
Prior art keywords
substrate
per
layer
metal layers
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/764,994
Other versions
US20120160544A1 (en
Inventor
Voya Markovich
Timothy Antesberger
Frank D. Egitto
William Wilson
Rabindra N. Das
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ttm Technologies North America LLC
Original Assignee
i3 Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/764,994 priority Critical patent/US8536459B2/en
Assigned to ENDICOTT INTERCONNECT TECHNOLOGIES, INC. reassignment ENDICOTT INTERCONNECT TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DAS, RABINDRA N., MARKOVICH, VOYA, WILSON, WILLIAM E., ANTESBERGER, TIMOTHY, EGITTO, FRANK D.
Application filed by i3 Electronics Inc filed Critical i3 Electronics Inc
Assigned to PNC BANK, NATIONAL ASSOCIATION reassignment PNC BANK, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: EI TRANSPORTATION COMPANY LLC, ENDICOTT INTERCONNECT TECHNOLOGIES, INC., ENDICOTT MEDTECH, INC.
Publication of US20120160544A1 publication Critical patent/US20120160544A1/en
Assigned to INTEGRIAN HOLDINGS, LLC reassignment INTEGRIAN HOLDINGS, LLC ASSIGNMENT OF SECURITY AGREEMENT Assignors: PNC BANK, NATIONAL ASSOCIATION
Assigned to M&T BANK reassignment M&T BANK SECURITY AGREEMENT Assignors: EI TRANSPORTATION COMPANY LLC, ENDICOTT INTERCONNECT TECHNOLOGIES, INC., ENDICOTT MEDTECH, INC., INTEGRIAN HOLDINGS, LLC
Assigned to MAINES, DAVID, MAINES, WILLIAM reassignment MAINES, DAVID SECURITY AGREEMENT Assignors: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Publication of US8536459B2 publication Critical patent/US8536459B2/en
Application granted granted Critical
Assigned to ENDICOTT INTERCONNECT TECHNOLOGIES, INC. reassignment ENDICOTT INTERCONNECT TECHNOLOGIES, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MAINES, DAVID, MAINES, WILLIAM
Assigned to I3 ELECTRONICS, INC. reassignment I3 ELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Assigned to M&T BANK reassignment M&T BANK SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: I3 ELECTRONICS, INC.
Assigned to TTM TECHNOLOGIES NORTH AMERICA, LLC reassignment TTM TECHNOLOGIES NORTH AMERICA, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: I3 ELECTRONICS, INC.
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/061Lamination of previously made multilayered subassemblies
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4688Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Abstract

A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Description

RELATED APPLICATIONS

The present application is related to co-pending U.S. patent application Ser. No. 12/764,993 for CORELESS LAYER BUILDUP STRUCTURE and co-pending U.S. patent application Ser. No. 12/764,997 for CORELESS LAYER BUILDUP STRUCTURE WITH LGA AND JOINING LAYER, both incorporated by reference herein in their entirety.

FIELD OF THE INVENTION

The present invention relates to circuit board manufacturing and preparation and, more specifically, to a structure wherein a core is built up utilizing at least partially to completely advanced thermoset resin or thermoplastics.

BACKGROUND OF THE INVENTION

A common procedure in circuit board processing involves laminating multiple cores together. However, generally, the cores are not electrically connected via to via during lamination. For example, one method involves first electrically connecting the cores using conductive pads. After lamination, a hole is drilled through the conductive pads and electroplated with copper to form the via.

An alternative solution uses conductive adhesive to electrically attach vias during lamination. The conductive adhesive is placed onto a via and electrically connects the vias when the cores are laminated together. However, conductive adhesives contain plate-like structures greater than 0.5 mils in size. These plates tend to clog at the top of the holes. Therefore, the adhesives cannot be used effectively with thicker cores and smaller vias. Additionally, conductive adhesives require precious metal for good connections, making the products more expensive. Finally, a substantial number of manufacturing sites are not equipped to handle conductive adhesives. Consequently, significant costs may be required to modify current manufacturing sites to use conductive adhesives.

As a result, there exists a need for a structure and method of attaching cores having vias with conductive surfaces without using a conductive material for the joining process such as that that is currently used.

DISCUSSION OF RELATED ART

U.S. Pat. No. 6,465,084, by Curcio, et al., granted Oct. 15, 2002, and U.S. Pat. No. 6,638,607, by Curcio, et al., granted Oct. 28, 2003 for METHOD AND STRUCTURE FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS disclose a method of forming a core for a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

U.S. Pat. No. 6,969,436 by Curcio, et al., granted Nov. 29, 2005 for METHOD AND STRUCTURE FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS and U.S. Pat. No. 7,303,639, by Curcio, et al., granted Dec. 4, 2007 for METHOD FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS disclose a method of forming a member to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a method and structure of attaching a plurality of cores. A substrate for use in a PC board has a coreless buildup layer and a metal layer and LGA disposed thereon. Optionally, a second metal layer can be provided with a dielectric layer between the two metal layers.

A first aspect of the invention is directed to having coreless buildup layers consisting of thermoset resin. Each or alternate buildup layers are partially advanced to process circuitization and subsequently fully cured during final lamination process. Example of buildup layers: resin coated Cu based on filled epoxy or filled PPE, etc.

A second aspect of the invention is directed to a method having coreless buildup layers consisting of thermoplastics. Each buildup layer is circuitized and subsequently laminated to get final structure. Example of buildup layers: Polyimide, liquid crystal polymer (LCP) or Teflon® based materials. Buildup layers can also be a mixture of thermoplastics such as LCP and polyimide. Here, LCP will melt and form bonding among the buildups. For LCP and Teflon mixtures, LCP will likewise melt and form bonding among the buildups.

A third aspect of the invention is directed to a structure having coreless buildup layers consisting of thermoset and/or thermoplastic resin. Here the thermoset buildup layers are partially advanced to process circuitization and subsequently fully cured during a final lamination process.

A fourth aspect of the invention is directed to a method having coreless buildup layers consist of thermoset and/or thermoplastic resin. Here thermoset buildup layers are fully cured and circuitized. Thermoplastic will melt and form bonding among the buildups.

A fifth aspect of the invention is directed to a method having a metal surface: It can be metal or alloy or their mixture that will diffuse with each other during final bonding. All surfaces, some surfaces, or alternate surface can have low melting point metal or alloy surface finish where low melting melts during or after lamination and form metal-metal bonding.

Another aspect of the invention is directed to a structure that consists of at least one joining layer, wherein joining layers will connect multiple signal layers. Joining multiple signal layers and land grid array (LGA) can be a single step or a multi step process.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:

FIGS. 1-6 show a longitudinal, sectional view, somewhat diagrammatic, of the steps to form a core member according to one embodiment of the present invention;

FIGS. 7 and 8 show the steps of laminating two core members together to form a printed wiring board according to one embodiment of the invention;

FIGS. 9-13 show a longitudinal, sectional view, somewhat diagrammatic, of the steps to form a joining member according to another embodiment of the present invention;

FIGS. 14 and 15 show the steps of laminating two core members together using a joining member formed according to this invention;

FIG. 16 shows a section view of coreless buildup layer stack up; and

FIG. 17 shows a plurality of cores attached according to one embodiment of the current invention wherein a metallurgical paste makes an electrical connection between two Z-interconnect vias with conductive surfaces and coreless buildup layers attached thereto.

It is noted that the drawings of the invention are not to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.

For the sake of clarity and brevity, like elements and components of each embodiment will bear the same designations throughout the description.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the invention, a method and structure are provided for electrically joining a plurality of cores using thermoset resin and/or thermoplastic.

Referring now to the drawings and, for the present, to FIGS. 1-6, the successive steps in forming a core member 10 for use in laminating to another core member to form a printed wiring board according to one embodiment of the invention are shown. As can be seen in FIG. 1, the core member 10 includes a dielectric substrate 12 which has layers of metal coatings 14 and 16 on opposite faces thereof. Dielectric substrate 12 can be any conventional dielectric, such as FR4 (a glass reinforced epoxy), polyimide, polytetrafluoroethylene or other suitable well known dielectric. In the embodiment shown in FIGS. 1-6, the metal coatings 14 and 16 preferably are copper and, typically, the layer is either one-half ounce copper (17.5 μm), one ounce copper (35 μm thick) or two ounce copper (70 μm thick). However, other thicknesses of copper coatings can be used.

As shown in FIG. 2, preferably the copper layer 14 is patterned to form circuit traces 18 and the copper layer 16 is patterned to form circuit traces 20. Any conventional patterning process, such as by using a photoresist, exposing, developing and etching the exposed areas and then stripping the photoresist can be used.

As shown in FIG. 3, a film in the form of adhesive tape 22 is applied over the circuit traces 18 and the same type of film is applied over the circuit traces 20. A particularly useful adhesive tape is a polyimide having a silicone adhesive. This is available from Dielectric Polymers, Inc. of Holyoke, Mass. This tape must be compatible with the conductive material and processes associated with the formatting of the core, which will be described presently. Other types of film material may be used, such as plating tapes NT-580, 582, 583, 590 and 590-2 manufactured by Dielectric Polymers, Inc. The tape 22 and 24 should be of a thickness equal to the height that it is desired to have the conductive material extend above the circuit traces 18 and 20. If a single layer of tape is not sufficient, multiple layers may be used.

Referring now to FIG. 4, a plurality of holes or openings, two of which are shown at 26, are drilled through the entire composite, including the adhesive tape 22 and 24, circuit traces 18 and 20 and the substrate 12. These holes or openings 26 define the location of the conductive interconnect vias that will be formed.

Into the openings 26 is deposited an electrically conductive paste material 28, as shown in FIG. 5. The filling of these openings 26 can be performed by screening, stenciling, flood coating, doctor blading, immersing or injecting. Various types of conductive material may be used. By the term “conductive paste” as used herein is meant an electrically conductive paste composition adapted for use in holes or openings of substrates as well as between conductors which form parts of conductive planes of such a substrate. Such a paste includes at least one organic binder component and, in one embodiment, at least one metallic component including a plurality of “microparticles.” In another embodiment, the paste includes such an organic binder in addition to the aforementioned microparticles. A preferred conductive polymer material is a conductive epoxy sold by National Starch and Chemical Company under the trademark “Ablebond 8175” (This was formerly sold by Ablestik Corporation). “Ablebond 8175” is a silver filled thermosetting epoxy. Following the filling of the holes 26, as shown in FIG. 5, the epoxy is B-staged which entails heating the material to a temperature of about 130° C. until the degree of cure is advanced from about 20% to about 80% complete cure. As will become apparent later, the film material should not be fully cured at this stage since it will be used to adhere to another conductive epoxy in another core element. Alternatively, a solder paste of tin lead, tin lead silver, tin silver copper, tin silver copper antimony or tin bismuth, which are commercially available, can be used and heated to reflow.

After the conductive material 28 is partially cured, the adhesive tape 22 and 24 is removed to provide the structure shown in FIG. 6. As can be seen in FIG. 6, the partially cured conductive material 28 extends above the circuit traces 18 and 20 a distance equal to the thickness of the adhesive tape 22 and 24.

If the copper layers 14 and 16 have not been previously patterned, that can be done at this point. However, in general, it is preferred that the patterning to form the circuit traces 18 and 20 be done, as shown in FIG. 2, at that stage in the process so that the conductive material 28 is not subjected to the harsh chemical processes normally encountered in patterning material.

As can be seen in FIG. 7, two core elements 10 a and 10 b are provided which are to be laminated together. It will be noted that the two core elements 10 a and 10 b are very similar except that the circuit traces on each of them is slightly different. (In describing the embodiments of FIGS. 7 and 8, the letter suffixes a and b are used to denote similar structures in each core element.) As seen in FIG. 7, a pre-drilled adhesive bonding film 30, such as the film sold under the trademark Pyralux LF by Pyralux Corporation, is interposed between the two cores 10 a and 10 b. The film 30 has openings 32 drilled therein which are positioned to align with the conductive fill material 28 a, 28 b in the two core elements 10 a and 10 b.

Heat and pressure are applied to cause the two core members to bond together, with the Pyralux LF film acting as an adhesive bond material. Also, the fill material 28 a and 28 b in each of the openings in the two core members 10 a and 10 b will bond together, as shown in FIG. 8, to form a continuous Z-axis electrical connection between the circuit traces 18 a, 18 b, 20 a and 20 b on the core element 10 a and 10 b. Also, the material of the substrate 30 will fill around the circuit traces 18 b and 20 a. The lamination process also advances the cure of the conductive fill material 28 a and 28 b past 80% to the fully cured stage. A specially formulated dicing tape can be used as adhesive tape 22. An example of suitable dicing tape is Adwill D-series tape provided by Lintec Corporation. These tapes are comprised of a base material, such as PVC (poly vinyl chloride), or PET (polyethylene terephthalate), or PO (polyolefin) with an adhesive film that provides strong temporary adhesion. Alternatively, the adhesive could be provided on other base material, such as polyimide.

The adhesive layer provided on the base layer is formulated so that it provides strong initial adhesion but, upon exposure to UV (ultraviolet) radiation, its adhesion is diminished and it can be peeled and released without causing damage or leaving residue on the copper traces 18 or the dielectric layer 12. In such case, the backing must be transparent to UV radiation. Also, it is to be understood that the tape 22, 24 does not need to be a dielectric. For example, a metal foil with an adhesive on one side could be used. This also constitutes a “tape”. (Alternatively, the film material 30 could be a dry film epoxy adhesive which is B-staged, or thermoplastic LCP film or organic pre-preg typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-staged epoxy resin or other film type adhesive dielectric layers and used to laminate the core elements 10 a and 10 b together.)

Referring now to FIGS. 9-13, another embodiment of the present invention is shown which is useful in forming a joining member. A substrate 10 is provided which is preferably an adhesive dielectric material. For example, this could be an adhesive coated film (such as duPont Pyralux LF, which is a modified acrylic adhesive on a polyimide film) or a B-staged thermoset adhesive (such as IBM Dri-clad glass reinforced high glass transition dielectric material), or other film type adhesive dielectric layers, including materials such as Rogers 2800 Silica filled polytetrafluoroethylene. Thermoset resin coated Silica filled polytetrafluoroethylene or thermoset resin coated liquid crystal polymer (LCP) or LCP-Silica filled polytetrafluoroethylene-LCP or LCP-Polyimide-LCP type materials can also be used. In general, LCP bondply (available from Rogers) can be laminated with polyimide or Silica filled polytetrafluoroethylene to make LCP-Polyimide-LCP or LCP-Silica filled polytetrafluoroethylene-LCP mixed dielectric.

A plurality of holes, one of which is shown at 26, is either mechanically or laser drilled through the substrate 12 and through both of the tapes 22 and 24, as shown in FIG. 11. A conductive material 28 of the same type as described with respect to FIGS. 1-6 is deposited in the hole 26 by the same techniques as previously described with respect to FIGS. 1-6. After the conductive material 28 is remelted or cured, as previously described, the adhesive tapes 22 and 24 are removed to provide a joining member, as shown in FIG. 13. Alternatively, tapes 22 and 24 can be CU layer. Cu can be removed by an etching process. Proper conducting paste such as silver-epoxy based paste is etch resistant and generates paste nubs (FIG. 13).

In FIG. 11 a, the opening 26 is plated, preferably with copper, to form inner conductive layers. A preferred method of accomplishing this is to use a “flash” plating of electroless copper. It is to be understood that forming plated layers 35 is an optional step in forming a substrate as defined herein, but is preferred to further assure sound conductive paths in these portions of the structure. The next step, as also shown in FIG. 12, involves the deposition of conductive paste 28 within each of the plated openings 26. Such deposition may be accomplished using conventional paste printing processes or dispensing through conventional needles. Significantly, the conductive paste as used in this embodiment includes a binder (preferably an organic binder) component and at least one metallic component. As defined herein, this metallic component is in the form of microparticles or nanoparticles or their mixtures, either as flakes or semi-colloidal powders. Metals may include copper, silver, gold, zinc, cadmium, palladium, iridium, ruthenium, osmium, rhodium, platinum, iron, cobalt, nickel, indium, tin, antimony, lead, bismuth and alloys thereof for the microparticles.

In one embodiment of the invention, a conductive paste having silver microparticles may be used, the paste including an anhydride epoxide as the organic binder. This paste preferably includes about 88% by weight of the silver microparticles and about 12% by weight of the anhydride epoxide. With the solder added to the microparticles as described below, the resulting paste has a decomposition temperature of approximately 340 degrees C., which, when considering the above high temperature dielectric material, is about ten degrees C. less than the 350 degrees C. temperature the dielectric can withstand during lamination. The average silver particles are each from about 0.01 microns to about 10 microns in diameter. In the case of both flat particles (flakes) and rod-like particles, thicknesses are each from about 0.01 micron to 10 micron.

Although only one opening 26 is depicted in FIG. 11 a, this is meant to be representative only. In one example, a total of 2500 openings may be provided within a rectangular layer having dimensions of about 52.5 millimeters (mm) wide by about 52.5 mm long, and a thickness of about 0.175 mm. These 2500 paste filled nubs in FIG. 13 generate 3-D micro arrays. These kinds of conductive adhesive based 3-D micro array Z-interconnects are used to connect multiple electronic layers.

FIGS. 6 and 13 show 3-D micro arrays for connecting several electronic layers starting from chip to board. Adhesives formulated using controlled-sized particles, ranging from nanometer scale to micrometer scale, were used to form micro arrays of contact pads having diameters ranging from 5 μm to 250 μm for internal and external interconnect applications. For example, micro arrays (not shown) with pads having 5-15 micron diameters are suitable for device level interconnects (chip to chip interconnects), whereas 50-75 μm and 250 μm diameters of the pads are suitable for chip carrier and board level interconnects, respectively.

As shown in FIGS. 14 and 15, a joining member formed according to FIGS. 9-13 is used to join two printed wiring boards 34. The dielectric substrate 10 is adhesive or B-staged thermoset resin or thermoplastic polymer acting as a bonding member. Typically, the printed wiring boards will have a dielectric substrate 36 with a plurality of internal conductive planes, one of which is shown at 38, and plated through holes 40. However, this is just illustrative as the joining member can be used to join many different types of printed wiring boards, the boards shown in FIGS. 14 and 15 being merely illustrative.

Alternatively, in FIG. 14, two printed wiring boards 34 can be flexible substrates and extended beyond the joining layer 10. In that case, area 34 bonded with dielectric 10 is rigid and the rest of the area is free standing and flexible. In general, II-VI metal layers substrate made with flexible materials produces flexible substrate 34. One example of such material is sold under the product name “RO2800” dielectric material provided by Rogers Corporation, Rogers, Conn.

Again, area 34 can be a substrate having embedded capacitors and resistors. Embedded capacitors can be a high dielectric constant ceramic filled dielectric (e.g., barium titanate filled epoxy) layer. One example of such material is resin coated capacitive materials used as a buildup layer. The resistor can be a multilayer resistor foil laminated with the capacitor dielectric. For example, core can use 25 ohm per square material and 250 ohm per square inch material. This combination enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Here, two printed wiring boards 34 having embedded capacitors and resistors are bonded with the dielectric substrate 10. Adhesive or B-staged thermoset resin or thermoplastic polymer acts as a bonding member.

Referring now to FIG. 16, a core 100 is shown having a plurality of vias 130. Core 100 may comprise an epoxy core or any similar structure as commonly known in the art. Core 100 may include one or more planes 120-122, which may include, for example, a power plane, signal plane, or a ground plane. Using via 130 as an example, each via has a conductive surface 135 formed on a surface of core 100. Conductive surface 135 can comprise a thin layer of any solderable conductive material including, for example, a precious metal or copper. The joining concept for core 100 is to use compression and heating to melt or diffuse the solder to create the laminate, thereby having metallic contacts between planes 120-122 while not using a conductive paste.

Alternatively, core 100 may include multiple planes and multiple dielectric layers. At least one or multiple dielectrics can be made with thermoplastic polymers. At least one of the thermoplastic layers may be larger than the joining layer and remain as an extended flexible layer. Flexible layer can be a capacitance layer or resistor foil laminated capacitance layer. One example of such flexible capacitance material is sold under the product name “RO2800” dielectric material by Rogers Corporation, Rogers, Conn.

FIG. 17 shows a plurality of cores 200 attached according to one embodiment of the current invention wherein a metallurgical paste 210 creates an electrical connection between two vias with conductive surfaces 215 to create Z-axis interconnects 205 as known in the art and also the novel coreless buildup layer 100 and coreless buildup layer with LGA 105 containing individual LGA pads 220 are diffusion bonded to the upper surface 225 and lower surface 230, respectively. Few or all of the metallurgical paste 210 can be replaced by conductive adhesive to create an electrical connection between two vias with conductive surfaces 215 to create Z-axis interconnects.

Since other modifications and changes to the coreless layer buildup will be apparent to those skilled in the art, the invention is not considered limited to the description above for purposes of disclosure, and covers all changes and modifications which do not constitute departures from the true spirit and scope of this invention.

Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.

Claims (18)

What is claimed is:
1. A substrate for use in a PC board comprising:
a) a flexible thermoplastic dielectric having two major surfaces;
b) a first and a second metal layer attached to each of said major surfaces, respectively;
c) at least two coreless, partially-filled thermoset resin-coated Cu-based buildup layers disposed respectively on said first and said second metal layers;
d) a third and a fourth metal layer disposed on said at least two coreless buildup layers, respectively; and
e) an electrical connection between said first and said second metal layers, and said first and said third metal layers, and said first and said fourth metal layers, and said second and said third metal layers, and said second and said fourth metal layers, and said third and said fourth metal layers;
wherein said thermoplastic dielectric has dimensions greater than the dimensions of said coreless, partially-filled thermoset resin-coated Cu-based buildup layers, resulting in an extended flexible thermoplastic layer; and
whereby a high density, thin substrate is produced.
2. The substrate as per claim 1, wherein said coreless buildup layer comprises a partially-cured fiberglass cloth-impregnated thermoset resin.
3. The substrate as per claim 1, wherein said coreless buildup layer comprises a thermoplastic resin.
4. The substrate as per claim 2, wherein said coreless buildup layer comprises alternate layers of partially-cured and fully-cured resin.
5. The substrate as per claim 1, further comprising:
f) a land grid array (LGA) electrically connected to said third metal layer;
g) a fifth metal layer; and
h) a first joining layer of dielectric disposed between said fourth and said fifth metal layers.
6. The substrate as per claim 5, wherein said first and said second metal layers each comprise two to six metal layers.
7. The substrate as per claim 5, wherein said first joining layer of dielectric comprises at least one from the group: partially-cured thermoset resin and thermoplastic.
8. The substrate as per claim 5, wherein said first joining layer of dielectric comprises at least one from the group: high dielectric constant and low loss capacitance material.
9. The substrate as per claim 5, wherein said first and said second metal layers comprise a resistor foil laminated and circuitized on at least one from the group: at least partially-cured thermoset and thermoplastic resin dielectric layer.
10. The substrate as per claim 6, wherein said first and said second metal layers comprise a multilayer resistor foil.
11. The substrate as per claim 10, wherein said resistor foil has a resistance range of 15 ohms to 30,000 ohms.
12. The substrate as per claim 9, wherein said resistor foil comprises at least one from the group: high dielectric constant and low loss capacitance layer.
13. The substrate as per claim 5 further comprising:
i) a sixth metal layer.
14. The substrate as per claim 13, further comprising:
j) a second joining layer of dielectric disposed between said second and said third metal layers.
15. The substrate as per claim 14, wherein said second joining layer of dielectric comprises capacitance material.
16. The substrate as per claim 13, wherein said first and said second and said third metal layers comprise at least one plane from the group: signal, power, and ground.
17. The substrate as per claim 13, further comprising a conductive paste comprising at least one set of metal micro particles chosen from the group: copper, silver, gold, zinc, cadmium, palladium, iridium, ruthenium, osmium, rhodium, platinum, iron, cobalt, nickel, indium, tin, antimony, lead, bismuth and alloys thereof.
18. The substrate as per claim 17, wherein said conductive paste decomposition temperature is approximately 340° C.
US12/764,994 2010-04-22 2010-04-22 Coreless layer buildup structure with LGA Active 2030-04-23 US8536459B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/764,994 US8536459B2 (en) 2010-04-22 2010-04-22 Coreless layer buildup structure with LGA

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/764,994 US8536459B2 (en) 2010-04-22 2010-04-22 Coreless layer buildup structure with LGA

Publications (2)

Publication Number Publication Date
US20120160544A1 US20120160544A1 (en) 2012-06-28
US8536459B2 true US8536459B2 (en) 2013-09-17

Family

ID=46315301

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/764,994 Active 2030-04-23 US8536459B2 (en) 2010-04-22 2010-04-22 Coreless layer buildup structure with LGA

Country Status (1)

Country Link
US (1) US8536459B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8867219B2 (en) * 2011-01-14 2014-10-21 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
WO2014046014A1 (en) * 2012-09-20 2014-03-27 株式会社クラレ Circuit board and method for manufacturing same

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542174A (en) * 1994-09-15 1996-08-06 Intel Corporation Method and apparatus for forming solder balls and solder columns
US5869880A (en) * 1995-12-29 1999-02-09 International Business Machines Corporation Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US6284982B1 (en) * 2000-08-18 2001-09-04 Ga-Tek Inc. Method and component for forming an embedded resistor in a multi-layer printed circuit
US6465084B1 (en) 2001-04-12 2002-10-15 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
US20020189853A1 (en) * 2001-06-15 2002-12-19 Phoenix Precision Technology Corp. BGA substrate with direct heat dissipating structure
US6562657B1 (en) * 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6638607B1 (en) 2002-10-30 2003-10-28 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
JP2005064498A (en) * 2003-08-13 2005-03-10 Phoenix Precision Technology Corp Semiconductor package board structure having metal protective layer for electrical connection pad, and manufacturing method for semiconductor packaging board structure
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US20060043549A1 (en) * 2004-09-01 2006-03-02 Phoenix Precision Technology Corporation Micro-electronic package structure and method for fabricating the same
US20060060557A1 (en) * 2004-09-21 2006-03-23 Sreenivasan Sidlgata V Reverse tone patterning on surfaces having surface planarity perturbations
US7050304B2 (en) * 2003-08-28 2006-05-23 Phoenix Precision Technology Corporation Heat sink structure with embedded electronic components for semiconductor package
US20070007033A1 (en) * 2005-07-11 2007-01-11 Endicott Interconnect Technologies, Inc. Circuitized substrate with soler-coated microparticle paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same and method of making said substrate
US20070045784A1 (en) * 2005-08-25 2007-03-01 Corisis David J Lead frame-based semiconductor device packages incorporating at least one land grid array package and methods of fabrication
US7239525B2 (en) * 2004-11-17 2007-07-03 Phoenix Precision Technology Corporation Circuit board structure with embedded selectable passive components and method for fabricating the same
US7242092B2 (en) * 2005-02-02 2007-07-10 Phoenix Precision Technology Corporation Substrate assembly with direct electrical connection as a semiconductor package
JP2007214534A (en) * 2006-02-09 2007-08-23 Phoenix Precision Technology Corp Manufacturing method of circuit board having conductive structure
US20070243387A1 (en) * 2006-04-13 2007-10-18 Lin Wendy W Dual cure resin composite system and method of manufacturing the same
US20070246744A1 (en) * 2006-04-19 2007-10-25 Phoenix Precision Technology Corporation Method of manufacturing a coreless package substrate and conductive structure of the substrate
US20080185704A1 (en) * 2007-02-02 2008-08-07 Phoenix Precision Technology Corporation Carrier plate structure havign a chip embedded therein and the manufacturing method of the same
US7539022B2 (en) * 2005-10-04 2009-05-26 Phoenix Precision Technology Corporation Chip embedded packaging structure
US7592706B2 (en) * 2004-12-21 2009-09-22 Phoenix Precision Technology Corporation Multi-layer circuit board with fine pitches and fabricating method thereof
US7656040B2 (en) * 2006-06-01 2010-02-02 Phoenix Precision Technology Corporation Stack structure of circuit board with semiconductor component embedded therein

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US5542174A (en) * 1994-09-15 1996-08-06 Intel Corporation Method and apparatus for forming solder balls and solder columns
US5869880A (en) * 1995-12-29 1999-02-09 International Business Machines Corporation Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers
US6284982B1 (en) * 2000-08-18 2001-09-04 Ga-Tek Inc. Method and component for forming an embedded resistor in a multi-layer printed circuit
US6562657B1 (en) * 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US6465084B1 (en) 2001-04-12 2002-10-15 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
US20020189853A1 (en) * 2001-06-15 2002-12-19 Phoenix Precision Technology Corp. BGA substrate with direct heat dissipating structure
US6638607B1 (en) 2002-10-30 2003-10-28 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
US6969436B2 (en) 2002-10-30 2005-11-29 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
US7303639B2 (en) 2002-10-30 2007-12-04 International Business Machines Corporation Method for producing Z-axis interconnection assembly of printed wiring board elements
JP2005064498A (en) * 2003-08-13 2005-03-10 Phoenix Precision Technology Corp Semiconductor package board structure having metal protective layer for electrical connection pad, and manufacturing method for semiconductor packaging board structure
US7050304B2 (en) * 2003-08-28 2006-05-23 Phoenix Precision Technology Corporation Heat sink structure with embedded electronic components for semiconductor package
US20060043549A1 (en) * 2004-09-01 2006-03-02 Phoenix Precision Technology Corporation Micro-electronic package structure and method for fabricating the same
US20060060557A1 (en) * 2004-09-21 2006-03-23 Sreenivasan Sidlgata V Reverse tone patterning on surfaces having surface planarity perturbations
US7239525B2 (en) * 2004-11-17 2007-07-03 Phoenix Precision Technology Corporation Circuit board structure with embedded selectable passive components and method for fabricating the same
US7592706B2 (en) * 2004-12-21 2009-09-22 Phoenix Precision Technology Corporation Multi-layer circuit board with fine pitches and fabricating method thereof
US7242092B2 (en) * 2005-02-02 2007-07-10 Phoenix Precision Technology Corporation Substrate assembly with direct electrical connection as a semiconductor package
US20070007033A1 (en) * 2005-07-11 2007-01-11 Endicott Interconnect Technologies, Inc. Circuitized substrate with soler-coated microparticle paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same and method of making said substrate
US20070045784A1 (en) * 2005-08-25 2007-03-01 Corisis David J Lead frame-based semiconductor device packages incorporating at least one land grid array package and methods of fabrication
US7539022B2 (en) * 2005-10-04 2009-05-26 Phoenix Precision Technology Corporation Chip embedded packaging structure
JP2007214534A (en) * 2006-02-09 2007-08-23 Phoenix Precision Technology Corp Manufacturing method of circuit board having conductive structure
US20070243387A1 (en) * 2006-04-13 2007-10-18 Lin Wendy W Dual cure resin composite system and method of manufacturing the same
US20070246744A1 (en) * 2006-04-19 2007-10-25 Phoenix Precision Technology Corporation Method of manufacturing a coreless package substrate and conductive structure of the substrate
US7656040B2 (en) * 2006-06-01 2010-02-02 Phoenix Precision Technology Corporation Stack structure of circuit board with semiconductor component embedded therein
US20080185704A1 (en) * 2007-02-02 2008-08-07 Phoenix Precision Technology Corporation Carrier plate structure havign a chip embedded therein and the manufacturing method of the same

Also Published As

Publication number Publication date
US20120160544A1 (en) 2012-06-28

Similar Documents

Publication Publication Date Title
US9756724B2 (en) Method of making a circuitized substrate
US5401913A (en) Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
KR100203540B1 (en) Circuit devices and fabrication method of the same
EP0469308B1 (en) Multilayered circuit board assembly and method of making same
US5440075A (en) Two-sided printed circuit board a multi-layered printed circuit board
US6541712B1 (en) High speed multi-layer printed circuit board via
JP5082321B2 (en) Multilayer printed wiring board and manufacturing method thereof
EP1280393B1 (en) Multilayer circuit board and method for manufacturing multilayer circuit board
EP0851724B1 (en) Printed circuit board and electric components
US5839188A (en) Method of manufacturing a printed circuit assembly
US6939738B2 (en) Component built-in module and method for producing the same
US5719749A (en) Printed circuit assembly with fine pitch flexible printed circuit overlay mounted to printed circuit board
US7485569B2 (en) Printed circuit board including embedded chips and method of fabricating the same
CN1812689B (en) Multilayer circuit board and manufacturing method thereof
US6872894B2 (en) Information handling system utilizing circuitized substrate
DE60215518T2 (en) Wiring module with reduced supply distribution impedance
US5737833A (en) Method of producing a high-density printed wiring board for mounting
EP0647090B1 (en) Printed wiring board and a method of manufacturing such printed wiring boards
US7849591B2 (en) Method of manufacturing a printed wiring board
US7326858B2 (en) Printed circuit board with embedded capacitors and manufacturing method thereof
TWI294757B (en) Circuit board with a through hole wire, and forming method thereof
JP3969192B2 (en) Manufacturing method of multilayer wiring board
US5688584A (en) Multilayer electronic circuit having a conductive adhesive
JP3853219B2 (en) Semiconductor element built-in substrate and multilayer circuit board
US5906042A (en) Method and structure to interconnect traces of two conductive layers in a printed circuit board

Legal Events

Date Code Title Description
AS Assignment

Owner name: ENDICOTT INTERCONNECT TECHNOLOGIES, INC., NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARKOVICH, VOYA;ANTESBERGER, TIMOTHY;EGITTO, FRANK D.;AND OTHERS;SIGNING DATES FROM 20100228 TO 20100304;REEL/FRAME:024341/0009

AS Assignment

Owner name: PNC BANK, NATIONAL ASSOCIATION, PENNSYLVANIA

Free format text: SECURITY AGREEMENT;ASSIGNORS:ENDICOTT INTERCONNECT TECHNOLOGIES, INC.;EI TRANSPORTATION COMPANY LLC;ENDICOTT MEDTECH, INC.;REEL/FRAME:028230/0798

Effective date: 20120210

AS Assignment

Owner name: INTEGRIAN HOLDINGS, LLC, NEW YORK

Free format text: ASSIGNMENT OF SECURITY AGREEMENT;ASSIGNOR:PNC BANK, NATIONAL ASSOCIATION;REEL/FRAME:029938/0823

Effective date: 20130306

AS Assignment

Owner name: M&T BANK, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:ENDICOTT INTERCONNECT TECHNOLOGIES, INC.;EI TRANSPORTATION COMPANY LLC;ENDICOTT MEDTECH, INC.;AND OTHERS;REEL/FRAME:030359/0057

Effective date: 20130313

AS Assignment

Owner name: MAINES, DAVID, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:ENDICOTT INTERCONNECT TECHNOLOGIES, INC.;REEL/FRAME:030599/0918

Effective date: 20130612

Owner name: MAINES, WILLIAM, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:ENDICOTT INTERCONNECT TECHNOLOGIES, INC.;REEL/FRAME:030599/0918

Effective date: 20130612

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: ENDICOTT INTERCONNECT TECHNOLOGIES, INC., NEW YORK

Free format text: RELEASE BY SECURED PARTY;ASSIGNORS:MAINES, WILLIAM;MAINES, DAVID;REEL/FRAME:035098/0968

Effective date: 20150130

AS Assignment

Owner name: I3 ELECTRONICS, INC., NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ENDICOTT INTERCONNECT TECHNOLOGIES, INC.;REEL/FRAME:035442/0569

Effective date: 20150415

AS Assignment

Owner name: M&T BANK, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNOR:I3 ELECTRONICS, INC.;REEL/FRAME:040608/0626

Effective date: 20161103

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: TTM TECHNOLOGIES NORTH AMERICA, LLC, MISSOURI

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:I3 ELECTRONICS, INC.;REEL/FRAME:049758/0265

Effective date: 20190612

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY