CN103299724B - 具有液晶聚合物焊料掩模及外封层的电子装置及相关联方法 - Google Patents
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Abstract
一种电子装置(10)包含衬底(11)与在所述衬底(11)上具有焊料衬垫(13)的电路层(12)。在所述衬底上存在液晶聚合物LCP焊料掩模(16),所述液晶聚合物LCP焊料掩模(16)具有与所述焊料衬垫对准的孔隙。在所述衬底与所述LCP焊料掩模之间存在熔融接缝。焊料在所述孔隙中,且电路组件(35)经由所述焊料而电耦合至所述焊料衬垫。具有第一多个介电层的第一介电层堆叠(20)在所述LCP焊料掩模上,且具有与所述焊料衬垫对准的孔隙(24)。存在在所述第一介电层堆叠上的第一LCP外封层(23),及具有第二多个介电层的第二介电层堆叠(30),所述第二介电层堆叠(30)处于所述衬底上所述衬底与所述LCP焊料掩模相反的一侧上。另外,在所述第二介电层堆叠上存在第二LCP外封层(33)。
Description
技术领域
本发明涉及电子装置制造的领域,且更特定来说,涉及具有液晶聚合物焊料掩模及多个介电层的电子装置,以及相关方法。
背景技术
随着半导体及集成电路技术进步,已存在朝着具有众多输入及输出衬垫的高功能性集成电路组件发展的趋势,以及对减小的芯片大小、重量及功率消耗的需求。因此,随着集成电路的大小减小,集成电路日益具有比先前更紧密地配置在一起的更小输出衬垫。
为了匹配这些高功能性集成电路,存在对由用于集成电路的焊料附接的紧密配置的衬垫组成的印刷线路板的需求。然而,在一些应用中,目前集成电路衬垫之间的间隔的小型化正以比印刷电路板上的焊料衬垫的小型化大的速率发生。另外,通过焊料掩模来保护这些紧密隔开的衬垫的能力尚未跟上集成电路上的衬垫之间的空间的减小。在无紧密隔开的邻近衬垫之间的焊料掩模保护的情况下,在于将集成电路附接至印刷线路板中所利用的焊料回焊工艺期间存在桥接及电短路的增加的风险。因此,对于一些现代装置来说,存在互连技术差距。
为了使此些装置起作用,印刷线路板可具有用以处置集成电路的衬垫的额外布线层或利用扇出封装。此情形导致集成电路的封装大小比集成电路自身大,此情形可限制系统小型化。除对小型化装置的这些需求之外,在一些状况下也需要由柔性而非硬质的衬底来建构这些装置。
先前技术的小型化装置描述于颁给Lee等人的第2007/0025092号美国专利公开案中。此参考案揭示一种电子装置,所述电子装置包括界定电路互连件的多个堆积层,且所述电子装置包括一个或一个以上薄膜型嵌入式被动装置、形成于所述堆积层中的至少一空腔。主动装置安置于所述空腔中且电连接至所述堆积层的电路互连件。封装具有芯片可重新使用性、较容易的热管理及相对来说极薄的轮廓。然而,这些封装并非由柔性材料建构,且因此可能在一些情形下不合适。另外,可能需要甚至更薄的封装。
现用作衬底(由所述衬底来建构薄的且柔性的印刷线路板)的材料为双轴定向的液晶聚合物(LCP)。LCP中的分子具有硬质、杆状形状,且在处于液相中时或在加热及熔化时维持结晶次序。液晶聚合物印刷电路的处理及组装(The Processing and Assembly ofLiquid Crystalline Polymer Printed Circuits)(T.Zhang、W.Johnson、B.Farrell及M.St.Lawrence,“液晶聚合物印刷电路的处理及组装(The processing and assembly of liquidcrystalline polymer printed circuits)”,2002年,国际微电子研讨会2002)论述了使用LCP作为衬底的印刷电路板的建构。首先将光阻剂涂覆至覆铜叠层,将所述光阻剂曝露且显影以界定所要的电路图案。接着通过蚀刻掉曝露的铜来界定实际电路。在热压机或高压釜中将多个电路层层压在一起以形成多层。经由机械或激光钻孔在衬底中形成孔或通孔。接着执行去污步骤以自通孔或孔移除碎片,藉此制备用于金属沉积的LCP材料。接下来执行金属化步骤,且将常规焊料掩模施加至LCP衬底。接着经由常规焊料掩模涂覆焊料以完成LCP印刷电路板的建构。
虽然此设计确实允许形成薄的柔性印刷电路板,但其仍遭受与上文关于具有紧密隔开的衬垫的集成电路至印刷电路板的附接所描述的缺点相同的缺点。因而,需要将集成电路连接至印刷电路板的额外方法。
发明内容
鉴于前述背景,因此,本发明的目标为提供一种有效地将电子组件附接至衬底的方法。
藉由通过一种电子装置来提供根据本发明的此目标、特征及优点及其它目标、特征及优点,所述电子装置包括衬底及电路层,所述电路层在所述衬底上且包括至少一焊料衬垫。存在液晶聚合物(LCP)焊料掩模,所述液晶聚合物(LCP)焊料掩模在所述衬底上且具有与所述至少一焊料衬垫对准的至少一孔隙。另外,存在在所述衬底与所述LCP焊料掩模之间的熔融接缝,以及在所述至少一孔隙中的焊料。此外,至少一电路组件经由所述焊料而电耦合至所述至少一焊料衬垫。
包括第一多个介电层的第一介电层堆叠在所述LCP焊料掩模上且具有与所述至少一焊料衬垫对准的至少一孔隙。存在在所述第一介电层堆叠上的第一LCP外封层,以及包括第二多个介电层的第二介电层堆叠,所述第二介电层堆叠在所述衬底的与所述LCP焊料掩模相反的一侧上处于所述衬底上。另外,第二LCP外封层在所述第二介电层堆叠上。
此装置呈现出众多优点,包含(但不限于)以下各事实:此装置可归因于所述LCP焊料掩模而薄于先前技术的装置的事实;所述电子组件附接至具有比先前技术的间距细微的间距的焊料衬垫阵列的事实;以及所述LCP外封层密封所述装置从而保护所述装置免受污染物影响的事实。
所述第一多个介电层可包含在所述LCP焊料掩模上的第一介电层、在所述第一介电层上的第一结合层,以及在所述第一结合层上的第二介电层。另外,可能存在在所述第一介电层与所述LCP焊料掩模之间的熔融接缝、在所述结合层与所述第一介电层之间的熔融接缝、在所述第一结合层与所述第二介电层之间的熔融接缝,以及在所述第二介电层与所述第一LCP外层之间的熔融接缝。
在一些应用中,所述第二多个介电层包括在所述衬底的与所述LCP焊料掩模相反的一侧上处于所述衬底上的第二结合层,以及在所述第二结合层上的第三介电层。可能存在在所述第二结合层与所述衬底之间的熔融接缝,以及在所述第二结合层与所述第三介电层之间的熔融接缝,以及在所述第三介电层与所述第二LCP外层之间的熔融接缝。
在一些应用中,所述衬底可为液晶聚合物(LCP)衬底。另外,所述第一多个介电层及所述第二多个介电层可各自包括多个LCP介电层。至少一导电通孔可在所述第一多个介电层及所述第二多个介电层中的每一者中。
所述至少一焊料衬垫可为多个焊料衬垫,所述多个焊料衬垫可以阵列图案配置,且所述LCP焊料掩模中的所述至少一孔隙可小于0.10″英寸,且在一些状况下小至0.0025英寸或小于0.0025英寸。
一方法方面是针对一种制造一电子装置的方法。所述方法包括在衬底上形成包括至少一焊料衬垫的电路层,以及形成液晶聚合物(LCP)焊料掩模,所述液晶聚合物(LCP)焊料掩模具有可与所述至少一焊料衬垫对准的至少一孔隙。所述方法还包含形成第一介电层堆叠及第二介电层堆叠,所述第一介电层堆叠具有可与所述至少一焊料衬垫对准的至少一孔隙;以及使所述LCP焊料掩模与所述衬底对准,使所述第一介电层堆叠与所述LCP焊料掩模对准,且使所述第二介电层堆叠与所述衬底对准。所述方法进一步包含将所述LCP焊料掩模层压至所述衬底,将所述第一介电层堆叠层压至所述LCP焊料掩模,且将所述第二介电层堆叠层压至所述衬底的与所述LCP焊料掩模相反的一侧。同样,所述方法包含将焊料膏定位于所述LCP焊料掩模的所述至少一孔隙中,使用所述焊料膏将至少一电路组件附接至所述至少一焊料衬垫,以及使第一LCP外封层与第二LCP外封层对准且分别将所述第一LCP外封层及所述第二LCP外封层层压至所述第一介电层堆叠及所述第二介电层堆叠。
附图说明
图1至6为在本发明的电子装置的制造期间的连续示意性横截面图。
图7为根据本发明的制造电子装置的方法的流程图。
具体实施方式
现将在下文中参看随附图式来更完全地描述本发明,本发明的优选实施例展示于所述随附图式中。然而,本发明可以许多不同形式来体现且不应被解释为限于本文中所阐述的实施例。确切地说,提供这些实施例以使得本发明将为详尽的及完整的,且将本发明的范围完全地传达给所属领域的技术人员。贯穿各图,相同数字指代相同元件。
最初参看图7的流程图40以及图1至6,现描述制造电子装置10的方法。如图1中所展示,在开始(框41)之后,在衬底11上形成包括至少一焊料衬垫13的电路层12(框42)。此处,电路层12说明性地包括以阵列图案配置的多个焊料衬垫13。另外,在衬底11中形成导电通孔14,但应理解,这些通孔是可选的。同样,应理解,可存在任何数目个焊料衬垫13。
衬底11可由液晶聚合物(LCP)形成。出于多种原因,LCP为用以形成柔性印刷电路板的特别有利的材料,所述多种原因包含以下事实:LCP具有高拉伸强度,从而提供高耐磨损性及高耐损害性。通常,LCP还具有高温下的高机械强度、高耐化学性、固有的阻燃性及良好的耐气候性。另外,LCP相对来说较具惰性。LCP耐受在高温下在存在大多数化学物质的情况下的应力破裂性,所述化学物质包含芳族烃或卤化烃、强酸、碱、酮及其它侵蚀性工业物质。此外,LCP可经形成而具有均匀表面,由此允许层间的狭窄间隙。
所属领域的技术人员应理解,存在可用于生产根据本发明的电子装置的多种LCP。
接下来,如图2中所展示,形成LCP焊料掩模16,LCP焊料掩模16具有可与焊料衬垫13对准的至少一孔隙18(框43)。由LCP形成焊料掩模16是有利的,因为LCP耐受与焊料的接触,且因为LCP比常规焊料掩模更耐受切削。
此处,说明性地存在多个孔隙18。可通过例如激光或机械钻孔/冲压等合适工艺来形成孔隙18。当将LCP用作焊料掩模16时,LCP的高耐磨损性及拉伸强度是特别有利的。举例来说,孔隙18可小至0.004英寸至0.008英寸,或更小。另外,LCP焊料掩模16的使用并不抑制电子装置10的柔性,因为LCP焊料掩模16极薄。另外,LCP焊料掩模16帮助向电子装置10提供更紧密的弯曲半径,且在热定形的情形下将呈现永久性形状。此外,LCP耐受多种化学物质及溶剂。
继续制造电子装置10的方法的论述,如图3至4中所展示,形成第一介电层堆叠20及第二介电层堆叠30(框44)。第一介电层堆叠20中形成有与焊料衬垫13对准的孔隙24,以便耦合至焊料衬垫的电子组件装配于孔隙24中。
在一些应用中,衬底11、第一介电层堆叠20及第二介电层堆叠30均可由LCP形成。通过由LCP建构衬底11、焊料掩模16、第一介电层堆叠20及第二介电层堆叠30,可在不使用黏着剂的情况下执行层压,从而减小所得装置的总厚度。另外,通过由LCP建构各种层,可使所述各种层匹配(例如,具有相同介电常数、损耗角正切、热膨胀系数等),从而使得此配置特别适用于尺寸稳定的射频(RF)装置的建构。另外,使用LCP来建构焊料掩模16产生比一些先前技术焊料掩模薄的焊料掩模,例如,0.001英寸厚而非0.002+英寸厚。另外,与一些先前技术焊料掩模相比较来说,LCP焊料掩模16展现出优异的厚度均匀性。此外,LCP焊料掩模16提供比常规焊料掩模更好的电隔离,与常规焊料掩模的每密耳500伏特相对比,LCP焊料掩模16具有约每密耳3500伏特的介电强度。同样重要的是:LCP焊料掩模具有在层压至下伏衬底之前形成的孔隙,此情形允许非焊料掩模界定的衬垫阵列。
当然,在一些应用中,并非所有层由LCP建构。举例来说,在一实施例中,第一介电层堆叠20包括第一介电层22、第一结合层21及第二介电层34的堆叠配置。第二介电层堆叠30包括第二结合层31及第三介电层32的堆叠配置。第一介电层22、第二介电层30及第三介电层32可由例如聚酰亚胺等合适介电材料建构,且第一结合层21及第二结合层31可由任何合适材料建构,例如,预先浸渍的b阶段基于树脂的材料或热塑性结合膜。
接下来,如图4中所展示,使LCP焊料掩模16与衬底11对准,使第一介电层堆叠20与LCP焊料掩模对准,且使第二介电层堆叠30与衬底对准(框45)。
关于LCP焊料掩模16与衬底11以及第一介电层堆叠20与LCP焊料掩模16,将对准定义为:使得焊料衬垫13定中心于孔隙18的中间处。可通过以下操作来执行此对准:例如,首先使用夹具或导引件来使LCP焊料掩模16与LCP衬底11粗略对准,或使第一介电层堆叠20与LCP焊料掩模粗略对准,且接着在显微镜下精细地调整所述对准以达到最终对准。此方法有利地允许在0.0005英寸至0.001英寸的范围中的位置对准准确度。
对准之后,执行层压。也就是说,如图4中所展示,将LCP焊料掩模16层压至衬底11,将第一介电层堆叠20层压至LCP焊料掩模,且将第二介电层堆叠30层压至衬底的与LCP焊料掩模相反的侧(框46)。通常经由施加热及压力(例如,在高压釜中)来执行所述层压。高压釜有利地提供均衡压力(也就是说,来自所有方向的相等压力),且在层压工艺期间帮助阻止LCP发生变形。虽然将高压釜用于层压是优选的,但也可使用压机(有可能在惰性气氛下)来执行层压。所述层压在邻近层之间产生熔融接缝,所述熔融接缝在经横截装置的像片中可容易地见到。
在层压之后,将焊料膏定位于焊料掩模的孔隙18中(框47)。如图5中所展示,接着通过加热焊料膏(所述焊料膏接着熔化且重新凝固)将例如集成电路35等电子组件附接至焊料衬垫13(框48)。
如图6中所展示,接着分别使第一LCP外封层23及第二LCP外封层33与第一介电层堆叠20及第二介电层堆叠30对准,且将第一LCP外封层23及第二LCP外封层33层压至第一介电层堆叠20及第二介电层堆叠30(框49)。此操作密封装置10(在一些应用中,有可能甚至气密地密封装置10),从而帮助保护电路层12使电路层12在装置10曝露于有害环境时免受氧化影响。
应理解,可使用LCP覆盖层代替LCP焊料掩模16。覆盖层可有利地提供电隔离,且在一些应用中可对电子装置10添加耐挠曲性。
在图6中展示完成的电子装置10,且电子装置10包括衬底11与在所述衬底上的电路层12。电路层12包括焊料衬垫13的阵列。在衬底11上存在LCP焊料掩模16,LCP焊料掩模16具有与焊料衬垫13对准的孔隙18。焊料在孔隙18中以将焊料衬垫13电耦合至电子装置35。第一介电层20在LCP掩模16上,且第一介电层20中具有与焊料衬垫13对准的孔隙24。第一介电层20包括第一介电层22、第一结合层21及第二介电层34的堆叠配置。在第二介电层34上存在第一LCP外封层23。
第二介电层堆叠30处于衬底11上衬底11与LCP焊料掩模16相反的侧上。第二介电层堆叠30包括处于堆叠配置的第二结合层31及第三介电层32。在第三介电层32上存在第二LCP外封层33。熔融接缝51至58在各层之间,且在装置10的横截面中可容易地见到。
Claims (10)
1.一种电子装置,其包括:
衬底;
电路层,其在所述衬底上且包括至少一焊料衬垫;
液晶聚合物焊料掩模,其在所述衬底上且具有与所述至少一焊料衬垫对准的至少一孔隙;
在所述衬底与所述液晶聚合物焊料掩模之间的熔融接缝;
在所述至少一孔隙中的焊料;
至少一电路组件,其经由所述焊料而电耦合至所述至少一焊料衬垫;
第一介电层堆叠,其包括第一多个介电层,所述第一介电层堆叠在所述液晶聚合物焊料掩模上且具有与所述至少一焊料衬垫对准的至少一孔隙;
第一液晶聚合物外封层,其在所述第一介电层堆叠上;
第二介电层堆叠,其包括第二多个介电层,所述第二介电层堆叠处于所述衬底上所述衬底与所述液晶聚合物焊料掩模相反的一侧上;以及
第二液晶聚合物外封层,其在所述第二介电层堆叠上。
2.根据权利要求1所述的电子装置,其中所述第一多个介电层包括在所述液晶聚合物焊料掩模上的第一介电层、在所述第一介电层上的第一结合层,以及在所述第一结合层上的第二介电层。
3.根据权利要求2所述的电子装置,其进一步包括在所述第一介电层与所述液晶聚合物焊料掩模之间的熔融接缝、在所述第一结合层与所述第一介电层之间的熔融接缝、在所述第一结合层与所述第二介电层之间的熔融接缝,以及在所述第二介电层与所述第一液晶聚合物外层之间的熔融接缝。
4.根据权利要求1所述的电子装置,其中所述第二多个介电层包括处于所述衬底上所述衬底与所述液晶聚合物焊料掩模相反的一侧上的第二结合层,以及在所述第二结合层上的第三介电层。
5.根据权利要求4所述的电子装置,其进一步包括在所述第二结合层与所述衬底之间的熔融接缝,以及在所述第二结合层与所述第三介电层之间的熔融接缝,以及在所述第三介电层与所述第二液晶聚合物外层之间的熔融接缝。
6.根据权利要求1所述的电子装置,其中所述衬底包括液晶聚合物衬底。
7.一种制造电子装置的方法,其包括:
在衬底上形成包括至少一焊料衬垫的电路层;
形成液晶聚合物焊料掩模,所述液晶聚合物焊料掩模具有能够与所述至少一焊料衬垫对准的至少一孔隙;
形成第一介电层堆叠及第二介电层堆叠,所述第一介电层堆叠包括处于所述液晶聚合物焊料掩膜上的第一多个介电层并具有可与所述至少一焊料衬垫对准的至少一孔隙,所述第二介电层堆叠包括处于所述衬底上所述衬底与所述液晶聚合物焊料掩膜相反的一侧上的第二多个介电层;
使所述液晶聚合物焊料掩模与所述衬底对准,使所述第一介电层堆叠与所述液晶聚合物焊料掩模对准,且使所述第二介电层堆叠与所述衬底对准;
将所述液晶聚合物焊料掩模层压至所述衬底,将所述第一介电层堆叠层压至所述液晶聚合物焊料掩模,且将所述第二介电层堆叠层压至所述衬底的与所述液晶聚合物焊料掩模相反的一侧;
将焊料膏定位于所述液晶聚合物焊料掩模的所述至少一孔隙中;
使用所述焊料膏将至少一电路组件附接至所述至少一焊料衬垫;以及
分别使第一液晶聚合物外封层及第二液晶聚合物外封层与所述第一介电层堆叠及所述第二介电层堆叠对准且将所述第一液晶聚合物外封层与所述第二液晶聚合物外封层层压至所述第一介电层堆叠与所述第二介电层堆叠。
8.根据权利要求7的方法,其中所述第一介电层堆叠及所述第二介电层堆叠各自被形成为在其中具有至少一导电通孔。
9.根据权利要求7的方法,其中所述第一多个介电层包括在所述液晶聚合物焊料掩模上的第一介电层、在所述第一介电层上的第一结合层,以及在所述第一结合层上的第二介电层;且所述方法进一步包括将所述第一介电层、所述第一结合层及所述第二介电层层压在一起。
10.根据权利要求7所述的方法,其中所述第二多个介电层包括处于所述衬底上所述衬底与所述液晶聚合物焊料掩模相反的一侧上的第二结合层,以及在所述第二结合层上的第三介电层;且所述方法进一步包括将所述第二结合层与所述第三介电层层压在一起。
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-
2011
- 2011-01-14 US US13/007,072 patent/US8472207B2/en active Active
- 2011-12-19 TW TW100147184A patent/TWI473225B/zh active
- 2011-12-20 KR KR1020137016550A patent/KR101450499B1/ko active IP Right Grant
- 2011-12-20 CN CN201180064833.9A patent/CN103299724B/zh not_active Expired - Fee Related
- 2011-12-20 WO PCT/US2011/066151 patent/WO2012096764A1/en active Application Filing
- 2011-12-20 JP JP2013549427A patent/JP2014502792A/ja not_active Withdrawn
- 2011-12-20 EP EP11808518.2A patent/EP2664225B1/en active Active
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EP2664225B1 (en) | 2020-04-22 |
KR20140020843A (ko) | 2014-02-19 |
TW201232734A (en) | 2012-08-01 |
US8472207B2 (en) | 2013-06-25 |
US20120181073A1 (en) | 2012-07-19 |
JP2014502792A (ja) | 2014-02-03 |
CN103299724A (zh) | 2013-09-11 |
EP2664225A1 (en) | 2013-11-20 |
KR101450499B1 (ko) | 2014-10-13 |
WO2012096764A1 (en) | 2012-07-19 |
TWI473225B (zh) | 2015-02-11 |
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