CN103201832B - 创建场效应晶体管器件中的各向异性扩散结 - Google Patents

创建场效应晶体管器件中的各向异性扩散结 Download PDF

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CN103201832B
CN103201832B CN201180054201.4A CN201180054201A CN103201832B CN 103201832 B CN103201832 B CN 103201832B CN 201180054201 A CN201180054201 A CN 201180054201A CN 103201832 B CN103201832 B CN 103201832B
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insulator layer
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B·格林
梁擎擎
J·B·约翰逊
E·玛西朱斯基
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GlobalFoundries Inc
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Abstract

一种用于形成晶体管器件的方法，包括在绝缘体上半导体衬底中注入扩散抑制种类物，该绝缘体上半导体衬底包括大块衬底、隐埋绝缘体层、以及绝缘体上半导体层，绝缘体上半导体层具有在其上形成的一个或多个栅极结构使得扩散抑制种类物被设置在绝缘体上半导体层的与沟道区相对应的部分中，并且被设置在隐埋绝缘体层的与源极和漏极区相对应的部分中。在源极和漏极区中引入晶体管掺杂剂种类物。执行退火以便在基本垂直的方向上扩散晶体管掺杂剂种类物而同时基本防止晶体管掺杂剂种类物横向扩散到沟道区中。

Description

创建场效应晶体管器件中的各向异性扩散结
技术领域
本发明一般性地涉及半导体器件的制造，并且更具体地涉及创建场效应晶体管(FET)器件中的各向异性扩散结。
背景技术
由于集成电路(IC)上的分立器件之间的间距随着每一个新技术的产生而继续缩小，因此这些器件上的元件(例如晶体管栅极电极和间隔物)以及源极和漏极扩散程度，在横向和垂直的方向上都需要相应地减小尺寸。因此，FET缩放已成为半导体工业中的一个重大的挑战。因为对于掺杂分布的突变和浅度的控制由于不可避免的瞬态增强扩散而受到限制，诸如浅注入和降低的热预算的传统缩放技术随着器件尺寸缩小到纳米(nm)级别(regime)而开始停止作用。用于缓和不能越来越多地创建突变结和浅结的能力的一个众所周知的方法是抑穿通(APT)和晕(halo)注入。这些晕注入保护越来越小的FET沟道区免遭源极和漏极注入的侵占，并且因此有助于减少有害短沟道效应(SCE)。然而，得到的高度掺杂的沟道或袋式(pocket)注入区通过增加结电容和带间隧穿(band-to-bandtunneling)而会劣化器件的性能和功耗。
此外，传统的缩放需要同时减小晶体管的横向和垂直方向的尺寸，包括栅极间距、栅极厚度和源极/漏极(S/D)结深度，以维持从一个节点到下一个节点的合理的短沟道控制。然而，在亚90nm技术节点中，其中诸如外延生长的锗硅(eSiGe)和碳化硅(eSiC)的S/D应力诱导元素被并入用于载流子迁移率增强，对S/D结深度进行缩放由于应力损耗而导致器件性能劣化。此外，浅结导致更高的S/D串联电阻，进一步劣化缩放器件的性能。最后，在高性能的绝缘体上硅(SOI)技术中，每个器件的源极和漏极结的某些部分必须足够地侵占隐埋绝缘体(buriedinsulator)，即一种称作“对接”的状态，以便隔离占据相同的毗邻硅区的相邻器件。由于典型的FET(NFET)结经由自对准的掺杂剂注入和随后的热退火而形成，或者通过自对准的腔蚀刻和随后的通过重地原位掺杂的应变硅合金的填充而形成，因此典型地利用相对大的间隔物和高的晕注入以便防止由深的源极/漏极的横向侵占所引起的短沟道劣化。
美国专利7655523B2(Babcock，J.A.等人的“AdvancedCMOSusingSuperSteepRetrogradeWells”，2010年2月2日)公开了用于形成MOS晶体管中的超陡掺杂分布的方法。该方法包括形成含碳层，该含碳层防止掺杂剂扩散到栅极电介质层正下方的区域。
因此，该技术中需要解决上述问题。
发明内容
在一个示例性实施例中，一种形成晶体管器件的方法包括在绝缘体上半导体衬底中注入扩散抑制种类物，该绝缘体上半导体衬底包括大块衬底、隐埋绝缘体层、以及绝缘体上半导体层，该绝缘体上半导体层具有在其上形成的一个或多个栅极结构使得扩散抑制种类物被设置在绝缘体上半导体层的与沟道区相对应的部分中，并且被设置在隐埋绝缘体层的与源极和漏极区相对应的部分中；在源极和漏极区中引入晶体管掺杂剂种类物；以及执行退火以便在基本垂直的方向上扩散晶体管掺杂剂种类物而同时基本防止晶体管掺杂剂种类物横向扩散到沟道区中。
在另一个实施例中，一种形成场效应晶体管(FET)器件的方法包括：在绝缘体上硅(SOI)衬底中注入扩散抑制种类物，该绝缘体上硅(SOI)衬底包括大块衬底、在大块衬底上形成的隐埋氧化层(BOX)、以及在BOX层上形成的SOI层，该SOI层具有在其上形成的一个或多个栅极结构使得扩散抑制种类物被设置在SOI层的与沟道区相对应的部分中，并且设置在BOX的与源极和漏极区相对应的部分中；在源极和漏极区中注入第一、浅晶体管掺杂剂种类物；在源极和漏极区中注入第二、深晶体管掺杂剂种类物；以及执行退火以便基本垂直的方向上扩散第二晶体管掺杂剂种类物而同时基本防止第二晶体管掺杂剂种类物横向扩散到沟道区中。
在另一个实施例中，一种形成场效应晶体管(FET)器件的方法包括在绝缘体上硅(SOI)衬底中注入扩散抑制种类物，该绝缘体上硅(SOI)衬底包括大块衬底、在大块衬底上形成的隐埋氧化层(BOX)、以及在BOX层上形成的SOI层，该SOI层具有在其上形成的一个或多个栅极结构使得扩散抑制种类物被设置在SOI层的与沟道区相对应的部分中，并且被设置在BOX的与源极和漏极区相对应的部分中；在源极和漏极区中注入第一、浅晶体管掺杂剂种类物；在源极和漏极区中使得SOI层的部分凹进；在源极和漏极区中使用原位掺杂有第二、深晶体管掺杂剂种类物的半导体材料来填充SOI层所凹进的部分；以及执行退火以便在基本垂直的方向上扩散第二晶体管掺杂剂种类物而同时基本防止第二晶体管掺杂剂种类物横向扩散到沟道区中。
在另一个实施例中，一种晶体管器件包括：绝缘体上半导体衬底，包括：大块衬底、隐埋绝缘体层、以及绝缘体上半导体层；在绝缘体上半导体层上形成的栅极结构，该栅极结构包括栅极导体和与栅极导体相邻的侧壁间隔物；扩散抑制种类物，被设置在绝缘体上半导体层的与沟道区相对应的部分中，与栅极结构自对准，扩散抑制种类物还被设置在隐埋绝缘体层的与源极和漏极区相对应的部分中；以及在源极和漏极区中引入的晶体管掺杂剂种类物；其中该晶体管掺杂剂种类物在源极和漏极区内具有基本垂直的分布，延伸至隐埋绝缘体层，而沟道区基本没有晶体管掺杂剂种类物。
在另外的一个实施例中，一种场效应晶体管器件包括：绝缘体上硅(SOI)衬底，包括大块衬底、隐埋氧化物(BOX)层、以及SOI层；在SOI层上形成的栅极结构，该栅极结构包括栅极导体和与栅极导体相邻的侧壁间隔物；扩散抑制种类物，被设置在SOI层的与沟道区相对应的部分中，与栅极结构自对准，扩散抑制种类物还被设置在BOX层的与源极和漏极区相对应的部分中；在源极和漏极区中注入的第一、浅晶体管掺杂剂种类物；以及在源极和漏极区中引入的第二、深晶体管掺杂剂种类物；其中第二晶体管掺杂剂种类物在源极和漏极区内具有基本垂直的分布，延伸至BOX层，而沟道区基本没有第二晶体管掺杂剂种类物。
附图说明
现在将参照如下附图所示的优选实施例，仅以示例的方式来描述本发明，附图中：
图1(a)至图1(f)是根据本发明的优选实施例的创建场效应晶体管(FET)器件中的各向异性扩散结的示例性方法的截面图，具体地：
图1(a)是具有在其上形成的一对NFET栅极的绝缘体上硅(SOI)衬底的横面图；
图1(b)示出了用于图1(a)中所示器件的碳种类物的注入；
图1(c)示出了在图1(b)的注入之后在栅极结构下面的SOI层的沟道区中的以及在源极区和漏极区下面的BOX层中的碳区的结果位置；
图1(d)示出了使用第一掺杂剂的图1(c)中所示的器件的浅源极/漏极注入；
图1(e)示出了使用第二掺杂剂的图1(d)中所示的器件的深源极/漏极注入；
图1(f)示出了驱动图1(e)中的第二掺杂剂垂直向下朝着BOX层的水平同时抑制第二掺杂剂垂直侵占到沟道区中的快速热退火(RTA)工艺；
图2(a)至图2(c)是根据本发明的优选实施例创建场效应晶体管(FET)器件中的各向异性扩散结的示例性方法的横面图，具体地：
图2(a)示出了在图1(d)的浅源极/漏极注入之后栅极结构之间的SOI层的凹陷；
图2(b)示出使用原位掺杂有第二掺杂剂的硅或硅合金来对图2(a)中的SOI层的凹陷区域的填充；
图2(c)示出了驱动图2(c)中的第二掺杂剂垂直向下朝着BOX层的水平同时抑制第二掺杂剂垂直侵占到沟道区中的RTA工艺。
具体实施方式
本文所公开的内容是用于创建场效应晶体管(FET)器件中的各向异性扩散结的方法和结构。具体地，公开了用于促进NFET和/或PFETS/D结的垂直扩散并且同时抑制横向扩散的方法的实施例，这些实施例使得能够实现具有相对中等大小的间隔物和减少的晕注入剂量的深源极/漏极。因此，这样的工艺降低NFET和/或PFET的S/D串联电阻，并且使得能够使用更厚的绝缘体上硅(SOI)衬底，这对于eSiGep-型FET(PFET)和eSiCn型FET(NFET)的应力优化是有利的。在以下的描述中，PFET器件中的二氟化硼(BF2)掺杂剂相当于NFET器件中的砷(As)掺杂剂，同时PFET器件中的硼(B)掺杂剂相当于NFET器件中的磷(P)掺杂剂。
在以下示出的实施例中，示出了示例性NFET器件。但是，应当理解本文的原理也同样地适用于PFET器件。
简而言之，实施例实现用于NFETSOI器件的扩散抑制种类物(例如碳)的贯通栅极(through-gate)注入，使得碳被并入栅极下的沟道区(例如硅)中。然而，在S/D区中的其他地方，碳种类物穿过SOI层并且进入SOI层下面的隐埋氧化物(BOX)层。然后，例如，将诸如P的n型掺杂剂注入，或以其掺杂再生长半导体材料进入NFETS/D区中用于深结形成。在这里，众所周知P的扩散将受到碳的抑制。快速热退火(RTA)垂直向下朝着BOX层扩散磷掺杂原子，有效地对接结被并且降低S/D电阻。然而，由于存在先前注入栅极下面的沟道区中的碳材料，与FET沟道有效地自对准的碳基本抑制了磷的横向扩散。
首先参考图1(a)，其中示出了适合于根据本发明的优选实施例使用的、具有在其上形成的一对NFET栅极的绝缘体上半导体(例如，SOI集成电路器件100)的截面图。如所示，器件100包括大块衬底102(例如硅)、BOX层104或形成在大块衬底上的其他适当的绝缘层、薄SOI层106或形成在BOX层104上的其它适当的绝缘体上半导体层。此外，根据现有半导体加工技术在SOI层106之上形成一对NFET栅极结构，各自包括栅极电极108和侧壁间隔物。
然后，如在图1(b)所示，器件经受例如碳的种类物(由箭头表示)的注入，使得碳得以注入到栅极电极108下面的SOI层106的沟道区中，而至于SOI层106的源极/漏极区，碳穿过SOI层并且得以注入到BOX层104内。在图1(c)中示出了得到的中间结构，在图1中将能够观察到在SOI层106中形成的碳区112在栅极电极108侧壁间隔物下自对准，而BOX层104中的碳区112对应于随后形成的(其中不存在栅极结构的)源极/漏极区下面的位置。
现在进入到图1(d)，使用第一n型掺杂剂114执行第一、浅源极/漏极注入。该第一注入与栅极自对准。在一个示例性实施例中，第一n型掺杂剂114是砷(As)，其还在侧壁间隔物下方延伸。砷是对于浅源级/漏极结而选择的掺杂剂，因为其注入后分布相对浅和突变，并且它抵抗瞬态增强扩散。在图1(e)中，使用第二n型掺杂剂执行第二、深源极/漏极注入。该第二注入也与栅极自对准。在一个示例性实施例中，第二n型掺杂剂116是磷(P)。磷是对于深结而选择的种类物，因为相对于砷而言，其注入后分布宽广并且易于做深。然而，在硅中，磷与砷相比扩散的非常快。
图1(f)示出了RAT过程后的第二类型掺杂剂116的扩散。正如将看到的，磷种类物116的扩散绝大多数在垂直方向上朝向BOX层104，这是由于在NFET的沟道区中的碳种类物的存在。不受抑制的垂直扩散使得能够实现对接的和低电阻的结，而避免由掺杂剂横向侵占到器件沟道中所引起的短沟道效应劣化。
如上文所指出的，将要理解的是，虽然已经使用NFET器件对上述实施例进行了描述，但是本文公开的原理同样适用于PFET器件。在这里，二氟化硼(BF2)可以是砷的掺杂剂种类类似物，并且硼(B)可以是磷的掺杂剂种类类似物。至于扩散抑制种类物，氟(F)是可能的NFET和PFET的碳的类似物(虽然不太理想)。
此外，在上述示例性实施例中，通过注入工艺描绘了将第二类型(深)掺杂剂引入到源极/漏极区。但是，在一个替代实施例中，这可能通过SOI蚀刻并且随后利用原位掺杂的半导体材料的源极漏极区的外延再生长来执行。现在参考图2(a)，接着在图1(d)的第一、浅源极/漏极注入过程之后的处理中的点，诸如通过蚀刻使SOI层106的部分凹进。这导致图2(a)中所示的凹进的区域202。然后，如图2(b)所示，使用原位掺杂有适当的第二掺杂剂的外延生长半导体材料204来填充所凹进的区域。在NFET的示例中，掺杂剂可以是磷，而对于PFET的示例，掺杂剂可以是硼。半导体材料例如可以是硅或诸如锗硅(SiGe)的硅合金。也可以使用其他半导体材料。最终，如在图2(c)中所示，RTA工艺扩散外延生长半导体材料204的原位掺杂剂。如同图1(e)的注入的实施例一样，原位种类物的扩散大多数是在垂直方向上，朝向BOX层104，这是由于在NFET和PFET的沟道区中的碳种类物(或者，可替换地，PFET沟道中的氟种类物)的存在。不受抑制的垂直扩散使得能够实现对接的和低电阻的结，而避免由掺杂剂横向侵占到器件沟道所引起的短沟道效应劣化。
虽然已经参考一个或多个优选实施例描述了本发明，但是本领域技术人员将理解，在不偏离本发明的范围的前提下可以进行多种变化并且可以使用等同物来取代其元素。此外，在不偏离本发明的本质范围的前提下，可以作出许多修改以使得特定情形和材料适合于其教导。因此，并不旨在将本发明局限于作为实现本发明的预期的最佳方式所公开的具体实施例，而是旨在本发明将包括落入所附的权利要求的范围内的所有实施例。

Claims (25)

1.一种用于形成晶体管器件的方法，所述方法包括：
在绝缘体上半导体衬底中注入扩散抑制种类物，其中所述绝缘体上半导体衬底包括大块衬底、隐埋绝缘体层、以及绝缘体上半导体层，所述绝缘体上半导体层具有在其上形成的一个或多个栅极结构使得所述扩散抑制种类物被设置在所述绝缘体上半导体层中的直接位于所述一个或多个栅极结构下面的沟道区中，与所述一个或多个栅极结构自对准，并且穿过所述绝缘体上半导体层被设置在所述隐埋绝缘体层中的直接位于所述绝缘体上半导体层中的源极和漏极区下面的部分中；
在所述源极和漏极区中引入晶体管掺杂剂种类物；以及
执行退火以便在垂直的方向上扩散所述晶体管掺杂剂种类物而同时防止所述晶体管掺杂剂种类物横向扩散到所述沟道区中。
2.根据权利要求1所述的方法，其中所述引入所述晶体管掺杂剂种类物的步骤包括步骤：在所述源极和漏极区中向下垂直扩散到所述隐埋绝缘体层的水平。
3.根据权利要求1或2任一项所述的方法，其中所述绝缘体上半导体层包括绝缘体上硅层，并且所述隐埋绝缘体层包括隐埋氧化物层。
4.根据权利要求1或2任一项所述的方法，其中：
所述晶体管器件包括n型场效应晶体管(NFET)；
所述扩散抑制种类物包括碳；以及
所述晶体管掺杂剂种类物包括磷。
5.根据权利要求1或2任一项所述的方法，其中：
所述晶体管器件包括p型场效应晶体管(PFET)；
所述扩散抑制种类物包括氟；以及
所述晶体管掺杂剂种类物包括硼。
6.根据权利要求1所述的方法，其中：
所述在所述绝缘体上半导体衬底中注入所述扩散抑制种类物的步骤包括步骤：在绝缘体上硅衬底中注入所述扩散抑制种类物，所述绝缘体上硅衬底包括大块衬底、在所述大块衬底上形成的隐埋氧化物层，以及在所述隐埋氧化物层上形成的绝缘体上硅层，所述绝缘体上硅衬底具有在其上形成的一个或多个场效应晶体管栅极结构使得所述扩散抑制种类物被设置在所述绝缘体上硅层中的直接位于所述一个或多个场效应晶体管栅极结构下面的沟道区中，与所述一个或多个场效应晶体管栅极结构自对准，并且穿过所述绝缘体上硅层被设置在所述隐埋氧化物层中的直接位于所述绝缘体上硅层中的源极和漏极区下面的部分中；
所述引入所述晶体管掺杂剂种类物的步骤包括步骤：
在所述源极和漏极区中注入第一浅晶体管掺杂剂种类物；以及
在所述源极和漏极区中注入第二深晶体管掺杂剂种类物；以及
所述执行退火的步骤包括步骤：执行退火以便在垂直的方向上扩散所述第二深晶体管掺杂剂种类物而同时防止所述第二深晶体管掺杂剂种类物横向扩散到所述沟道区中。
7.根据权利要求6所述的方法，其中：
所述晶体管器件包括n型场效应晶体管(NFET)；
所述扩散抑制种类物包括碳；
所述第一浅晶体管掺杂剂种类物包括砷；以及
所述第二深晶体管掺杂剂种类物包括磷。
8.根据权利要求6所述的方法，其中：
所述晶体管器件包括p型场效应晶体管(PFET)；
所述扩散抑制种类物包括氟；
所述第一浅晶体管掺杂剂种类物包括二氟化硼；以及
所述第二深晶体管掺杂剂种类物包括硼。
9.根据权利要求6至8中任一项所述的方法，其中所述第二深晶体管掺杂剂种类物在所述源极和漏极区中向下垂直扩散到所述隐埋氧化物层的水平。
10.根据权利要求1所述的方法，其中：
所述在绝缘体上半导体衬底中注入扩散抑制种类物的步骤包括步骤：在绝缘体上硅衬底中注入所述扩散抑制种类物，所述绝缘体上硅衬底包括大块衬底、在所述大块衬底上形成的隐埋氧化物层、以及在所述隐埋氧化物层上形成的绝缘体上硅层，所述绝缘体上硅衬底具有在其上形成的一个或多个场效应晶体管栅极结构使得所述扩散抑制种类物被设置在所述绝缘体上硅层中的直接位于所述一个或多个场效应晶体管栅极结构下面的沟道区中，与所述一个或多个场效应晶体管栅极结构自对准，并且穿过所述绝缘体上硅层被设置在所述隐埋氧化物层中的直接位于所述绝缘体上硅层中的源极和漏极区下面的部分中；
所述引入晶体管掺杂剂种类物的步骤包括步骤：
在所述源极和漏极区中注入第一浅晶体管掺杂剂种类物；
在所述源极和漏极区中使得所述绝缘体上硅层的部分凹进；以及
使用在所述源极和漏极区中原位掺杂有第二深晶体管掺杂剂种类物的半导体材料来填充所凹进的部分；以及
所述执行退火的步骤包括：执行退火以便在垂直的方向上扩散所述第二深晶体管掺杂剂种类物而同时防止所述第二深晶体管掺杂剂种类物横向扩散到所述沟道区中。
11.根据权利要求10所述的方法，其中所述原位掺杂有第二深晶体管掺杂剂种类物的半导体材料包括硅和含硅合金中的一个。
12.根据权利要求10或11任一项所述的方法，其中：
所述晶体管器件包括n型场效应晶体管(NFET)；
所述扩散抑制种类物包括碳；
所述第一浅晶体管掺杂剂种类物包括砷；以及
所述第二深晶体管掺杂剂种类物包括磷。
13.根据权利要求10或11任一项所述的方法，其中：
所述晶体管器件包括p型场效应晶体管(PFET)；
所述扩散抑制种类物包括氟；
所述第一浅晶体管掺杂剂种类物包括二氟化硼；以及
所述第二深晶体管掺杂剂种类物包括硼。
14.一种晶体管器件，包括：
绝缘体上半导体衬底，包括：大块衬底、隐埋绝缘体层、以及绝缘体上半导体层；
在所述绝缘体上半导体层上形成的栅极结构，所述栅极结构包括栅极导体和与所述栅极导体相邻的侧壁间隔物；
扩散抑制种类物，被设置在所述绝缘体上半导体层中的直接位于所述栅极结构下面的沟道区中，与所述栅极结构自对准，所述扩散抑制种类物还穿过所述绝缘体上半导体层被设置在所述隐埋绝缘体层中的直接位于所述绝缘体上半导体层中的源极和漏极区下面的部分中；
在所述源极和漏极区中引入的晶体管掺杂剂种类物；
其中所述晶体管掺杂剂种类物在所述源极和漏极区内具有垂直的分布，延伸至所述隐埋绝缘体层，而所述沟道区没有所述晶体管掺杂剂种类物。
15.根据权利要求14所述的器件，其中所述晶体管器件是n型场效应晶体管(NFET)。
16.根据权利要求15所述的器件，其中所述扩散抑制种类物包括碳，并且所述晶体管掺杂剂种类物包括磷。
17.根据权利要求14所述的器件，其中所述晶体管器件是p型场效应晶体管(NFET)。
18.根据权利要求17所述的器件，其中所述扩散抑制种类物包括氟，并且所述晶体管掺杂剂种类物包括硼。
19.根据权利要求14所述的器件，其中所述绝缘体上半导体层包括绝缘体上硅层，并且所述隐埋绝缘体层包括隐埋氧化物层。
20.根据权利要求14所述的器件，其中：
所述绝缘体上半导体衬底是绝缘体上硅衬底；所述隐埋绝缘体层包括隐埋氧化物层；所述绝缘体上半导体层包括绝缘体上硅层；
所述栅极结构形成在所述绝缘体上硅层上；
所述扩散抑制种类物被设置在所述绝缘体上硅层中的直接位于所述栅极结构下面的沟道区中，与所述栅极结构自对准，所述扩散抑制种类物穿过所述绝缘体上半导体层被设置在所述隐埋氧化物层中的直接位于所述绝缘体上半导体层中的源极和漏极区下面的部分中；
以及
所述晶体管掺杂剂种类物还包括在所述源极和漏极区中注入的第一浅晶体管掺杂剂种类物；以及在所述源极和漏极区中引入的第二深晶体管掺杂剂种类物；
其中所述第二深晶体管掺杂剂种类物在所述源极和漏极区内具有垂直的分布，延伸至所述隐埋氧化物层，而所述沟道区没有所述第二深晶体管掺杂剂种类物。
21.根据权利要求20所述的器件，其中：
所述器件包括n型场效应晶体管(NFET)；
所述扩散抑制种类物包括碳；
所述第一浅晶体管掺杂剂种类物包括砷；以及
所述第二深晶体管掺杂剂种类物包括磷。
22.根据权利要求20所述的器件，其中：
所述器件包括p型场效应晶体管(PFET)；
所述扩散抑制种类物包括氟；
所述第一浅晶体管掺杂剂种类物包括二氟化硼；以及
所述第二深晶体管掺杂剂种类物包括硼。
23.根据权利要求20至22中任一项所述的器件，其中所述第二深晶体管掺杂剂种类物是注入的种类物。
24.根据权利要求20至22中任一项所述的器件，其中所述源极和漏极区包括原位掺杂有所述第二深晶体管掺杂剂种类物的外延生长半导体材料。
25.根据权利要求24所述的器件，其中所述原位掺杂有所述第二深晶体管掺杂剂种类物的外延生长半导体材料包括硅和含硅合金中的一个。
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