CN103178059B - 功率集成电路器件 - Google Patents

功率集成电路器件 Download PDF

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CN103178059B
CN103178059B CN201310087472.0A CN201310087472A CN103178059B CN 103178059 B CN103178059 B CN 103178059B CN 201310087472 A CN201310087472 A CN 201310087472A CN 103178059 B CN103178059 B CN 103178059B
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effect transistor
resistor
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CN103178059A (zh
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V·帕塔萨拉蒂
S·班纳吉
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Power Integrations Inc
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Abstract

本发明涉及功率集成电路器件，所述功率集成电路器件包括主横向高压场效应晶体管（HVFET）和邻近定位的横向sense FET，该HVFET和sense FET两者都形成在一高电阻率衬底上。检测电阻器形成于布置在该HVFET和sense FET之间的所述衬底的一区域中的阱区中。衬底寄生电阻器形成为与该HVFET的和sense FET的源极区之间的该检测电阻器并联地电连接。两个晶体管器件共用公共的漏极和栅极电极。当该主横向HVFET和sense FET处于导通状态时，在第二源极金属层处产生一电势，该电势与流过该横向HVFET的第一电流成比例。

Description

功率集成电路器件
本申请是申请日为2010年5月28日、申请号为201010188478.3、名称为“具有内含式电流检测场效应晶体管的功率集成电路器件”的发明专利申请的分案申请。
背景技术
本公开内容涉及半导体器件、器件结构，以及用于制作高压集成电路或功率晶体管器件的方法。
背景技术
电流检测场效应晶体管（current sensing field-effecttransistor）,亦常常称作sense FET，其已被用于集成电路应用长达多年，其中精确的电流检测可提供信息供用于控制和过保护两者。Sense FET一般被构造为较大的主载流半导体器件的一个小部分或晶体管部分。例如，在常规绝缘栅场效应晶体管（MOSFET）器件中，senseFET可包括主器件的沟道区的一小部分。在运行中，sense FET可对较大器件的沟道电流的一小部分取样，从而提供关于流过主晶体管器件的电流的指示。Sense FET和主器件一般共用一个公共漏极和栅极，但是各具有单独的源极电极，该源极电极可对体区短路，也可不对体区短路。
Sense FET尤其可用于许多功率传送应用中，以提供限流保护和精确的功率传送。为了提供这些功能，sense FET需要在很宽的漏电流（100mA至10安培）、温度（-25℃至125℃）以及制造工艺变化和机械应力/封装变化范围内相对于主高压FET维持恒定的电流检测比例（CSR）。主高压FET（HVFET）的漏电流与sense FET的漏电流之比一般在20:1-800:1的范围内或更大。
横向场效应晶体管广泛用于高压（例如，高于400伏）集成电路应用中。在横向HVFET结构中，由一沟道区将源极区与扩展漏极区或漂移区横向隔开。栅极结构布置在沟道区之上，通过薄氧化物层与在下面的半导体材料绝缘。在导通状态，施加到栅极的合适电压导致在源极区和扩展漏极区之间形成横向导通沟道，从而允许电流横向流过器件。在截止状态，栅极上的电压足够低，使得没有导通沟道在衬底中形成，因而没有电流流动。在截止状态，器件承受漏极区和源极区之间的高压。
在用于具有横向HVFET器件的功率IC中的sense FET的设计中出现的困难之中，存在漏极电压去偏置和体效应问题。漏极电压的去偏置可在检测电阻器（一般联接在源极和地之间）为sense FET电阻的大百分比（例如，>25％）从而导致在检测电阻器两端有大压降时出现。这相对于栅极提高了sense FET的源极电压，从而相对于主HVFET降低了sense FET的栅极-源极驱动。类似地，在其中本体物理地连接至衬底的横向HVFET中，sense FET的本体需要与源极隔开。这导致sense FET的阈值电压随电流增加，损害了sense FET对主HVFET器件的跟踪。另外，过去试图将sense FET物理上靠近主HVFET定位（例如，位于共用的阱区中）以改善跟踪，而这是有问题的，因为这样做会影响器件中的电荷平衡，导致较低的击穿电压（BV）。另一个缺点是，检测元件——一般是远离HVFET区一定距离定位的电阻器——的位置。这导致对HVFET的不良匹配。
附图说明
根据接下来的详细描述以及附图将更充分理解本公开内容，然而所述详细描述和附图不应被解释成将本发明限制于所示出的特定实施方案，而是仅用于说明和理解。
图1是包含在横向HVFET结构中的一示例性sense FET的侧视横截面图。
图2是图1中示出的集成器件的示例性电路示意图。
图3是包含在横向HVFET结构中的另一示例性sense FET的侧视横截面图。
图4是图3中示出的集成器件的示例性电路示意图。
图5是包含在横向HVFET结构中的一sense FET的示例性布局的顶视图。
具体实施方案
在以下描述中阐述了各种特定细节，诸如材料类型、尺寸、结构特征、处理步骤等，以提供对本发明的透彻理解。然而，相关领域的普通技术人员将意识到，实施本发明可以不需要这些特定细节。还应理解，图中的元件是代表性的，为清楚起见未按比例绘制。
图1示出了半导体器件10的示例性侧视横截面图，半导体器件10包括主横向HVFET 30和相邻的sense FET 31，所述主横向HVFET 30和sense FET 31都被形成在轻掺杂（高电阻率）P型硅衬底11上。衬底11一般是轻掺杂的，以增加其对P型体区36和16之间流动的寄生电流的电阻，该电阻在图1中用电阻器50（Rsub）示出。在一个实施方案中，P衬底11被掺杂至在大约1×1013cm-3到大约1×1014cm-3的范围内的浓度，具有大约100-1000欧姆-cm的电阻率。
主HVFET 30包括布置在轻掺杂（例如，2×1016cm-3）N阱区12中的N＋漏极区13，该轻掺杂N阱区12横向延伸到较重掺杂（例如，1×1017cm-3）的P体区16。从N＋区13延伸到毗连P体区16的N阱12的侧边界的N阱12的部分包括横向HVFET 30的扩展漏极区或漂移区。大部分扩展漏极半导体材料被布置在相对厚（～1μm）的场氧化物层18之下。P＋区17和N＋源极区15被布置在衬底表面处的P体区16内。应意识到，横向HVFET 30的扩展漏极区可包括位于p型体区16和N＋漏极区13之间的多个平行的N型漂移区。
HVFET 30还包括栅极14，该栅极14例如由多晶硅和栅极绝缘层20组成，该栅极绝缘层20将栅极14与在下面的半导体区绝缘。栅极绝缘层20可包括薄的普通二氧化硅层或其他合适的介电绝缘材料层。如可看到的，栅极14在衬底之上从N＋源极区15横向延伸到刚刚过在N阱区12之上的场氧化物层18的最左边缘。厚（～1.5μm）层间电介质（ILD）19将栅极14与源极金属层（电极）21绝缘。金属层21电接触HVFET 30的P＋区17和N＋源极区15。漏极金属层（电极）22电接触HVFET 30的N＋区13以及sense FET 31的N＋漏极区33。换句话说，sense FET 31和HVFET 30的漏极区在器件10中电联接在一起。
在一个实施方案中，源极电极和漏极电极包括铝；然而，半导体领域的技术人员将意识到，在替代实施方案中，源极电极和漏极电极可包括其它金属、合金或导电材料（例如，多晶硅）。
Sense FET 31的器件结构与HVFET 30的器件结构成镜像，不过应意识到，为了获得更大的电流处理能力，主HVFET 30一般被制作为大得多的横向晶体管器件。在图1的实施方案中，sense FET 31被显示为邻近于HVFET 30布置，并包括毗连P体区36的N阱区32。N＋源极区35和P＋区37均被布置在P体区36中，源极区35的侧边缘与邻接N阱32的P体区36的侧边界隔开一小段距离。栅极24在P体区36的该区域之上从N＋源极区35的上述边缘横向延伸到刚刚过在N阱区32之上的场氧化物层18的最左边缘。由薄栅极绝缘层40将栅极24与在下面的半导体衬底绝缘，该薄栅极绝缘层40一般包括热生长氧化物。N＋源极区35和P＋区37均电联接到源极金属层41。源极金属层41被显示为借助ILD 19与栅极24绝缘。
Sense FET 31和HVFET 30被布置在高电阻率P衬底11中，互相隔开一距离“d3”。将两个场效应晶体管隔开的横向区域包括N阱区25和在N阱区25的最左边缘或边界与sense FET 31的P体区36的最右边缘或边界之间的P衬底11的一个小区域。场氧化物层18覆盖在器件的该小区域中的衬底的顶部。距离d3等于N阱区25的横向宽度（距离“d2”）加上将N阱25与P本体36隔开的P衬底11的该小区域的宽度（距离“d1”）之和。
在一个特定实施方案中，图1中将sense FET 31的P体区36与HVFET 30的P体区16隔开的距离d3约为75μm。在其它实施方案中，该距离可从5μm上至100μm或更大，这取决于布局的几何形状、N阱25的掺杂浓度、电阻器50和51的期望值等。此外，采用合适的间距，可将电阻器50的衬底寄生电阻Rsub最小化。
注意，在示出的实施方案中，电阻器50（Rsub）由衬底11的P型半导体材料形成，而电阻器51由N阱25的N型半导体材料形成。因而，在图1示出的器件结构中，电阻器50（Rsub）与电阻器51（Rsense）并联连接。该配置允许Rsense可比Rsub低约50-100倍以使其对senseFET 31的跟踪精确性的影响最小化。在一个实施方案中，Rsense＝5欧姆，Rsub＝500欧姆，HVFET 30和sense FET 31的器件电阻值（漏极-源极）分别是1欧姆和25欧姆。在其它实施方案中，电阻Rsense与sense FET 31的器件电阻之比在约10：1到4：1的范围内。Rsub与Rsense之比可在10：1和800：1或更高之间变化。此外，应理解，电阻器51可被实现为多个分离的阱区的组合，所述多个分离的阱区中的一个或多个通过多个N＋触点（例如，触点27和26）连接到P体区36和16。
从业者将理解，N阱区12、25和32中的每个可使用相同的掩模/注入/扩散步骤形成，使得这些区中的每个都具有相同的掺杂浓度和导电性。类似地，P体区16和36可以以相同的处理步骤形成。N＋区13、15、26、27、35和33也可在单个处理步骤序列中被形成。本领域技术人员将意识到，通过使用相同的处理步骤来制作半导体器件结构的相似的、相邻定位的区（例如，N阱区），实现器件特性（例如，senseFET跟踪）的更大一致性。这还简化了整个制作过程。
半导体领域的从业者还将意识到，由于sense FET 31和HVFET 30两者邻近彼此布置，sense FET 31的电流跟踪精确度是优异的，但sense FET的体区36和源极区35仍与HVFET 30充分隔开，而不损害HVFET 30的BV，因为N阱区32和12被分别从P体区36和16向后拉。此外，因为电阻器Rsense通过与用来制作sense FET 31和HVFET 30的扩展漏极（N阱）区的注入/扩散步骤相同的注入/扩散步骤来形成，并物理地位于在这两个晶体管之间的布局的中心，所以实现了非常高的工艺和封装匹配，结果导致恒定的电流检测比例。此外，因为Rsense电阻器51紧邻sense FET 31集成，可发送出IC的功率器件区并进入同一IC的控制器部分的检测FET信号是一电压信号，而非电流信号。换句话说，源极金属41可被引导到IC的控制器部分，以提供一用作功率器件的控制信号的节点电压。
在图1的实施方案中，N阱25的最右边缘邻接或毗连HVFET 30的P体区16的最左边缘。两个N＋区26和27分别接近N阱25的相对侧端布置在N阱25中。N＋区26电连接到源极金属21，该源极金属21还被联接到横向HVFET 30的源极区15。N＋区27电连接到源极金属41，该源极金属41还被联接到sense FET 31的源极区35。因此源极区21和41通过由N阱25中的半导体材料所形成的电阻器51（Rsense）被电连接。当然，电阻器51的电阻取决于N阱25的掺杂水平以及N＋触点区26与27之间的间隔距离。
在另一实施方案中，可在N阱区12、25和32中的每个中布置一个或多个竖向堆叠的、竖向隔开的P型埋层，以在其中形成多个横向JFET导通沟道。例如，可通过注入合适的掺杂剂在这些N阱区的每个中形成多个P型埋层，使得每个P埋层完全布置在相应的N阱区内（即，四面八方都被相应的N阱区围绕）。以此方式，每个P埋层与所有其他P埋层隔开。最上面的P埋区可被布置在N阱区的上表面以下或与之重合。在一具体实现中，每个P埋层中的掺杂浓度可在大约1×1012/cm3到大约2×1012/cm3的范围内。因为通过在每个N阱中包含P埋层而形成的JFET沟道的电阻与这些沟道中的总电荷成反比，所以每个附加的P埋层导致HVFET和sense FET器件的导通电阻减小。
图2的电路示意图图解了横向HVFET 30和sense FET 31共用一个公共栅极节点14和公共漏极节点22。注意，电阻器50和51并联连接在sense FET 31的源极金属层（节点）41和地之间，而HVFET 30的源极金属层（节点）21直接连接至地电势。如在上文说明的，senseFET 31的源极节点41可被用来对与流过大得多的横向晶体管器件30的电流的一小部分成比例的一电压进行采样，从而提供流过HVFET 30的电流的指示。
图3是包含在横向HVFET结构中的另一示例性sense FET的侧视横截面图。图2的器件60以与图1的器件相同的方式配置和制作，只是检测电阻器Rsense不再被引入在HVFET 30和sense FET 31之间的布局的中心位置。在该实施方案中，检测电阻器Rsense布置在衬底的另一区域中（在器件60附近或远离器件60）。在图3中，P体区16和36被显示为隔开一距离d4，该距离可在5-100μm的范围内，这取决于器件的布局。场氧化物层18在衬底11的侧面之上在P体区16和36之间延伸。
图4是图3中示出的集成器件的示例性电路示意图。注意，HVFET30和sense FET 31各自的源极节点21和41通过器件60内的高电阻率P衬底电阻器50电联接。另外，检测电阻器55（被显示在器件60外）被显示为并联连接在节点21和41之间。源极节点21被显示为接地。在图3和4的实施方案中，源极节点21可被联接到功率IC的控制器部分，以提供代表流过横向HVFET 30的电流的电压信号。
图5是包含在横向HVFET结构中的sense FET的示例性布局的顶视图。注意，在该实施方案中，单个N阱区45被用来形成所述senseFET和HVFET晶体管器件两者的扩展漏极区。N阱区45的最左侧边缘或边界毗连两个分开的P体区47a和47b，这两个分开的P体区47a和47b分别与主横向HVFET器件和sense FET相关联。一组交替的P＋和N＋区57和58分别被显示为布置在每个P体区47内。例如，N＋源极区58a被显示为插在主P体区47a中的每个P＋区57a之间。类似地，N＋源极区58b被显示为插在主P体区47b中的每个P＋区57b之间。单个伸长的栅极构件46被显示为在x方向上从（在P体区47之上的）区57和58中的每个的右手边缘横向地延伸至N阱45之上的一小段距离。栅极46在y方向上从检测FET的P体区47b的顶边缘横向地延伸到主P体区47a的底边缘。
在图5中，P体区47a和47b被显示为隔开一距离d5，在该实施方案中该距离d5约为5μm。在该实施方案中，仅高电阻率P型衬底11将P体区47a和47b隔开。也就是说，检测电阻器未被包含在图5中示出的器件布局中。
尽管结合特定器件类型描述了上述实施方案，但本领域的普通技术人员将意识到，在本发明的范围内多种改型和变体是合适的。例如，尽管描述了HVFET，但所示出的方法、布局和结构同样适用于其它结构和器件类型，包括肖特基、二极管、IGBT和双极型结构。此外，尽管描述了n沟道器件，但应意识到，通过各种半导体区的导电类型方面的适当改变也可实现p沟道器件结构。另外，以示例方式示出的实施方案既适用于单一RESURF横向结构又适用于多RESURF横向结构。因此，说明书和附图应被视为说明性的而非限制性的。

Claims (11)

1.一种功率集成电路器件，包括：
具有第一导电类型的衬底；
横向高压场效应晶体管，其包括：第一漏极区，其布置在具有与所述第一导电类型相反的第二导电类型的第一阱区中；第一源极区，其布置在具有所述第一导电类型的第一体区中；以及，第一源极电极，电连接到所述第一源极区；
电流检测场效应晶体管，与所述横向高压场效应晶体管横向间隔开，所述电流检测场效应晶体管包括：第二漏极区，其布置在具有所述第二导电类型的第二阱区中；第二源极区，其布置在具有所述第一导电类型的第二体区中；以及，第二源极电极，电连接到所述第二源极区；
具有所述第二导电类型的第三阱区，其横向布置在介于所述第一和第二体区之间的所述衬底的区域中，检测电阻器形成于所述第三阱区中的间隔开的第一和第二触点区之间，所述第一源极电极电连接到所述第一触点区，所述第二源极电极电连接到所述第二触点区，其中当所述横向高压场效应晶体管和所述电流检测场效应晶体管处于导通状态时，在所述第二源极电极处产生一电势，该电势与流过所述横向高压场效应晶体管的第一电流成比例。
2.如权利要求1所述的功率集成电路器件，还包括衬底寄生电阻器，所述衬底寄生电阻器在所述第一和第二体区之间布置在所述衬底中，所述衬底寄生电阻器具有的值比所述检测电阻器的电阻大至少25倍。
3.如权利要求2所述的功率集成电路器件，还包括具有所述第一导电类型的第三和第四触点区，该第三和第四触点区分别布置在所述第一和第二体区中，所述第一源极电极电接触所述第三触点区且所述第二源极电极电接触所述第三触点区，使得所述衬底寄生电阻器与所述第一和第二源极电极之间的所述检测电阻器并联连接。
4.如权利要求1所述的功率集成电路器件，其中所述检测电阻器的电阻比所述电流检测场效应晶体管的器件电阻小至少4倍。
5.如权利要求1所述的功率集成电路器件，其中所述电流检测场效应晶体管的器件电阻比所述横向高压场效应晶体管的器件电阻大至少10倍。
6.如权利要求1所述的功率集成电路器件，其中所述第三阱区在所述衬底的表面处与所述第二体区隔开一第一距离。
7.如权利要求6所述的功率集成电路器件，其中一第二距离将所述第一和第二体区隔开，该第二距离大于所述第一距离。
8.一种功率集成电路器件，包括：
衬底；
横向高压场效应晶体管，其布置在所述衬底中，所述横向高压场效应晶体管具有源极区和漏极区以及栅极，所述源极区布置在第一体区中；
横向电流检测场效应晶体管，其邻近所述横向高压场效应晶体管布置在所述衬底中，所述横向电流检测场效应晶体管具有源极区和漏极区以及栅极，所述横向电流检测场效应晶体管的源极区布置在第二体区中，所述横向电流检测场效应晶体管在所述衬底的表面处与所述横向高压场效应晶体管横向隔开一第一距离；
衬底寄生电阻器，形成在所述横向高压场效应晶体管的所述第一体区和所述横向电流检测场效应晶体管的所述第二体区之间；以及，
检测电阻器，其联接在所述横向高压场效应晶体管的第一源极电极和所述横向电流检测场效应晶体管的第二源极电极之间，所述第一和第二源极电极被电阻性地连接到所述第一和第二体区，使得所述检测电阻器和所述衬底寄生电阻器并联联接。
9.如权利要求8所述的功率集成电路器件，其中所述衬底寄生电阻器具有第一电阻，该第一电阻比所述检测电阻器的第二电阻大至少20倍。
10.如权利要求9所述的功率集成电路器件，其中所述第二电阻比所述横向电流检测场效应晶体管的第一器件电阻小至少4倍。
11.如权利要求1或8所述的功率集成电路器件，其中所述高压场效应晶体管和所述电流检测场效应晶体管中的每一个都具有一组交替的P+和N+区，所述高压场效应晶体管和所述电流检测场效应晶体管具有的所述组交替的P+和N+区分别被布置在所述第一和第二体区中。
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