CN103109371A - 集成鳍式场效应晶体管(finfet)及其制作方法 - Google Patents
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Abstract
一种集成鳍式场效应晶体管(FinFET)和在块体晶片上制作这种装置(具有浅沟槽隔离(STI)区域上方的EPI界定的鳍高)的方法。在半导体块体内FinFET通道位于STI区域上面,而鳍片延伸超过所述STI区域进入被植入所述半导体块体内的源极和漏极区域。在具有块体源极和漏极区域的情况下,提供减小的外部FinFET电阻,且在鳍片延伸至块体源极和漏极区域的情况下,提供相比于传统绝缘体上硅(SOI)装置的改善的热性质。
Description
技术领域
本公开内容涉及多栅极场效应晶体管(FET),诸如金属氧化物半导体场效应晶体管(MOSFET)且尤其涉及鳍式场效应晶体管,也称FinFET。
发明背景
可能现代电子系统中的单个最重要装置是MOSFET。这种装置不仅用作晶体管,而且还用作被动装置,诸如电阻和电容。将这种装置调小为愈来愈小的尺寸的能力已允许电子系统变小至实现许多手持和袖珍系统的程度。但是,在当前装置调节速度下,预计平面晶体管不久将在使大小最小化方面达到其极限。此外,随着这些装置变得更小,其日益遭受不合需要的短通道效应,诸如关闭状态泄漏电流,其增大装置的功率消耗。
因此,多栅极MOSFET越来越受关注,这是基于其在多个表面上使用多个栅极,从而更有效地抑制关闭状态泄漏电流。此外,这些多栅极允许打开状态中的增强电流,即驱动电流。这些优点导致较低功率消耗和更强的装置性能。此外,这些非平面装置比传统平面晶体管更小,从而实现甚至更高的电路密度且因此实现更小的系统大小。
已开发的一种特定多栅极MOSFET是FinFET,其中导电通道围绕充当装置主体的薄硅“鳍片”安置。鳍片的尺寸创建晶体管的有效通道长度。
传统FinFET使用绝缘体上硅(SOI)技术制作。但是,这类装置通常具有不良的热性质,例如,不良的热消散以及相对较大的外部电阻。因此,可能需要改进的FinFET。
附图简述
图1是根据示例性实施方案的集成FinFET的平面图。
图2至图5是分别沿着线2a至线2d的图1FinFET的横截面图。
图6至图8是图1装置的浅沟槽隔离(STI)制造期间的横截面图。
图9至图12是使用TEOS氧化物的浅沟槽隔离的制作的横截面图。
图13是图示N井和P井植入的横截面图。
图14至图15是EPI生长的横截面图。
图16至图17是EPI硬掩膜沉积的横截面图。
图18至图19是EPI鳍片心轴制作的横截面图。
图20和图21是心轴间隔体制作的横截面图。
图22至图23是间隔体蚀刻的横截面图。
图24至图25是心轴移除的横截面图。
图26至图27是鳍片硬掩膜蚀刻的横截面图。
图28至图29是间隔体移除的横截面图。
图30至图31是鳍片蚀刻的横截面图。
图32至图33是隔离不合需要的鳍片进行移除的横截面图。
图34至图35是移除不合需要的鳍片的横截面图。
图36至图37是移除用于隔离不合需要的鳍片的抗蚀剂的横截面图。
图38至图39是高K栅极材料沉积的横截面图。
图40至图41是金属栅极沉积的横截面图。
图42至图43是金属栅极硬掩膜的横截面图。
图44至图45是金属栅极抗蚀剂沉积的横截面图。
图46至图47是硬掩膜蚀刻的横截面图。
图48是抗蚀剂移除的横截面图。
图49至图51是金属栅极和高K栅极蚀刻的横截面图。
图52至图53是间隔体沉积和蚀刻的横截面图。
图54至图55是P源极/漏极和N源极/漏极植入物的横截面图。
图56至图57是P-EPI和N-EPI合并的横截面图。
图58至图59是TEOS氧化物沉积的横截面图。
图60是局部互连件制作的横截面图。
图61是根据替代示例性实施方案的FinFET的平面图。
图62至图65是分别沿着线13la至线131d的图61装置的横截面图。
图66是传统FinFET的平面图。
图67至图70是分别沿着线233a至线233d的图66装置的横截面图。
具体实施方式
下文详细描述是目前参考附图要求的发明的示例性实施方案。此描述旨在作为说明性的且非对本发明范围进行限制。这些实施方案足够详细地描述以使本领域一般技术人员能够实践本发明且应了解可实践存在一些变化的其它实施方案而不脱离本发明的精神或范围。
提供一种集成鳍式场效应晶体管(FinFET)和在块体晶片上制作这种装置(具有浅沟槽隔离(STI)区域上方的EPI界定的鳍高)的方法。在半导体块体内FinFET通道位于STI区域上面,而鳍片延伸超过STI区域进入被植入半导体块体内的源极和漏极区域。在具有块体源极和漏极区域的情况下,提供减小的外部FinFET电阻,且在鳍片延伸至块体源极和漏极区域的情况下,提供相比于传统绝缘体上硅(SOI)装置的改善的热性质。
有利地,这样一种装置通过允许源极和漏极区域位于块体中且更靠近通道而使外部电阻最小化。更有利地,基于未掺杂通道外延(EPI)的鳍片安置在浅沟槽隔离(STI)上方使得EPI层允许更好地控制鳍高而具较小可变性和更一致的鳍片,例如无底切。更有利地,这样一种装置允许来自在STI层中引入附加应变以及来自块体源极和漏极区域的性能增强。更有利地,热消散随鳍片用块体基板连接到源极和漏极区域而增强。
根据示例性实施方案,FinFET通道将完全在STI上方而鳍片延伸超过STI进入块体源极和漏极区域。源极和漏极区域可使用传统源极和漏极植入物以及下方的井形成。与SOI相比,鳍片延伸至块体源极和漏极区域中允许类似于使用传统块体技术的改进热性质。在STI上方具有FinFET通道的情况下,通道区域中的鳍高由STI上方的沉积EPI层确定。块体源极和漏极区域帮助减小外部电阻。装置架构包括有关通道和栅极下方的STI层中以及来自块体源极和漏极区域的应变增强技术的灵活性。
参考图1和图2至图5,大体如所示,根据示例性实施方案的FinFET1包括块体源极和漏极以及EPI合并区域3、浅沟槽隔离4、栅极电极5、外延鳍片6、EPI合并7、P型源极和漏极区域8、间隔体9、局部互连件10、P型块体基板11、P井12、N井13、高K膜14、N源极和漏极区域15、硅化物16、栅极硬掩膜17和TEOS区域18。如下文更详细所述,浅沟槽隔离(STI)区域安置在块体内,源极和漏极区域安置在相邻STI区域之间。鳍片大致垂直于STI区域安置,其部分安置在STI区域上方且其其它部分安置在源极和漏极区域内。每个栅极电极安置在每个鳍片的部分上方且侧向远离源极和漏极区域,即非源极和漏极区域上方。
如下文所述的处理步骤本质上是传统的且因此为本领域一般技术人员所知。讨论处理步骤的顺序不旨在必定作为这些处理步骤可实践的顺序,而是举例示出。
参考图6至图8,如沿着线2c和线2d所见(图1),光致抗蚀剂21沉积在块体11上方并且被蚀刻掉以产生STI沟槽22、23。
参考图9至图12,或如分别沿着线2c和线2d所见,TEOS氧化物24沉积且随后通过化学机械抛光(CMP)移除,从而填充STI沟槽。
参考图13,植入P井12和N井13。
参考图14和图15,分别如沿着线2c和线2d所见,EPI层25例如按图右侧所描述的顺序生长和平坦化并且合并。如本领域一般技术人员易了解,生长EPI层只是制作工艺的这个阶段的一个实例。也可以使用电路制作中常用的其它类型的半导体材料,包括如本文所描述的侧向过度生长的其它硅基膜以及砷化镓(GaAs)、金刚石基或碳纳米管膜(例如,使用沉积)。
参考图16至图17,如分别沿着线2c和线2d所见,硬掩膜26沉积在EPI层25上方。
参考图18至图19,如分别沿着线2c至线2d所见,鳍片心轴抗蚀剂27沉积在EPI层26上方。
参考图20至图21,如分别沿着线2c至线2d所见,沉积材料28以形成心轴间隔体。
参考图22至图23,如分别沿着线2c至线2d所见,蚀刻保留将最终充当间隔体28a的物质。
参考图24至图25,如分别沿着线2c至线2d所见,移除心轴27。
参考图26至图27,如分别沿着线2c至线2d所见,蚀刻硬掩膜26,从而保留间隔体28a下方的硬掩膜区域26a。
参考图28至图29,如分别沿着线2c至线2d所见,移除间隔体28a。
参考图30至图31,如分别沿着线2c至线2d所见,鳍片通过蚀刻EPI层25而形成,从而保留硬掩膜部分26a下方的EPI层部分25a。
参考图32至图33,如分别沿着线2c至线2d所见,施加掩膜材料29以在暴露不合需要的鳍片进行移除的同时保护需要的鳍片。
参考图34至图35,如分别沿着线2c至线2d所见,移除不合需要的鳍片。
参考图36至图37,如分别沿着线2c至线2d所见,移除掩膜材料29,从而暴露需要的鳍片。
参考图38至图39,如分别沿着线2c至线2d所见,沉积高K栅极材料31。
参考图40至图41,如分别沿着线2c至线2d所见,沉积栅极电极的金属化32。如本领域一般技术人员易了解,目前为止描述的示例性制作工艺是单栅极金属化方案。如进一步所知,可根据已知技术使用更复杂的工艺,例如,使用用于P通道装置的一种金属和用于N通道装置的另一种金属制作更复杂的栅极。此外,如本领域中已知,栅极可制作有先栅极或替换栅极流。
参考图42至图43,如分别沿着线2c至线2d所见,沉积硬掩膜33。
参考图44至图45,如分别沿着线2c至线2d所见,掩膜材料34选择性地施加在金属化33上方。
参考图46至图47,如分别沿着线2c至图2d所见,蚀刻硬掩膜33,从而仅保留所选部分33a。
参考图48,移除掩膜材料34。
参考图49至图51,蚀刻栅极金属化32和高K栅极材料31,从而保留所选部分32a、31a。
参考图52至图53,如沿着线2c所见,选择性地沉积并且随后蚀刻间隔材料35,从而保留所选部分35a。
参考图54至图55,如沿着线2d所见,沉积并且蚀刻掩膜材料36,随后植入P型源极和漏极区域37和N型源极和漏极区域38。
参考图56至图57,如沿着线2d所见,施加P-EPI39p和N-EPI39n合并。
参考图58至图59,如分别沿着线2c至线2d所见,施加TEOS41。
参考图60,如沿着线2d所见,蚀刻TEOS氧化物41以允许例如通过钨沉积形成局部互连件42,随后化学和机械平坦化(CMP)可用于提供平坦表面。
参考图61至图65,大体如所示,根据替代实施方案的FinFET131包括块体源极和漏极区域以及EPI合并区域133、浅沟槽隔离134、栅极电极135、外延鳍片136、EPI合并137、P型源极和漏极区域138、间隔体139、局部互连件140、P型块体基板141、P井142、N井143、高K膜144、N型源极和漏极区域145、硅化物146、栅极硬掩膜147、TEOS氧化物148、超薄埋氧层149和外延硅鳍片150。用作鳍片的较大体积的外延材料137有利地允许使用装置通道内增大的应变。
参考图66至图70,传统的FinFET232包括源极和漏极区域以及EPI合并区域234、浅沟槽隔离235、栅极电极236、外延鳍片237、EPI合并238、间隔体239、P型源极和漏极区域240、局部互连件241、TEOS氧化物242、高K膜243、栅极硬掩膜244、硅化物247和大体如所示安置在埋氧层246上方的N型源极和漏极区域248,所述埋氧层246接着安置在P型块体基板245上方。间隔体239在源极和漏极区域扩散期间保护栅极236并且还防止应变材料太靠近栅极236。此外,较低体积的EPI合并7围绕鳍片使可能的应变效应最小化。
此外,集成电路设计系统(例如,具有数字处理器的工作站)已知,其基于存储在包括存储器但不限于CDROM、RAM、其它形式的ROM、硬盘、分布式存储器或任意其它适当计算机可读介质的计算机可读介质上的可执行指令创建集成电路。指令可由任意适当语言表示,诸如但不限于硬件描述语言(HDL)或其它适当语言。计算机可读介质含有在由集成电路设计系统执行时导致集成电路设计系统产生包括如上所述的装置或电路的集成电路的可执行指令。代码由工作站或系统(未示出)中的一个或多个处理装置执行。因而,本文所述的装置或电路还可由执行这些指令的这些集成电路系统生成为集成电路。
本领域技术人员了解本发明的结构和操作方法的多种其它修改和变更而不脱离本发明的范围和精神。虽然已结合具体优选实施方案描述本发明,但是应了解如所要求的本发明不得不当地受限于这些具体实施方案。下列权利要求旨在定义本发明的范围且旨在由此覆盖这些权利要求和其等效物的范围内的结构和方法。
Claims (18)
1.一种包括集成鳍式场效应晶体管(FinFET)的设备,其包括:
块体区域;
多个大致平行的浅沟槽隔离(STI)区域,其安置在所述块体区域的第一部分内;
多个源极和漏极区域,其每一个在所述块体区域的第二部分内安置在所述多个STI区域中的相邻区域之间;
多个鳍片区域,其安置为大致垂直于所述多个STI区域,且其每一个包括:
第一部分,其安置在所述多个STI区域的一部分上方,和
第二部分,其安置在所述多个源极和漏极区域的一部分内;和
多个栅极区域,其每一个安置在所述多个鳍片区域的相应部分和所述多个STI区域中的相应一个上方且侧向远离所述多个源极和漏极区域中的相邻区域。
2.根据权利要求1所述的设备,其中所述多个鳍片区域包括外延膜的多个部分。
3.根据权利要求1所述的设备,其中所述多个鳍片区域包括硅基膜的多个部分。
4.根据权利要求1所述的设备,其中所述多个鳍片区域包括砷化镓膜的多个部分。
5.根据权利要求1所述的设备,其中所述多个鳍片区域包括金刚石基膜的多个部分。
6.根据权利要求1所述的设备,其中所述多个鳍片区域包括碳纳米管膜的多个部分。
7.一种制作集成鳍式场效应晶体管(FinFET)的方法,其包括:
在块体区域的第一部分内蚀刻并填充多个浅沟槽隔离(STI)区域;
在所述块体区域的第二部分内植入多个源极和漏极区域,其中所述多个源极和漏极区域中的每一个安置在所述多个STI区域中的相邻区域之间;
形成大致垂直于所述多个STI区域的多个鳍片区域,其中所述多个鳍片区域中的每一个包括:
第一部分,其安置在所述多个STI区域的一部分上方,和
第二部分,其安置在所述多个源极和漏极区域的一部分内;和
在所述多个鳍片区域中的相应部分和所述多个STI区域中的相应一个上方且侧向远离所述多个源极和漏极区域中的相邻区域沉积多个栅极区域中的每一个。
8.根据权利要求7所述的方法,其中所述形成多个鳍片区域包括沉积和种植外延膜。
9.根据权利要求7所述的方法,其中所述形成多个鳍片区域包括沉积和种植硅基膜。
10.根据权利要求7所述的方法,其中所述形成多个鳍片区域包括沉积砷化镓膜。
11.根据权利要求7所述的方法,其中所述形成多个鳍片区域包括沉积金刚石基膜。
12.根据权利要求7所述的方法,其中所述形成多个鳍片区域包括沉积碳纳米管膜。
13.一种计算机可读介质,其包括在由集成电路设计系统执行时使所述集成电路设计系统产生下列项目的多个可执行指令:
集成鳍式场效应晶体管(FinFET),其包括:
块体区域;
多个大致平行的浅沟槽隔离(STI)区域,其安置在所述块体区域的第一部分内;
多个源极和漏极区域,其每一个在所述块体区域的第二部分内安置在所述多个STI区域中的相邻区域之间;
多个鳍片区域,其安置为大致垂直于所述多个STI区域,且其每一个包括:
第一部分,其安置在所述多个STI区域的一部分上方,和
第二部分,其安置在所述多个源极和漏极区域的一部分内;和
多个栅极区域,其每一个安置在所述多个鳍片区域中的相应部分和所述多个STI区域中的相应一个上方且侧向远离所述多个源极和漏极区域中的相邻区域。
14.根据权利要求13所述的设备,其中所述多个鳍片区域包括外延膜的多个部分。
15.根据权利要求13所述的设备,其中所述多个鳍片区域包括硅基膜的多个部分。
16.根据权利要求13所述的设备,其中所述多个鳍片区域包括砷化镓膜的多个部分。
17.根据权利要求13所述的设备,其中所述多个鳍片区域包括金刚石基膜的多个部分。
18.根据权利要求13所述的设备,其中所述多个鳍片区域包括碳纳米管膜的多个部分。
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PCT/US2011/046230 WO2012018789A1 (en) | 2010-08-02 | 2011-08-02 | Integrated fin-based field effect transistor (finfet) and method of fabrication of same |
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