CN103050458A - 具有图案化表面、图案化侧壁和局部隔离的硅通孔结构 - Google Patents

具有图案化表面、图案化侧壁和局部隔离的硅通孔结构 Download PDF

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CN103050458A
CN103050458A CN2012104811976A CN201210481197A CN103050458A CN 103050458 A CN103050458 A CN 103050458A CN 2012104811976 A CN2012104811976 A CN 2012104811976A CN 201210481197 A CN201210481197 A CN 201210481197A CN 103050458 A CN103050458 A CN 103050458A
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conductive layer
micro
deposited
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CN103050458B (zh
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罗珮璁
谢斌
杨丹
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

本发明公开了一种为具有图案化表面、图案化侧壁和局部隔离的硅通孔结构以及制作该结构的方法。在一个实施例中，TSV结构包括一个从所述第一侧表面延伸到所述第二侧表面穿透芯片的通孔，其在第一侧表面有第一端，在第二侧表面有第二端。一局部隔离层沉积在通孔侧壁上和第一端周围的部分第一侧表面上。TSV结构还包括多个密集的微结构，其被安排成非随机图案，并被制作在所述第一端周围的的至少部分第一侧表面上，所述局部隔离层覆盖于所述微结构上，用于提高局部隔离层到芯片的粘附力。大部分微结构的深度至少为1μm。

Description

具有图案化表面、图案化侧壁和局部隔离的硅通孔结构
【技术领域】
本发明涉及硅芯片的硅通孔结构，特别涉及使用图案化表面和图案化侧壁来提升局部隔离层沉积于硅芯片主体的粘附力，更涉及使用局部隔离来提高局部隔离层的可靠性。
【背景技术】
因为功能性增加的竞争需求以及越来越小的电子产品的竞争需求，迫使器件生产商要发明出更加复杂的封装设计，所以对于半导体器件来说，封装需求变得越来越严格。特别是，器件小型化的需求不断增加，已经使得封装生产商进行多芯片的垂直集成（vertical integration）以减小整个封装的尺寸，使得最终的电子产品能够更小。例如“系统级封装（system-in-package）”设计已经用于CMOS图像传感器以及相关的数字信号处理器和存储器芯片。为了电连接在这些垂直集成封装里的芯片，首先在硅芯片上形成硅通孔（TSV）并把这些TSV填充满导体，导体连接到每个芯片下面的焊球凸点（solder bump）上。
因为硅芯片主体是半导电的，在填充导体入TSV之前，需要隔离TSV。类似地，TSV周围的硅表面以及其上的导体也需要隔离。为了隔离TSV和周围的硅表面，有一个方法是通过使用大约300°C的高温过程沉积一层氧化硅。但是，该高温过程会影响已经存在在硅芯片上的集成电路，降低电路的可靠性，有时还会损坏电路。而且，高温过程成本非常贵。另外一个不涉及高温的方法是沉积一层隔离层，通常是聚合物层，是通过将液体聚合物施用在TSV和周围硅表面上。
美国专利8,049,327披露了一种方法，在TSV侧壁采用齿状表面（scalloped surface）来减少脱层（delamination）的发生。使用齿状表面的结果是，侧壁上有许多相互连接的同心环。因此侧壁的表面面积增加了，所以增强了聚合物层到侧壁的粘附力。但是，使用齿状表面的布置并不能直接适用于TSV周围的硅表面是平坦的。
一种增加聚合物层到侧壁粘附力的方法是基于二维毯式蚀刻的表面粗糙化，如对硅表面进行反应离子蚀刻（RIE）、深反应离子蚀刻（DRIE）和湿蚀刻。由于很难控制硅芯片粗糙化的均匀度，对于某些系统级封装，聚合物层的粘附力可靠性很难保证。
因此需要有改良的方法，能提高聚合物层或隔离层到硅表面的粘附力。
【发明内容】
本发明披露了一种为硅芯片的第一侧和第二侧之间提供电通路的硅通孔（TSV）结构。第一侧有第一侧表面，第二侧有第二侧表面。TSV结构包括一个从所述第一侧表面延伸到所述第二侧表面穿透芯片的通孔，其在第一侧表面有第一端，在第二侧表面有第二端。一局部隔离层沉积在通孔侧壁上和第一端周围的部分第一侧表面上。TSV结构还包括多个密集的微结构，其被安排成非随机图案，并被制作在所述第一端周围的至少部分第一侧表面上，所述局部隔离层覆盖于所述微结构上，用于提高局部隔离层沉积于芯片的粘附力。大部分微结构的深度至少为1μm。
优选地，大部分微结构的宽度是在2μm和4μm之间。优选地，局部隔离层是由聚合物材料构成。通孔可以是锥形的或垂直的。通孔侧壁可以包括多个台阶或齿形，用于增加侧壁和沉积在其上的局部隔离层之间的粘附力，其中大部分台阶和大部分齿形的深度大于1μm。
优选地，有一导电层沉积在局部隔离层上，完全覆盖但不接触通孔侧壁和被局部隔离层覆盖的那部分第一侧表面，其中沉积在第一侧表面上的局部隔离层的外边界和第一侧表面上的导电层的外边界对齐。优选地，导电层是由金属构成。
优选地，TSV结构还包括一保护层，其沉积在导电层上，以覆盖导电层和局部隔离层。保护层可以由聚合物材料构成。
优选地，TSV结构还包括一软保护材料，其沉积在第一侧表面上并贴附于沉积在第一侧表面上的局部隔离层的外边界和第一侧表面上的导电层的外边界，以保护局部隔离层和导电层的边缘免受暴露。
可选地，沉积在第一侧表面上的局部隔离层的外边界与围住多个微结构的最小外边界对齐。
通孔的第二端可以被位于第二侧表面上的一金属焊盘覆盖，使得导电层与金属焊盘连接，从而形成第一侧和第二侧之间的电通路。
本发明还披露了一种制作硅通孔结构的方法，其中硅通孔为硅芯片的第一侧和第二侧之间提供电通路，其中第一侧有第一侧表面，第二侧有第二侧表面，硅芯片有一金属焊盘连接到第二侧表面。在该方法中，在第一侧表面上制作多个密集的微结构，其中微结构被安排成非随机图案，其中大部分微结构的深度至少为1μm。然后形成一通孔从第一侧表面穿过该芯片延伸到第二侧表面，使得金属焊盘通过该通孔暴露于第一侧。然后，沉积第一材料（最好是聚合物材料）到第一侧上，但是使得第一材料并不覆盖暴露于第一侧的大部分金属焊盘。接着沉积金属到第一侧上，然后选择性地去除部分金属，从而在暴露于第一侧的大部分金属焊盘上、在通孔侧壁上、在通孔周围的部分第一侧表面上形成一导电层。然后去除位于第一侧表面上的没有被导电层覆盖的第一材料，从而形成一局部隔离层，以隔离导电层和芯片主体。然后，沉积第二材料（最好是聚合物材料）到第一侧上，再选择性地去除第二材料，形成一保护层。接着再沉积一软保护材料（最好是聚合物材料）到第一侧上，然后选择性地去除部分软保护材料。优选地，该方法还包括执行焊料凸点的沉积和凸点下金属化。
优选地，形成通孔的步骤包括：在通孔侧壁上形成多个台阶或齿形，大部分台阶或大部分齿形的深度都大于1μm。
去除位于第一侧表面上的没有被导电层覆盖的第一材料，可以通过蚀刻第一材料来完成，蚀刻时采用导电层作为掩膜，以保护被导电层覆盖的第一材料，不被蚀刻。
沉积第一材料到第一侧上，但是使得第一材料并不覆盖暴露于第一侧的大部分金属焊盘，该步骤可以这样执行：非选择性地沉积第一材料到第一侧上，以覆盖第一侧表面、通孔侧壁、和暴露于第一侧的金属焊盘；然后选择性地去除已经沉积在金属焊盘上的大部分第一材料，从而形成一接触开口在金属焊盘上，以暴露金属焊盘于第一侧。
另外，本发明披露了一种增加局部隔离层到硅芯片表面粘附力的方法分。该方法包括：在沉积所述局部隔离层到所述表面之前，在所述局部隔离层将要沉积其上的至少部分表面上制作多个密集的微结构，其中所述微结构被安排成非随机图案，其中大部分微结构的深度至少为1μm。局部隔离层是由聚合物材料构成。
【附图说明】
图1显示在硅表面上使用微结构来增加与隔离层接触的表面面积的一个例子。
图2显示基于（A）立方体表面纹理设计和（B）其他表面纹理设计的微结构例子。
图3是本发明一个实施例的TSV结构。
图4显示通过在TSV侧壁上使用台阶或齿形来增加表面面积的例子。
图5是本发明实施例的不同TSV结构。
图6是本发明实施例的制作TSV的过程。
【具体实施方式】
在此说明书及所附权利要求中使用的术语“通孔”是广义的，意指电材料层上的任何开孔，电材料层使得层与层之间有导电连接。在描述本发明中，各种其他类似得术语如“沟槽”或“通道”都被术语“通孔”涵盖。
到隔离层（如聚合物层）的粘附力可以通过增加该隔离层和硅表面之间的接触面积而增加。根据本发明，通过在硅表面上制作微结构（microstructure）而增加接触面积。图1显示通过微结构而增加接触面积的一个例子。在图1的例子中，原始平坦表面110由四个正方形组成，每个是3μm × 3μm。该平坦表面110的接触面积有4个面积单元。如果在这四个正方形的对角线位置上制作两个微结构，每个微结构是3μm × 3μm × 3μm的立方体，那么就会产生一个表面120，其接触面积有12个面积单元。
在硅表面上形成图案化的微结构纹理，如果注意以下几个因素，则能最大化接触面积。第一，微结构是一个具有深度的三维结构。发明人已经确认，如果深度大于1μm，那么接触面积就能大大增加，使得隔离层到硅表面的粘附力大大提高。第二，微结构可以安排得尽量密集以至于最大化接触面积。例如，通过制作相互类似的微结构基底（即微结构和硅表面接触的底面），可以使得微结构尽量密集。另一个使微结构尽量密集的例子是，相邻的微结构可以安排得相互接触。第三，微结构可以布置成非随机图案。非随机图案的一个例子是周期性结构的图案，如一个棋盘形图案。
图2显示本发明实施例的微结构及其布置（即合成图案）的例子。在图2A中，显示了具有立方体表面纹理的微结构图案的例子。多个微结构的俯视图，如230a，形成一个图案的平面视图。根据该俯视图，有两种实现可能。例如，从俯视图230a，可以有一个实现230b及其反向实现230c。在图2B中，显示了具有其他表面纹理的微结构图案的例子。
另外，发明人已经确认，每个微结构基底的宽度最好在2μm和4μm之间。如果隔离层是由聚合物制成的，那么这个范围内的数值是最好的。在此说明书及所附权利要求中，任意形状的二维轮廓的“宽度”被定义为，该轮廓边界的两条相对切线之间的最小距离。
根据本发明的典型实施例，图3显示了一个TSV结构。该TSV结构是为硅芯片350而制作。硅芯片350有第一侧和第二侧，第二侧与第一侧相对。第一侧有在硅芯片350主体上的第一侧表面351a。第二侧有第二侧表面351b。TSV结构提供第一侧表面351a和第二侧表面351b之间的电通路。为方便描述TSV结构，不失一般性，我们考虑这样一种情况，硅芯片350的第二侧包含集成电路的有源器件（active components）。相应地，第一侧是硅芯片350的背侧。在第二侧表面351b上，有一钝化层360。由于硅芯片350的脆弱，硅芯片350可能贴附在一个基板375上，基板375对该集成电路提供额外的机械支撑和保护。可以使用一层环氧树脂370将硅芯片350和基板375粘在一起。
TSV结构包括一个通孔310，其从第一侧表面351a延伸到第二侧表面351b而穿透芯片350。通孔310在第一侧表面351a有第一端311a，在第二侧表面351b有第二端311b。一层局部隔离层330（其是电绝缘层）沉积在通孔310的侧壁312上以及沉积在第一端311a周围的一部分第一侧表面351a上。优选地，局部隔离层330由聚合物材料组成。TSV结构还包括多个密集的微结构320，它们被排列成非随机图案，并被制作在所述第一端周围的至少那部分第一侧表面351a上，局部隔离层330覆盖于所述微结构上，用于提升局部隔离层330沉积于芯片350上的粘附力，其中大部分微结构320的深度都至少为1μm。优选地，大部分微结构320的宽度在2μm和4μm之间。
在图3中，通孔310是锥形的，其中第一端311a的面积和第二端311b的面积不同。在领一个实施例中（未在图3中显示），通孔310是垂直的，有着垂直的侧壁312。
为了增加局部隔离层330到侧壁312的粘附力，侧壁330可以包括多个台阶或齿形（scallop）。特别地，大部分台阶或大部分齿形的深度都大于1μm，以提供足够的粘附力给局部隔离层330。为了显示这些台阶或齿形提供的增大了的接触面积，图4描述了一个例子，其中在侧壁上没有任何台阶的锥形通孔410的接触面积是6350μm2，而另一个有四个台阶的通孔420的接触面积则增加到8200μm2。
为了在第一侧表面351a和第二侧表面351b之间提供电通路，在局部隔离层330上沉积一层导电层335，其通常是由金属制成。导电层335覆盖但是没有接触到侧壁312以及由局部隔离层330覆盖的那部分第一侧表面351a。优选地，沉积在第一侧表面351a上的局部隔离层330的外边界和第一侧表面351a上的导电层335的外边界要对齐。因此局部隔离层330和导电层335重叠。发明人已经发现，局部隔离层330和导电层335对齐的这种布置，和局部隔离层330延伸到导电层335之外的这种情况相比，前者的局部隔离层330要接受较少的机械应力。接受较少机械应力的好处是局部隔离层330的可靠性可以得到提高。注意到，沉积在第一侧表面351a上的局部隔离层330的内边界就是第一端311a的边界。
优选地，TSV结构还包括一层保护层340，其沉积在导电层335上，用于覆盖导电层335和局部隔离层330，因此对这两层335、330提供保护。优选地，保护层340由聚合物材料制成。
TSV结构还包括一软保护材料345，其沉积在第一侧表面351a上，并附着于第一侧表面351a上的局部隔离层330和导电层335的外边界，以保护局部隔离层330和导电层335的边缘，不受暴露。
TSV结构是用于提供第一侧表面351a和第二侧表面351b之间的电通路。因为考虑到硅芯片350的第二侧包括集成电路的有源器件，集成电路通过导电层335被电连接到第一侧表面351a。导电层335可以连接到第二端311b上的金属焊盘365。金属焊盘365位于与第二侧表面351b粘贴的钝化层360上，并与集成电路电连接。
从以上的披露中知道，局部隔离层沉积于硅芯片表面的粘附力可以通过以下结构和过程而得以提高：在沉积局部钝化层到表面之前，先在至少一部分将要沉积该局部钝化层的表面上制作多个密集的微结构，其中微结构被安排形成非随机图案，且大部分微结构的深度至少为1μm。
在其他实施例中，图5显示了各种TSV结构。锥形通孔且侧壁上有台阶或齿形的，如TSV结构510和560。垂直通孔且侧壁上没有台阶和齿形的，如TSV结构540和550。对于每个TSV结构510、530、550和560，多个微结构制作在第一侧表面上并与局部隔离层对齐。对于每个TSV结构520和540，多个微结构制作在第一侧表面上并超出局部隔离层的外边界。对于TSV结构560，使用了平坦的保护层。
根据本发明的实施例，图6显示了一个制作TSV结构的过程，TSV结构用于提供硅芯片第一侧和第二侧之间的电通路，第一侧有第一侧表面，第二侧有第二侧表面，芯片有一金属焊盘贴附在第二侧表面上。该过程包括步骤621～630，最终得到TSV结构600。
在第一步骤621，在第一侧表面上制作多个密集的微结构，其中微结构被安排成非随机图案，并且这多个微结构的深度至少为1μm。可以使用光刻和干蚀刻来制作这些微结构。
在第二步骤622，在第一侧表面和第二侧表面之间形成一个通孔穿过该芯片，使得金属焊盘通过该通孔而暴露于第一侧。例如，可以使用光刻和干蚀刻来制作该通孔。另外，可以在该通孔的侧壁上制作多个台阶或齿形，使得大部分台阶或大部分齿形的深度至少为1μm。
在步骤622形成通孔后，沉积第一材料（最好是聚合物）在第一侧上，第一材料并不覆盖暴露于第一侧的大部分金属焊盘。该沉积步骤可以由第三步骤623和第四步骤624执行。在步骤623，非选择性地沉积第一材料到第一侧，完全覆盖第一侧表面、通孔侧壁、和暴露于第一侧的金属焊盘。可以使用CVD来执行该非选择性沉积。在步骤624，选择性地去除已经沉积在金属焊盘上的大部分第一材料，从而在金属焊盘上形成一接触开口，暴露于第一侧。
在第五步骤625，沉积金属在第一侧上。在第六步骤626，选择性地去除已经沉积的部分金属，从而形成一层导电层在暴露于第一侧的大部分金属焊盘上、在通孔侧壁上、在通孔周围的部分第一侧表面上。
在第七步骤627，去除在第一侧表面上的没有被导电层覆盖的那部分第一材料，从而形成一层局部隔离层，以隔离导电层和芯片主体。特别地，可以通过蚀刻第一材料而完成该去除过程，蚀刻时使用导电层作为掩膜（mask）来保护被该导电层覆盖的第一材料不被蚀刻。好处是不需要额外的掩膜。
在第八步骤628，沉积第二材料（最好是聚合物）在芯片的第一侧上。在第九步骤629，选择性地去除沉积在TSV结构周围之外的第二材料，从而形成一层保护层。第九步骤629还包括：沉积一软保护材料（最好是聚合物）在芯片的第一侧上，然后选择性地去除部分软保护材料。
在第十步骤630，执行焊料凸点的沉积和凸点下金属化。
本发明还可以以其他具体形式但不脱离其精神或本质特征来实施。因此本实施例在所有方面都应考虑为描述性的而非限制性的。本发明的范围是由所附权利要求限定，而不是由以上描述限定，因此在所附权利要求或其等同物的意义和范围内的所有变化都在其覆盖范围内。

Claims (20)

1.一种为硅芯片的第一侧和第二侧之间提供电通路的硅通孔结构，其中所述第一侧有第一侧表面，所述第二侧有第二侧表面，所述通孔结构包括：
一通孔，其从所述第一侧表面延伸到所述第二侧表面穿透所述芯片，其在所述第一侧表面有第一端，在所述第二侧表面有第二端；
一局部隔离层，其被沉积在所述通孔的侧壁上和在所述第一端周围的至少部分第一侧表面上；
多个密集的微结构，其被安排成非随机图案，并被制作在所述第一端周围的至少部分第一侧表面上，所述局部隔离层覆盖于所述微结构上，用于提高所述局部隔离层沉积于所述芯片的粘附力，其中大部分微结构的深度至少为1μm。
2.根据权利要求1所述的通孔结构，其中大部分微结构的宽度在2μm和4μm之间。
3. 根据权利要求1所述的通孔结构，其中所述局部隔离层是由聚合物材料构成。
4. 根据权利要求1所述的通孔结构，其中所述通孔是锥形的或垂直的。
5. 根据权利要求1所述的通孔结构，其中所述侧壁包括多个台阶或齿形，其用于提高所述侧壁和沉积在其上的所述局部隔离层之间的粘附力，其中大部分台阶或大部分齿形的深度至少为1μm。
6. 根据权利要求1所述的通孔结构，还包括一导电层，其被沉积在所述局部隔离层上，以覆盖但不接触所述通孔侧壁和由所述局部隔离层覆盖的部分第一侧表面，其中沉积在所述第一侧表面上的所述局部隔离层的外边界和所述第一侧表面上的所述导电层的外边界对齐。
7. 根据权利要求6所述的通孔结构，其中所述导电层由金属构成。
8. 根据权利要求6所述的通孔结构，还包括一保护层，其沉积在所述导电层上，以覆盖所述导电层和所述局部隔离层。
9. 根据权利要求8所述的通孔结构，其中所述保护层是由聚合物材料构成。
10. 根据权利要求8所述的通孔结构，还包括一软保护材料，其被沉积在所述第一侧表面上，并贴附于沉积在所述第一侧表面上的所述局部隔离层的外边界和所述第一侧表面上的所述导电层的外边界，用以保护所述局部隔离层和所述导电层的边缘，免受暴露。
11. 根据权利要求6所述的通孔结构，其中沉积在所述第一侧表面上的所述局部隔离层的外边界与围住多个微结构的最小外边界对齐。
12. 根据权利要求6所述的通孔结构，其中所述第二端被一个位于所述第二侧表面上的金属焊盘覆盖，使得所述导电层连接所述金属焊盘，从而形成所述第一侧和所述第二侧之间的电通路。
13. 一种形成硅通孔结构的方法，其中所述硅通孔结构为硅芯片的第一侧和第二侧之间提供电通路，所述第一侧有第一侧表面，所述第二侧有第二侧表面，所述芯片有一金属焊盘连接到所述第二侧表面，该方法包括：
在所述第一侧表面制作多个密集的微结构，其中所述微结构被安排成非随机图案，其中大部分所述微结构的深度至少为1μm；
形成一通孔，从所述第一侧表面延伸到所述第二侧表面以穿透所述芯片；
沉积第一材料到所述第一侧上，所述第一材料并不覆盖暴露于所述第一侧的至少大部分金属焊盘；
沉积金属到所述第一侧上，然后选择性地去除部分金属，从而在暴露于所述第一侧的至少大部分金属焊盘上、在所属通孔侧壁上以及在所述通孔周围的部分第一侧表面上形成一导电层；
去除在所述第一侧表面上的没有被所述导电层覆盖的所述第一材料，从而形成一局部隔离层，用以隔离所述导电层和所述芯片主体；
沉积第二材料到所述第一侧上，然后选择性地去除部分第二材料，从而形成一保护层；
沉积一软保护材料到所述第一侧上，然后选择性地去除部分软保护材料。
14. 根据权利要求13所述的方法，还包括：执行焊料凸点的沉积和凸点下金属化。
15. 根据权利要求13所述的方法，其中形成通孔步骤包括：在所述通孔侧壁上形成多个台阶或齿形，大部分台阶或大部分齿形的深度至少为1μm。
16. 根据权利要求13所述的方法，其中去除在所述第一侧表面上的没有被所述导电层覆盖的所述第一材料，是通过蚀刻所述第一材料来完成的，在蚀刻时使用所述导电层作为掩膜，以保护被所述导电层覆盖的第一材料，免受蚀刻。
17. 根据权利要求13所述的方法，其中沉积第一材料到所述第一侧上，所述第一材料并不覆盖暴露于所述第一侧的至少大部分金属焊盘的步骤包括：
非选择性地沉积所述第一材料到所述第一侧上，从而覆盖所述第一侧表面、所述通孔侧壁、和所述暴露于所述第一侧的金属焊盘；
选择性地去除已经沉积在所述金属焊盘上的所述第一材料，从而形成一接触开口在所述金属焊盘上，将至少大部分金属焊盘暴露于所述第一侧。
18. 根据权利要求13所述的方法，其中任一所述第一材料、第二材料和所述软保护材料都是由聚合物材料构成。
19. 一种用于提高局部隔离层到硅芯片表面的粘附力的方法，包括：
在沉积所述局部隔离层到所述表面之前，在所述局部隔离层将要沉积其上的至少部分表面上制作多个密集的微结构，其中所述微结构被安排成非随机图案，其中大部分微结构的深度至少为1μm。
20. 根据权利要求19所述的方法，其中所述局部隔离层是由聚合物构成。
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