CN103035506A - Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove - Google Patents

Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove Download PDF

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CN103035506A
CN103035506A CN201210281659XA CN201210281659A CN103035506A CN 103035506 A CN103035506 A CN 103035506A CN 201210281659X A CN201210281659X A CN 201210281659XA CN 201210281659 A CN201210281659 A CN 201210281659A CN 103035506 A CN103035506 A CN 103035506A
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silicon
etching
deep groove
film
monocrystalline silicon
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CN103035506B (en
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吴智勇
肖胜安
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses an etching method for a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove. The etching method comprises steps of 1, etching a photoetching registration mark region; 2, growing a silicon oxide - silicon nitride layer; 3, etching monocrystalline silicon to form a shallow groove; 4, depositing silicon oxide; 5, using a hard mask dry method etching process with high selection ratio between the silicon oxide and the silicon nitride to form a deep groove image in the monocrystalline silicon shallow groove; and 6, using a dry method etching process with high selection ratio between the monocrystalline silicon and the silicon oxide and between the monocrystalline silicon and the silicon nitride to form a deep groove in a thick field oxygen region. The etching method can form ONO lamination layers on an inclined face region at the edge of a silicon wafer and the photoetching registration mark region, uses the process with high selection ratio between an oxide film and a nitride film in a deep groove hard mask etching process, uses the process with high selection ratio between monocrystalline silicon and a medium film in deep groove etching, and effectively overcomes the defect that silicon spines can be generated on the inclined face region at the edge of the silicon wafer and the photoetching registration mark region after etching with a deep groove dry method.

Description

The lithographic method of RFLDMOS spacer medium layer depth groove
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of lithographic method of RFLDMOS spacer medium layer depth groove.
Background technology
In RFLDMOS(radio frequency horizontal proliferation type burning field effect transistor) in the spacer medium layer process, thick oxygen technique combines monocrystalline silicon and returns quarter and deep plough groove etched technique, used this film layer structure of oxide-film-nitride film-oxide-film, cause in the hard mask dry etching of deep trench process, in place, silicon chip edge inclined-plane and photoetching alignment mark, there is deielectric-coating residual, thereby behind dark silicon trench dry etching, a large amount of silicon tip thorns appears in silicon chip edge inclined-plane and photoetching alignment mark, such as Fig. 1, shown in 2, through after the follow-up wet-cleaned, will form a large amount of silicon grain defectives on the surfacial pattern of silicon chip, these defectives cause technique to produce in a large number.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of lithographic method of RFLDMOS spacer medium layer depth groove, it can avoid deep plough groove etched after, silicon tip thorn appears in silicon chip edge inclined-plane and photoetching alignment mark.
For solving the problems of the technologies described above, the lithographic method of RFLDMOS spacer medium layer depth groove of the present invention may further comprise the steps:
1) in the scribe line of silicon chip, etches zero layer photoetching alignment mark regions;
2) grow successively silicon dioxide film and silicon nitride film;
3) monocrystalline silicon returns quarter, forms the monocrystalline silicon shallow trench on the deep trench zone in thick oxygen district;
4) the hard mask of deposit silicon dioxide;
5) with the hard mask dry etch process of silicon dioxide to the silicon nitride high selectivity, in the monocrystalline silicon shallow trench, form the deep trench figure;
6) with the dry etch process of monocrystalline silicon to silicon dioxide and silicon nitride high selectivity, form deep trench in thick oxygen district.
The present invention is by forming oxide-film-nitride film-oxide-film lamination in silicon chip edge beveled region and photoetching alignment mark, and in the hard mask etching process of deep trench, use oxide-film to the technique of nitride film high selectivity, in the deep trench dry etching, use monocrystalline silicon to the technique of the deielectric-coating high selectivities such as oxide-film, nitride film, avoided effectively that the defective of silicon tip thorn appears in silicon chip edge beveled region and photoetching alignment mark zone in the deep trench dry etching process, thereby helped to realize RFLDMOS spacer medium layer process volume production.
Description of drawings
Fig. 1 is the silicon tip thorn of silicon chip edge beveled region.
Fig. 2 is the silicon tip thorn in the photoetching alignment mark.
Fig. 3 is the etch process flow schematic diagram of the RFLDMOS spacer medium layer depth groove of the embodiment of the invention.
Description of reference numerals is as follows among the figure:
1:P type silicon substrate
2:P type extension
3,6: silicon dioxide film
4: silicon nitride film
5: the monocrystalline silicon shallow trench
7: photoresist
8: deep trench
9: the photoetching alignment mark district
10: thick oxygen district
11: the silicon chip edge beveled region
Embodiment
Understand for technology contents of the present invention, characteristics and effect being had more specifically, existing in conjunction with illustrated execution mode, details are as follows:
The lithographic method of the RFLDMOS spacer medium layer depth groove of present embodiment comprises the steps:
Step 1 by photoetching, etching and the technique such as remove photoresist, forms zero layer photoetching alignment mark regions 9, shown in Fig. 3 (a) in the scribe line of silicon chip.The degree of depth in this photoetching alignment mark district 9 is
Figure BDA00001991148300021
Step 2, successively deposit silicon dioxide film 3, silicon nitride film 4 form the lamination of oxide-film-nitride film.
Silicon dioxide film 3 is as the resilient coating of thermal expansion, and thickness is
Figure BDA00001991148300031
Silicon nitride film 4 simultaneously also will be as the barrier layer of follow-up hard mask etching and deep plough groove etched mask layer not only as the mask layer of an oxygen, and this layer silicon nitride film 4 can lose in subsequent technique gradually, so thickness is preferably in
Figure BDA00001991148300032
More than.
Step 3 at thick oxygen district of silicon chip edge beveled region 11, photoetching alignment mark district 9 and part 10 coating photoresists, is returned quarter by photoetching and monocrystalline silicon, forms monocrystalline silicon shallow trench 5 on deep trench 8 zones in thick oxygen district 10, shown in Fig. 3 (b).
Monocrystalline silicon shallow trench 5 is used for preventing that the cavity of subsequent fields oxygen from coming out at chemical mechanical milling tech, affects subsequent technique.The degree of depth of this monocrystalline silicon shallow trench 5 is preferably in
Figure BDA00001991148300033
Deeply can cause technology difficulty to photoetching and thermal oxidation technology again.
Step 4, deposit silicon dioxide film 6 is as the hard mask of subsequent deep trench dry etching, shown in Fig. 3 (c).
The thickness of silicon dioxide film 6 is as long as enough stop deep plough groove etchedly, and in the present embodiment, thickness is preferably in
Figure BDA00001991148300034
More than.After finishing the deposit of this step, form oxide-film-nitride film-oxide-film three-decker in silicon chip edge beveled region 11 and photoetching alignment mark district 9.
Step 5 by photoetching and the silicon oxide film hard mask dry etch process to the silicon nitride film high selectivity, forms the deep trench figure, shown in Fig. 3 (d) in monocrystalline silicon shallow trench 5.Etching condition is: the medium air pressure of 30~60 person of outstanding talent's holders, and 300~500 watts of power, etching gas is mainly with C 4F 6Or C 4F 8Be main, can assist and mix Ar, O 2Deng gas, with suitable increase etch rate.
This etching technics can reach silicon oxide film to the utmost point high selectivity (generally can accomplish 25:1 or higher) of silicon nitride film, at device region deep trench 8 tops not can owing to hard mask dry etching cross carve occur uneven, nitride film in silicon chip edge beveled region 11 and photoetching alignment mark district 9 does not almost have loss, and subsequent deep trench is groove etched to provide enough barrier layers thereby give.
Step 6 with the etching technics of monocrystalline silicon to deielectric-coating (silicon oxide film and silicon nitride film) high selectivity, forms the dark deep trench 8 of 3~4 μ m in thick oxygen district 10, shown in Fig. 3 (e).Etching condition is: the medium air pressure of 30~50 person of outstanding talent's holders, and 900~1500 watts of upper electrode power, 50~90 watts of lower electrode power, etching gas is with SF 6And O 2Be main, suitably add CHF 3Increase is to the etching selection ratio of deielectric-coating (generally at 20:1 between the 25:1).
This deep trench 8 forms thick oxygen layer after the subsequent thermal oxidation.Owing to the hard mask of enough silica is arranged, so the silicon nitride film of bottom can fully stop subsequent chemistry mechanical lapping.And in silicon chip edge beveled region 11 and photoetching alignment mark district 9 since the hard mask etching technique of step 5 leave after finishing enough nitride films (
Figure BDA00001991148300035
More than), therefore, can stop the etching of deep trench, after deep plough groove etched finishing, can not produce the silicon tip thorn.

Claims (10)

1.RFLDMOS the lithographic method of spacer medium layer depth groove is characterized in that, may further comprise the steps:
1) in the scribe line of silicon chip, etches zero layer photoetching alignment mark regions;
2) grow successively silicon dioxide film and silicon nitride film;
3) monocrystalline silicon returns quarter, forms the monocrystalline silicon shallow trench on the deep trench zone in thick oxygen district;
4) the hard mask of deposit silicon dioxide;
5) with the hard mask dry etch process of silicon dioxide to the silicon nitride high selectivity, in the monocrystalline silicon shallow trench, form the deep trench figure;
6) with the dry etch process of monocrystalline silicon to silicon dioxide and silicon nitride high selectivity, form deep trench in thick oxygen district.
2. method according to claim 1 is characterized in that, the degree of depth in described photoetching alignment mark district is
Figure FDA00001991148200011
3. method according to claim 1 is characterized in that step 2), the thickness of described silicon dioxide film is
Figure FDA00001991148200012
The thickness of silicon nitride film is
Figure FDA00001991148200014
More than.
4. method according to claim 1 is characterized in that, step 3), and the degree of depth of described monocrystalline silicon shallow trench is
Figure FDA00001991148200015
5. method according to claim 1 is characterized in that, step 4), and the thickness of described silicon dioxide film is
Figure FDA00001991148200017
More than.
6. method according to claim 1 is characterized in that, step 5), and etching condition is: air pressure 30~60 millitorrs, 300~500 watts of power, etching gas comprises C 4F 6Or C 4F 8
7. method according to claim 6 is characterized in that, step 5) contains assist gas Ar or O in the etching gas 2
8. according to claim 1 or 7 described methods, it is characterized in that, step 5), silicon dioxide to the selection of silicon nitride than for more than the 25:1.
9. method according to claim 1 is characterized in that, step 6), and etching condition is: air pressure 30~50 person of outstanding talent's holders, 900~1500 watts of upper electrode power, 50~90 watts of lower electrode power, etching gas comprises SF 6And O 2
10. according to claim 1 or 9 described methods, it is characterized in that, step 6), monocrystalline silicon is 20:1~25:1 to the etching selection ratio of silicon dioxide and silicon nitride.
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Cited By (5)

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CN103935953A (en) * 2014-04-25 2014-07-23 上海先进半导体制造股份有限公司 Composite cavity and forming method thereof
CN104281020A (en) * 2013-07-08 2015-01-14 无锡华润上华科技有限公司 Method for improving photoetching alignment capability
CN105700076A (en) * 2016-01-19 2016-06-22 中国电子科技集团公司第二十三研究所 Method for etching optical waveguide shielding layer
CN106128952A (en) * 2016-07-27 2016-11-16 上海华虹宏力半导体制造有限公司 Improve method and the MOS transistor of defects of wafer edge
CN110176501A (en) * 2019-05-30 2019-08-27 深圳市美浦森半导体有限公司 A kind of preparation method of MPS structure process silicon carbide diode

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CN102468128A (en) * 2010-11-09 2012-05-23 上海华虹Nec电子有限公司 Method for forming deep-trench polysilicon
CN102522363A (en) * 2011-12-22 2012-06-27 上海华虹Nec电子有限公司 Production method of deep groove isolation structure
CN102610490A (en) * 2011-01-19 2012-07-25 上海华虹Nec电子有限公司 Method for manufacturing trench of super junction

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US20020081809A1 (en) * 2000-12-22 2002-06-27 Angelo Pinto Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
CN1527374A (en) * 2003-02-18 2004-09-08 Ħ��������˾ Method for producing semi-conductor assembly
CN101996934A (en) * 2009-08-20 2011-03-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN102468128A (en) * 2010-11-09 2012-05-23 上海华虹Nec电子有限公司 Method for forming deep-trench polysilicon
CN102610490A (en) * 2011-01-19 2012-07-25 上海华虹Nec电子有限公司 Method for manufacturing trench of super junction
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CN102522363A (en) * 2011-12-22 2012-06-27 上海华虹Nec电子有限公司 Production method of deep groove isolation structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104281020A (en) * 2013-07-08 2015-01-14 无锡华润上华科技有限公司 Method for improving photoetching alignment capability
CN103935953A (en) * 2014-04-25 2014-07-23 上海先进半导体制造股份有限公司 Composite cavity and forming method thereof
CN103935953B (en) * 2014-04-25 2016-04-13 上海先进半导体制造股份有限公司 Composite cavity and forming method thereof
CN105700076A (en) * 2016-01-19 2016-06-22 中国电子科技集团公司第二十三研究所 Method for etching optical waveguide shielding layer
CN105700076B (en) * 2016-01-19 2019-01-25 中国电子科技集团公司第二十三研究所 A kind of lithographic method of optical waveguide shielded layer
CN106128952A (en) * 2016-07-27 2016-11-16 上海华虹宏力半导体制造有限公司 Improve method and the MOS transistor of defects of wafer edge
CN110176501A (en) * 2019-05-30 2019-08-27 深圳市美浦森半导体有限公司 A kind of preparation method of MPS structure process silicon carbide diode

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