JP2006032801A - Semiconductor device manufacturing process - Google Patents

Semiconductor device manufacturing process Download PDF

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JP2006032801A
JP2006032801A JP2004212172A JP2004212172A JP2006032801A JP 2006032801 A JP2006032801 A JP 2006032801A JP 2004212172 A JP2004212172 A JP 2004212172A JP 2004212172 A JP2004212172 A JP 2004212172A JP 2006032801 A JP2006032801 A JP 2006032801A
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film
etching
silicon nitride
nitride film
chf
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Hideyuki Shoji
秀行 庄司
Mitsuyoshi Seki
三好 関
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NEC Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a new process with a mask selectivity that ensures a vertical shape and suppresses a dimensional difference in a condensation/rarefaction area during SiN film etching. <P>SOLUTION: This semiconductor manufacturing process forms in order a silicon oxide film and a silicon nitride film on a silicon substrate, and then forms an anti-reflection coating for pattern generation by lithography. Furthermore, it etches the above anti-reflection coating by CHF<SB>3</SB>, CF<SB>4</SB>and O<SB>2</SB>, the above silicon nitride film by CH<SB>3</SB>F, CF<SB>4</SB>and O<SB>2</SB>and inert gas, and the above silicon oxide film by CHF<SB>3</SB>, CF<SB>4</SB>, O<SB>2</SB>and Ar. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置の製造方法に係り、特に素子分離工程、ゲート電極形成工程のシリコン窒化膜マスクのパターン形成を改良した半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which pattern formation of a silicon nitride film mask is improved in an element isolation step and a gate electrode formation step.

従来、特にシリコン酸化膜（ＳｉＯ２膜）及びシリコン窒化膜（Ｓｉ３Ｎ４膜）を含む積層膜を、特許文献１に示すように、ＣＦ系ガス（Ｃ４Ｆ８、Ｃ５Ｆ８、Ｃ４Ｆ６のいずれか一つ）、ＣＨＦ系ガス（ＣＨ３Ｆ、ＣＨ２Ｆ２、ＣＨＦ３のいずれか一つ）、Ｏ２、不活性ガス（Ａｒ）の混合ガスを用いてエッチングを行っている。 Conventionally, a laminated film including a silicon oxide film (SiO 2 film) and a silicon nitride film (Si 3 N 4 film), as shown in Patent Document 1, is generally a CF-based gas (C 4 F 8 , C 5 F 8 , Etching using a mixed gas of any one of C 4 F 6 ), CHF gas (any one of CH 3 F, CH 2 F 2 , CHF 3 ), O 2 , and inert gas (Ar). Is going.

ここで用いる混合ガスは、特許文献１に示す如く、ホール形成に適用しているが、ライン系例えばＳＴＩ（Ｓｈａｌｌｏｗ−Ｔｒｅｎｃｈ−Ｉｓｏｌａｔｉｏｎ）のＳｉエッチング、及びゲート電極エッチングのマスクに用いられるＳｉＮ膜のパターン形成に適用した場合、マスクであるフォトレジストへの選択性は優れているが垂直形状を得ることは困難であること、さらに疎密部の寸法差も大きくなる問題が発生する。   The mixed gas used here is applied to the hole formation as shown in Patent Document 1, but the SiN film used for the mask of the line system, for example, STI (Shallow-Trench-Isolation) Si etching and gate electrode etching. When applied to pattern formation, the selectivity to a photoresist serving as a mask is excellent, but it is difficult to obtain a vertical shape, and the dimensional difference between the sparse and dense portions also increases.

特開２００３−８６５６８号公報JP 2003-86568 A

上述したように、特許文献１の従来の方法では、マスクにおいて重要な、垂直性に欠け、更に疎密部の寸法差も大きくなるという問題があった。
本発明は上記従来の問題に対処し、ＳｉＮ膜等のエッチングにおいてマスク選択性を有し、垂直形状を得ることが可能であり、かつ疎密部での寸法差を抑えた新規なプロセスを提供するものである。 As described above, the conventional method of Patent Document 1 has a problem in that it lacks verticality, which is important for a mask, and further increases the dimensional difference between the sparse and dense portions.
The present invention addresses the above-described conventional problems, and provides a novel process that has mask selectivity in etching of a SiN film and the like, can obtain a vertical shape, and suppresses a dimensional difference in a dense portion. Is.

本発明は、シリコン基板上にシリコン酸化膜、シリコン窒化膜を順に形成し、この後に反射防止膜を形成してリソグラフィ技術によりパターン形成を行い、しかる後、前記反射防止膜を、ＣＨＦ３、ＣＦ４及びＯ２により、前記シリコン窒化膜をＣＨ３Ｆ、ＣＦ４、Ｏ２及び不活性ガスにより、前記シリコン酸化膜をＣＨＦ３、ＣＦ４、Ｏ２及びＡｒによりエッチングすることを特徴とする。
ここで、シリコン窒化膜のエッチングに用いる不活性ガスは、Ａｒ、Ｎｅ、Ｈｅ、ＫｒまたはＸｅから選ばれて少なくとも１つであることが望ましい。
また、反射防止膜をエッチングする時のガスの割合は、ＣＨＦ３：ＣＦ４：Ｏ２＝１：２０〜２５：１〜１．５、圧力が１２〜１４．７Ｐａ（９０〜１１０ｍＴｏｒｒ）であることが望ましい。
さらに、シリコン窒化膜をエッチングする時のガスの割合は、ＣＨ３Ｆ：ＣＦ４：Ｏ２：Ａｒ＝１：１２〜１３：１．６〜１．８：５０〜５５、圧力が１６〜２０Ｐａ（１２０〜１５０ｍＴｏｒｒ）であることが望ましい。
さらにまた、シリコン酸化膜をエッチングする時のガスの割合は、ＣＨＦ３：ＣＦ４：Ｏ２：Ａｒ＝２：５：１：４０、圧力が５．３〜８Ｐａ（４０〜６０ｍＴｏｒｒ）であることが望ましい。
また、前記シリコン基板をエッチングする際、シリコン基板温度を８０〜１００℃とした方がよい。 In the present invention, a silicon oxide film and a silicon nitride film are sequentially formed on a silicon substrate, and thereafter an antireflection film is formed, and pattern formation is performed by a lithography technique. Thereafter, the antireflection film is formed using CHF 3 , CF the 4 and O 2, the silicon nitride film CH 3 F, the CF 4, O 2 and inert gas, characterized by etching by the silicon oxide film CHF 3, CF 4, O 2 and Ar.
Here, the inert gas used for etching the silicon nitride film is preferably at least one selected from Ar, Ne, He, Kr or Xe.
The ratio of the gas when etching the antireflection film is CHF 3 : CF 4 : O 2 = 1: 20 to 25: 1 to 1.5, and the pressure is 12 to 14.7 Pa (90 to 110 mTorr). It is desirable.
Furthermore, the ratio of the gas when etching the silicon nitride film is as follows: CH 3 F: CF 4 : O 2 : Ar = 1: 12 to 13: 1.6 to 1.8: 50 to 55, and the pressure is 16 to 20 Pa. (120 to 150 mTorr) is desirable.
Furthermore, the gas ratio when etching the silicon oxide film is CHF 3 : CF 4 : O 2 : Ar = 2: 5: 1: 40, and the pressure is 5.3 to 8 Pa (40 to 60 mTorr). Is desirable.
Further, when the silicon substrate is etched, the silicon substrate temperature is preferably set to 80 to 100 ° C.

また、本発明の方法は、シリコン基板上にシリコン酸化膜、ポリシリコン膜、シリコン窒化膜を順に形成し、この後反射防止膜を形成して、リソグラフィ技術によりパターン形成を行い、前記反射防止膜をＣＦ４、Ｏ２の混合ガスまたはＮ２、Ｏ２混合ガス、によりエッチングを行い、シリコン窒化膜をＣＨ３Ｆ、ＣＦ４、Ｏ２、不活性ガスによりエッチングすることを特徴とする。 In the method of the present invention, a silicon oxide film, a polysilicon film, and a silicon nitride film are sequentially formed on a silicon substrate, and then an antireflection film is formed, and pattern formation is performed by a lithography technique. Is etched with a mixed gas of CF 4 and O 2 or a mixed gas of N 2 and O 2 , and the silicon nitride film is etched with CH 3 F, CF 4 , O 2 , and an inert gas.

本発明の方法によれば、ＳｉＮ膜のエッチングにおいてマスク選択性を有し、垂直形状を得ることが可能であり、かつ疎密部での寸法差を抑えることができる。   According to the method of the present invention, it is possible to obtain a vertical shape with mask selectivity in etching of a SiN film, and to suppress a dimensional difference in a sparse / dense portion.

本発明の実施形態につき、図１及び図２を用いて詳細に説明する。   An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

（第１の実施形態）
図１は、本発明の第１の実施形態として、ＳＴＩ形成のＳｉエッチングのマスク形成に用いた時の半導体装置の製造方法を説明するための工程断面図である。 (First embodiment)
FIG. 1 is a process cross-sectional view for explaining a method of manufacturing a semiconductor device when used for forming a mask for STI-formed Si etching as a first embodiment of the present invention.

まず、図１（ａ）に示すようにシリコン基板１０１にシリコン酸化膜１０２、シリコン窒化膜１０３を順に成長し、反射防止膜１０４を塗布する。次にフォトレジスト１０５を塗布し公知のリソグラフィ技術にてパターン形成を行う。   First, as shown in FIG. 1A, a silicon oxide film 102 and a silicon nitride film 103 are sequentially grown on a silicon substrate 101, and an antireflection film 104 is applied. Next, a photoresist 105 is applied and a pattern is formed by a known lithography technique.

次に、図１（ｂ）に示すように反射防止膜１０４をＣＨＦ３、ＣＦ４、Ｏ２により、シリコン窒化膜１０３をＣＨ３Ｆ、ＣＦ４、Ｏ２、不活性ガスにより、シリコン酸化膜１０２をＣＨＦ３、ＣＦ４、Ｏ２、Ａｒによりエッチングを行う。
具体的な条件として、反射防止膜１０４のエッチングは、ＣＨＦ３:６（ｓｃｃｍ）、ＣＦ４:１２８（ｓｃｃｍ）Ｏ２:８（ｓｃｃｍ）、圧力：１３．３Ｐａ（１００ｍＴｏｒｒ）、ＲＦパワー:１．１Ｗ／ｃｍ２であり、また、シリコン窒化膜１０３のエッチング条件は、ＣＨ３Ｆ:１０（ｓｃｃｍ）、ＣＦ４:１２５（ｓｃｃｍ）、Ｏ２:１７（ｓｃｃｍ）、Ａｒ：５００（ｓｃｃｍ）、圧力：２０Ｐａ（１３５ｍＴｏｒｒ）、ＲＦパワー:０．８５Ｗ／ｃｍ２あって、また、シリコン酸化膜１０２のエッチング条件は、ＣＨＦ３:３０（ｓｃｃｍ）、ＣＦ４:７５（ｓｃｃｍ）Ｏ２:１５（ｓｃｃｍ）、Ａｒ：６００（ｓｃｃｍ）、圧力：５０ｍＴｏｒｒ、ＲＦパワー：１．４Ｗ／ｃｍ２である。この時の、エッチングの際のシリコン基板温度は８０〜１００℃が望ましい。 Next, as shown in FIG. 1B, the antireflection film 104 is made of CHF 3 , CF 4 , O 2 , and the silicon nitride film 103 is made of CH 3 F, CF 4 , O 2 , an inert gas, and a silicon oxide film. Etching 102 is performed with CHF 3 , CF 4 , O 2 , and Ar.
As specific conditions, the antireflection film 104 is etched by CHF 3 : 6 (sccm), CF 4 : 128 (sccm) O 2 : 8 (sccm), pressure: 13.3 Pa (100 mTorr), RF power: 1 a .1W / cm 2, also, the etching conditions of the silicon nitride film 103, CH 3 F: 10 (sccm ), CF 4: 125 (sccm), O 2: 17 (sccm), Ar: 500 (sccm) pressure: 20Pa (135mTorr), RF power: 0.85 W / cm 2 there are, also, the etching conditions of the silicon oxide film 102 is, CHF 3: 30 (sccm) , CF 4: 75 (sccm) O 2: 15 (Sccm), Ar: 600 (sccm), pressure: 50 mTorr, RF power: 1.4 W / cm 2 . At this time, the temperature of the silicon substrate during etching is desirably 80 to 100 ° C.

この実施形態で用いるエッチング装置としては、図３に示すように半導体基板が載置される電極に周波数１３．５６ＭＨｚのＲＦ電源を有する平行平板型ＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）装置が望ましい。   As an etching apparatus used in this embodiment, a parallel plate type RIE (Reactive Ion Etching) apparatus having an RF power supply with a frequency of 13.56 MHz on an electrode on which a semiconductor substrate is mounted is desirable as shown in FIG.

続いて図１（ｃ）に示すように公知の技術によりアッシング、及び薬液処理を行ってフォトレジスト１０５、反射防止膜１０４を除去する。   Subsequently, as shown in FIG. 1C, ashing and chemical treatment are performed by a known technique to remove the photoresist 105 and the antireflection film 104.

最後に図１（ｄ）に示すように公知のエッチング技術によりシリコン基板１０１のエッチングを行い、溝１０６を形成し、シリコン窒化膜１０３を除去後、絶縁膜を埋め込むことにより素子分離領域が完成する。なお、図１（ｄ）ではシリコン窒化膜の除去及び絶縁膜の埋め込みは省略している。   Finally, as shown in FIG. 1D, the silicon substrate 101 is etched by a known etching technique to form a trench 106, remove the silicon nitride film 103, and embed an insulating film to complete an element isolation region. . In FIG. 1D, the removal of the silicon nitride film and the filling of the insulating film are omitted.

次に、ＣＨ３Ｆ流量を変化させた時の密部（１００ｎｍＬ／Ｓ）、疎部（ＩＳＯ Ｌｉｎｅ、ＩＳＯ Ｓｐａｃｅ）でのシフト量につき、図４（ａ）に示し、この図からＣＨ３Ｆ流量が増加するほどシフト量は＋（プラス）に変動している。
この図４（ａ）から、疎密差を示したのが、図４（ｂ）であり、この図からＣＨ３Ｆの増加により、疎密差が大きくなっていることがわかる。
この結果、シフト量、疎密差を抑えるには、ＣＨ３Ｆの流量調節の必要性がわかる。 Next, dense portion when changing the CH 3 F flow rate (100 Nml / S), sparse unit (ISO Line, ISO Space) per shift amount in, shown in Figure 4 (a), CH 3 F from FIG. As the flow rate increases, the shift amount fluctuates to + (plus).
From FIG. 4 (a), FIG. 4 (b) shows the difference in density, and it can be seen that the density difference increases as CH 3 F increases.
As a result, in order to suppress the shift amount and the density difference, it is understood that it is necessary to adjust the flow rate of CH 3 F.

次に、Ｏ２の流量を変化させた時のシフト量、Ｏ２の流量を変化させた時のＨＭ（ＳｉＮ膜）のテーパー角及びＯ２の流量を変化させた時のマスク残膜につき、図５（ａ）（ｂ）（ｃ）を示す。この図５から、Ｏ２流量増加により 疎密差低減、垂直形状というメリットがあるが、シフト量増大、マスク残膜減少というデメリットがあり、Ｏ２の流量についても、特定の流量に設定する必要があることが判る（本結果ではＯ２＝１７を選択）。 Next, the shift amount when changing the flow rate of O 2, per residual mask film when changing the flow rate of the taper angle and O 2 of HM when the flow rate is varied in O 2 (SiN film), 5A, 5B, and 5C are shown. From FIG. 5, there is a merit that the density difference is reduced and the vertical shape is increased by increasing the O 2 flow rate, but there is a demerit that the shift amount is increased and the mask residual film is decreased. The O 2 flow rate must be set to a specific flow rate. It can be seen that (in this result O 2 = 17 is selected).

上述したことから、特定の流量比を設定することにより、マスク残膜、シフト量、疎密差全てにおいて良好なエッチングが可能となる   As described above, by setting a specific flow rate ratio, it is possible to perform good etching in all of the remaining mask film, shift amount, and density difference.

以上説明したように、上述した第１の実施形態では、シリコン窒化膜をエッチングする際にＣＨＦ系ガスの中ではデポ性が強い ＣＨ３Ｆガスを用いＯ２ガス、不活性ガスの流量を調整することにより、フォトレジストに対し、選択性を保持しながら、疎密寸法差が小さくかつ垂直形状を得ることが可能となる。 As described above, in the first embodiment described above, when etching a silicon nitride film, CH 3 F gas, which has a strong depotency among CHF gases, is used to adjust the flow rates of O 2 gas and inert gas. By doing so, it becomes possible to obtain a vertical shape with a small sparse dimensional difference while maintaining selectivity with respect to the photoresist.

（第２の実施形態）
次に、半発明の第２の実施形態につき、図２を用いて説明する。
図２は、ゲート電極形成において、シリコン窒化膜ハードマスクを用いた時の半導体装置の製造方法を説明するための工程断面図である。
まず図２（ａ）に示すようにシリコン基板２０１にシリコン酸化膜２０２、ポリシリコン膜２０３、シリコン窒化膜２０４を順に成長し、反射防止膜２０５を塗布する。次にフォトレジスト２０６を塗布し公知のリソグラフィ技術にてパターン形成を行う。 (Second Embodiment)
Next, a second embodiment of the semi-invention will be described with reference to FIG.
FIG. 2 is a process cross-sectional view for explaining a method of manufacturing a semiconductor device when a silicon nitride hard mask is used in forming a gate electrode.
First, as shown in FIG. 2A, a silicon oxide film 202, a polysilicon film 203, and a silicon nitride film 204 are sequentially grown on a silicon substrate 201, and an antireflection film 205 is applied. Next, a photoresist 206 is applied and a pattern is formed by a known lithography technique.

次に図２（ｂ）に示すようにフォトレジスト２０６、及び反射防止膜２０５をＣＦ４、Ｏ２の混合ガスまたはＮ２、Ｏ２混合ガスにより、シリコン窒化膜１０３をＣＨ３Ｆ、ＣＦ４、Ｏ２、不活性ガスによりエッチングを行う。
シリコン窒化膜エッチングの具体的な条件としては、ＣＨ３Ｆ：１０（ｓｃｃｍ）、ＣＦ４:１２５（ｓｃｃｍ）Ｏ２：１７（ｓｃｃｍ）、Ａｒ：５００（ｓｃｃｍ）、圧力:２０Ｐａ（１３５ｍＴｏｒｒ）、ＲＦパワー：０．８５Ｗ／ｃｍ２であって、エッチングの際のシリコン基板温度は、８０〜１００℃が望ましい。
また、エッチング装置としては、上記第１の実施形態と同様、図３に示すように半導体基板が載置される電極に周波数１３．５６ＭＨｚのＲＦ電源を有する平行平板型ＲＩＥ装置が望ましい。 Next, as shown in FIG. 2B, the photoresist 206 and the antireflection film 205 are made of a mixed gas of CF 4 and O 2 or a mixed gas of N 2 and O 2 , and the silicon nitride film 103 is made of CH 3 F and CF 4. Etching is performed with O 2 , inert gas.
Specific conditions for etching the silicon nitride film include: CH 3 F: 10 (sccm), CF 4 : 125 (sccm) O 2 : 17 (sccm), Ar: 500 (sccm), pressure: 20 Pa (135 mTorr), RF power: 0.85 W / cm 2 The silicon substrate temperature during etching is desirably 80 to 100 ° C.
As the etching apparatus, a parallel plate type RIE apparatus having an RF power source with a frequency of 13.56 MHz on the electrode on which the semiconductor substrate is mounted as shown in FIG. 3 is desirable as in the first embodiment.

続いて図２（ｃ）に示すように公知の技術によりアッシング、及び薬液処理を行ってフォトレジスト２０６、反射防止膜２０５を除去する。   Subsequently, as shown in FIG. 2C, ashing and chemical treatment are performed by a known technique to remove the photoresist 206 and the antireflection film 205.

最後に、図２（ｄ）に示すように、公知のエッチング技術によりポリシリコン膜２０３のエッチングを行い、シリコン窒化膜２０４、および露出したシリコン酸化膜２０３を公知の技術により除去し、ゲート電極２０７を形成する。   Finally, as shown in FIG. 2D, the polysilicon film 203 is etched by a known etching technique, the silicon nitride film 204 and the exposed silicon oxide film 203 are removed by a known technique, and the gate electrode 207 is removed. Form.

上述した第２の実施形態は、５０ｎｍ以下の微細ゲート電極形成においてシリコン窒化膜マスクを適用する場合においても、シリコン窒化膜エッチング時にフォトレジストに対し選択性を保持することによりシリコン窒化膜マスクがダメージを受けることなく、かつ垂直形状を維持し、かつ疎密部で寸法差の無いマスク形成を行うことが可能である。   In the second embodiment described above, even when a silicon nitride mask is applied in forming a fine gate electrode of 50 nm or less, the silicon nitride mask is damaged by maintaining selectivity with respect to the photoresist during etching of the silicon nitride film. It is possible to form a mask without any difference in size, maintaining a vertical shape, and having no dimensional difference in a dense portion.

本発明の第１の実施形態を説明するための工程断面図。Process sectional drawing for demonstrating the 1st Embodiment of this invention. 本発明の第２の実施形態を説明するための工程断面図。Process sectional drawing for demonstrating the 2nd Embodiment of this invention. 本発明の第１の実施形態及び第２の実施形態で用いたエッチング装置の概略を示す図。The figure which shows the outline of the etching apparatus used in the 1st Embodiment and 2nd Embodiment of this invention. 本発明の第１の実施形態を説明するための図The figure for demonstrating the 1st Embodiment of this invention 本発明の第１の実施形態を説明するための図The figure for demonstrating the 1st Embodiment of this invention

符号の説明Explanation of symbols

１０１：シリコン基板
１０２：シリコン酸化膜
１０３：シリコン窒化膜
１０４：反射防止膜
１０５：フォトレジスト
１０６：溝 101: Silicon substrate 102: Silicon oxide film 103: Silicon nitride film 104: Antireflection film 105: Photo resist 106: Groove

Claims (7)

シリコン基板上にシリコン酸化膜、シリコン窒化膜を順に形成し、この後に反射防止膜を形成してリソグラフィ技術によりパターン形成を行い、しかる後、前記反射防止膜を、ＣＨＦ３、ＣＦ４及びＯ２により、前記シリコン窒化膜をＣＨ３Ｆ、ＣＦ４、Ｏ２及び不活性ガスにより、前記シリコン酸化膜をＣＨＦ３、ＣＦ４、Ｏ２及びＡｒによりエッチングすることを特徴とする半導体装置の製造方法。 A silicon oxide film and a silicon nitride film are sequentially formed on the silicon substrate, and then an antireflection film is formed, and pattern formation is performed by a lithography technique. Thereafter, the antireflection film is formed as CHF 3 , CF 4, and O 2. The silicon nitride film is etched with CH 3 F, CF 4 , O 2 and an inert gas, and the silicon oxide film is etched with CHF 3 , CF 4 , O 2 and Ar. . 前記シリコン窒化膜のエッチングに用いる不活性ガスは、Ａｒ、Ｎｅ、Ｈｅ、ＫｒまたはＸｅから選ばれて少なくとも１つであることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the inert gas used for etching the silicon nitride film is at least one selected from Ar, Ne, He, Kr or Xe. 前記反射防止膜をエッチングする時のガスの割合は、ＣＨＦ３：ＣＦ４：Ｏ２＝１：２０〜２５：１〜１．５、圧力が１２〜１４．７Ｐａ（９０〜１１０ｍＴｏｒｒ）であることを特徴とする請求項１記載の半導体装置の製造方法。 The gas ratio when etching the antireflection film is CHF 3 : CF 4 : O 2 = 1: 20 to 25: 1 to 1.5, and the pressure is 12 to 14.7 Pa (90 to 110 mTorr). The method of manufacturing a semiconductor device according to claim 1. 前記シリコン窒化膜をエッチングする時のガスの割合は、ＣＨ３Ｆ：ＣＦ４：Ｏ２：Ａｒ＝１：１２〜１３：１．６〜１．８：５０〜５５、圧力が１６〜２０Ｐａ（１２０〜１５０ｍＴｏｒｒ）であることを特徴とする請求項１記載の半導体装置の製造方法。 The ratio of gas when etching the silicon nitride film is as follows: CH 3 F: CF 4 : O 2 : Ar = 1: 12 to 13: 1.6 to 1.8: 50 to 55, and the pressure is 16 to 20 Pa ( 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is 120 to 150 mTorr). 前記シリコン酸化膜をエッチングする時のガスの割合は、ＣＨＦ３：ＣＦ４：Ｏ２：Ａｒ＝２：５：１：４０、 圧力が５．３〜８Ｐａ（４０〜６０ｍＴｏｒｒ）であることを特徴とする請求項１記載の半導体装置の製造方法。 The gas ratio for etching the silicon oxide film is CHF 3 : CF 4 : O 2 : Ar = 2: 5: 1: 40, and the pressure is 5.3 to 8 Pa (40 to 60 mTorr). A method for manufacturing a semiconductor device according to claim 1. 前記シリコン基板をエッチングする際、シリコン基板温度が８０〜１００℃であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein when the silicon substrate is etched, the temperature of the silicon substrate is 80 to 100 [deg.] C. シリコン基板上にシリコン酸化膜、ポリシリコン膜、シリコン窒化膜を順に形成し、この後反射防止膜を形成して、リソグラフィ技術によりパターン形成を行い、前記反射防止膜をＣＦ４、Ｏ２の混合ガスまたはＮ２、Ｏ２混合ガス、によりエッチングを行い、シリコン窒化膜をＣＨ３Ｆ、ＣＦ４、Ｏ２、不活性ガスによりエッチングすることを特徴とする半導体装置の製造方法

A silicon oxide film, a polysilicon film, and a silicon nitride film are sequentially formed on a silicon substrate, and then an antireflection film is formed, and pattern formation is performed by a lithography technique, and the antireflection film is mixed with CF 4 and O 2 . Etching with a gas or a mixed gas of N 2 and O 2 , and etching the silicon nitride film with CH 3 F, CF 4 , O 2 , and an inert gas, a method for manufacturing a semiconductor device

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JP2007266291A (en) * 2006-03-28 2007-10-11 Tokyo Electron Ltd Method for manufacturing semiconductor device, plasma treatment device and storage medium
JP2008270522A (en) * 2007-04-20 2008-11-06 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
US8263498B2 (en) 2006-03-28 2012-09-11 Tokyo Electron Limited Semiconductor device fabricating method, plasma processing system and storage medium

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JPH05160077A (en) * 1991-12-05 1993-06-25 Sharp Corp Plasma etching method
JPH118223A (en) * 1997-03-31 1999-01-12 Applied Materials Inc Selective plasma etching of silicon nitride coexisting with silicon or silicon oxide using methyl fluoride or ethyl difluoride and mixture of tetrafluoro-carbon and oxygen
JPH11102896A (en) * 1997-08-15 1999-04-13 Internatl Business Mach Corp <Ibm> Anisotropic selective nitride etching for featuring high aspect ratio in high-density plasma
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266291A (en) * 2006-03-28 2007-10-11 Tokyo Electron Ltd Method for manufacturing semiconductor device, plasma treatment device and storage medium
US8263498B2 (en) 2006-03-28 2012-09-11 Tokyo Electron Limited Semiconductor device fabricating method, plasma processing system and storage medium
JP2008270522A (en) * 2007-04-20 2008-11-06 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device

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