CN102610490A - Method for manufacturing trench of super junction - Google Patents
Method for manufacturing trench of super junction Download PDFInfo
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- CN102610490A CN102610490A CN2011100214238A CN201110021423A CN102610490A CN 102610490 A CN102610490 A CN 102610490A CN 2011100214238 A CN2011100214238 A CN 2011100214238A CN 201110021423 A CN201110021423 A CN 201110021423A CN 102610490 A CN102610490 A CN 102610490A
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Abstract
The invention discloses a method for manufacturing a trench of a super junction. The method comprises the following steps that: A, bottom layer silicon oxide, middle silicon nitride and top layer silicon oxynitride are sequentially deposited on a silicon base plate; B, a layer of positive photoresist is coated, and 0-3mm photoresist is removed at the edge; C, the top layer silicon oxynitride is etched in positions with a distance being 0-3mm from the circumference, and the photoresist is used as a blocking layer; D, the photoresist is removed; E, a layer of negative photoresist is coated; F, a photoresist machine is adopted for overall exposure and development; G, a layer of positive photoresist is coated; H, photoetching is carried out for forming trenches, and development is carried out; I, the bottom layer silicon oxide, the middle silicon nitride and the top layer silicon oxynitride are etched, and the photoresist is used as a blocking layer; and J, the photoresist is removed; and K, a trench being 2-80 microns is etched in the silicon base plate, and the bottom layer silicon oxide is used as a blocking layer. The method has the advantages that the silicon grass phenomenon after etching can be avoided, or the condition that an acid groove is contaminated caused by generation of many silicon particles is avoided.
Description
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process, especially a kind of trench fabrication methods that is used for super junction.
Background technology
At present; In Super Junction (super junction) manufacturing process; Because photoetching form trench (groove) if the time photoetching trimming can cause etching after silicon grass (silicon tip thorn); Thereby can influence yield (yield), and trimming does not have a lot of particles (particulate or particle) and takes acid tank to and pollute, cause can't volume production situation.
As shown in Figure 2, the concrete technological process of the groove manufacturing process of present existing super junction is:
A is deposit ONO layer (silicon nitride 3-top layer silica 4 in the middle of the bottom silica 2-) on silicon substrate 1, sees Fig. 2 A;
B is coated with one deck positive photoresist 5 (EBR is zero, and EBR refers to that the edge removes photoresist), sees Fig. 2 B; The technical sophistication of photoresist, kind is more, according to its chemical reaction mechanism and development principle, can divide two types of negative photoresist and positive photoresists; What form insoluble material after the illumination is negative photoresist; Otherwise, be insoluble to some solvent, after illumination, become the positive photoresist that is of soluble substance; Existing super junction groove manufacturing process adopts positive photoresist;
The C photoetching forms groove (WEE is zero, and WEE refers to the silicon chip edge exposure), and develops, and sees Fig. 2 C;
D etches away part of O NO layer, as etching barrier layer, sees Fig. 2 D with positive photoresist 5;
E removes positive photoresist 5, sees Fig. 2 E;
F etches the groove of a 40um (micron) on silicon substrate 1, as etching barrier layer, see Fig. 2 F with the bottom silica 2 of ONO layer.
Summary of the invention
The technical problem that the present invention will solve provides a kind of trench fabrication methods that is used for super junction, and this method can be avoided silicon grass (silicon tip thorn) phenomenon of etching or produce a lot of particles (particulate or particle) causing that acid tank pollutes.
For solving the problems of the technologies described above, the present invention provides a kind of trench fabrication methods that is used for super junction, comprises the steps:
A. deposit bottom silica, middle silicon nitride and top layer silicon oxynitride successively on silicon substrate;
B. be coated with one deck positive photoresist and the edge 0-3mm that removes photoresist;
C. etching is apart from peripheral 0-3mm place top layer silicon oxynitride, with photoresist as the barrier layer;
D. remove photoresist;
E. be coated with the last layer negative photoresist;
F. go up mask aligner blanket exposure and development;
G. be coated with the last layer positive photoresist;
H. photoetching forms groove and develops;
I. etching bottom silica, middle silicon nitride, top layer silicon oxynitride, with photoresist as the barrier layer;
J. remove photoresist;
K. on silicon substrate, etch the groove of a 2-80 micron, with the bottom silica as the barrier layer.
In steps A, the thickness of said bottom silica be 2500 dusts to 15000 dusts, the thickness of middle silicon nitride is 50 dusts-1500 dusts, the thickness of top layer silicon oxynitride is that 100 dusts are to 15000 dusts; Wherein, the bottom silica adopts the thermal oxidation technology growth, and temperature is 800-1200 ℃; Middle silicon nitride adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-800 ℃; The top layer silicon oxynitride adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-900 ℃.
In step B and step G, the thickness of described positive photoresist is that 1000 dusts are to 100000 dusts.
In step e, the thickness of described negative photoresist is that 1000 dusts are to 100000 dusts.
In step F, the described upward mask aligner blanket exposure and the energy that uses that develops arrive 100mJ as 10mJ.
In step e and step G, it is zero that the edge removes photoresist.
In step H, said photoetching forms in the groove process, and the silicon chip edge exposure is zero.
Compare with prior art; The present invention has following beneficial effect: existing processes adopts oxide-film to make pattern (figure) as hard mask (hard mask layer or barrier layer) and with positive photoresist; Shown in Figure 1A; Adopt silicon grass (silicon tip thorn) phenomenon after existing technology can cause etching, and trimming does not have a lot of particles (particulate or particle) and takes acid tank to and pollute.And the present invention is as hard mask and the situation that adopts the photoetching method of negative photoresist can avoid existing processes to run into SION (silicon oxynitride).Shown in Figure 1B, adopt thick can the increasing of glue of wafer (silicon chip) periphery after the technology of the present invention, thereby can avoid the not enough etching of silicon chips periphery and the silicon grass phenomenon that causes and acid tank by the phenomenon of silicon grain pollution.
Description of drawings
Fig. 1 is the effect comparison sketch map of groove manufacturing process of groove manufacturing process and the existing super junction of super junction of the present invention; Wherein, Figure 1A is the effect sketch map of existing technology; Figure 1B is the effect sketch map of technology of the present invention;
Fig. 2 is the flow chart of the groove manufacturing process of existing super junction; Wherein, Fig. 2 A is the sketch map after steps A is accomplished; Fig. 2 B is the sketch map after step B accomplishes; Fig. 2 C is the sketch map after step C accomplishes; Fig. 2 D is the sketch map after step D accomplishes; Fig. 2 E is the sketch map after step e is accomplished; Fig. 2 F is the sketch map after step F is accomplished; Wherein, the 1st, silicon substrate, the 2nd, bottom silica, the 3rd, middle silicon nitride, the 4th, top layer silica, the 5th, positive photoresist;
Fig. 3 is the flow chart of the groove manufacturing process of super junction of the present invention; Wherein, Fig. 3 A is the sketch map after steps A is accomplished; Fig. 3 B is the sketch map after step B accomplishes; Fig. 3 C is the sketch map after step C accomplishes; Fig. 3 D is the sketch map after step D accomplishes; Fig. 3 E is the sketch map after step e is accomplished; Fig. 3 F is the sketch map after step F is accomplished; Fig. 3 G is the sketch map after step G accomplishes; Fig. 3 H is the sketch map after step H accomplishes; Fig. 3 I is the sketch map after step I accomplishes; Fig. 3 J is the sketch map after step J accomplishes; Fig. 3 K is the sketch map after step K is accomplished; Wherein, the 11st, silicon substrate, the 12nd, bottom silica; The 13rd, middle silicon nitride, the 14th, top layer silicon oxynitride, the 15th, positive photoresist; The 16th, negative photoresist, the 17th, positive photoresist, the membranous pattern of silicon chips periphery after 18 expression process photoetching for the first time and the etching processing.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.
The present invention provides a kind of trench fabrication methods that is used for super junction; This method is during semiconductor integrated circuit is produced; In Super Junction (super junction) technology; Through adjustment rete design and photolithography process, thereby the method for improving wafer periphery photoresist thickness is avoided the silicon grass phenomenon of etching or produces a lot of particles taking acid tank to and polluting.
As shown in Figure 3, the inventive method mainly comprises the steps:
A deposit bottom silica 12, middle silicon nitride 13, top layer silicon oxynitride 14 successively on silicon substrate 11; The thickness of bottom silica 12 is that 2500 dusts are to 15000 dusts; The thickness of middle silicon nitride 13 is 50 dusts-1500 dusts, the thickness of top layer silicon oxynitride 14 be 100 dusts to 15000 dusts, see Fig. 3 A; Wherein, bottom silica 12 adopts the thermal oxidation technology growth, and temperature is 800-1200 ℃; Middle silicon nitride 13 adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-800 ℃; Top layer silicon oxynitride 14 adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-900 ℃.
B is coated with one deck positive photoresist 15 and EBR (edge removes photoresist) 0-3mm (for example, 2.1mm removes photoresist at present embodiment employing edge), sees Fig. 3 B; Wherein, the thickness of positive photoresist 15 is that 1000 dusts are to 100000 dusts;
The C etching is located top layer silicon oxynitride 14 apart from peripheral 0-3mm (for example, 2.1mm removes photoresist at present embodiment employing edge), as the barrier layer, sees Fig. 3 C with positive photoresist 15;
D removes positive photoresist 15, sees Fig. 3 D;
E is coated with last layer negative photoresist 16, and EBR is zero, sees Fig. 3 E; Wherein, the thickness of negative photoresist 16 is that 1000 dusts are to 100000 dusts;
The last mask aligner blanket exposure of F is also developed, and the energy that this step is used to 100mJ, is seen Fig. 3 F as 10mJ, wherein, and the membranous pattern of silicon chips periphery after 18 expression process photoetching for the first time and the etching processing;
G is coated with last layer positive photoresist 17 (EBR is zero), sees Fig. 3 G; Wherein, the thickness of positive photoresist 17 is that 1000 dusts are to 100000 dusts;
The H photoetching forms groove (WEE is zero), and develops, and sees Fig. 3 H;
I etches away bottom silica 12, middle silicon nitride 13, top layer silicon oxynitride 14, as the barrier layer, sees Fig. 3 I with positive photoresist 17;
J removes positive photoresist 17, sees Fig. 3 J;
K etches the groove (for example, present embodiment etches the groove of a 35um) of a 2-80um (micron) on silicon substrate 11, as the barrier layer, see Fig. 3 K with bottom silica 12.
The present invention does not adopt silica as hard mask and with the photoetching method of positive photoresist (not trimming), but with SION (silicon oxynitride) as hard mask and the following phenomenon that adopts the photoetching method of negative photoresist can avoid existing technology to run into: the not enough etching of silicon chips periphery and the silicon grass phenomenon that causes and acid tank are by the phenomenon of silicon grain pollution.
Claims (7)
1. a trench fabrication methods that is used for super junction is characterized in that, comprises the steps:
A. deposit bottom silica, middle silicon nitride and top layer silicon oxynitride successively on silicon substrate;
B. be coated with one deck positive photoresist and the edge 0-3mm that removes photoresist;
C. etching is apart from peripheral 0-3mm place top layer silicon oxynitride, with photoresist as the barrier layer;
D. remove photoresist;
E. be coated with the last layer negative photoresist;
F. go up mask aligner blanket exposure and development;
G. be coated with the last layer positive photoresist;
H. photoetching forms groove and develops;
I. etching bottom silica, middle silicon nitride, top layer silicon oxynitride, with photoresist as the barrier layer;
J. remove photoresist;
K. on silicon substrate, etch the groove of a 2-80 micron, with the bottom silica as the barrier layer.
2. the trench fabrication methods that is used for super junction as claimed in claim 1; It is characterized in that in steps A, the thickness of said bottom silica is that 2500 dusts are to 15000 dusts; The thickness of middle silicon nitride is 50 dusts-1500 dusts, and the thickness of top layer silicon oxynitride is that 100 dusts are to 15000 dusts; Wherein, the bottom silica adopts the thermal oxidation technology growth, and temperature is 800-1200 ℃; Middle silicon nitride adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-800 ℃; The top layer silicon oxynitride adopts the growth of low pressure chemical gaseous phase deposition technology, and temperature is 300-900 ℃.
3. the trench fabrication methods that is used for super junction as claimed in claim 1 is characterized in that, in step B and step G, the thickness of described positive photoresist is that 1000 dusts are to 100000 dusts.
4. the trench fabrication methods that is used for super junction as claimed in claim 1 is characterized in that, in step e, the thickness of described negative photoresist is that 1000 dusts are to 100000 dusts.
5. the trench fabrication methods that is used for super junction as claimed in claim 1 is characterized in that, in step F, the described upward mask aligner blanket exposure and the energy that uses that develops arrive 100mJ as 10mJ.
6. the trench fabrication methods that is used for super junction as claimed in claim 1 is characterized in that, in step e and step G, it is zero that the edge removes photoresist.
7. the trench fabrication methods that is used for super junction as claimed in claim 1 is characterized in that, in step H, said photoetching forms in the groove process, and the silicon chip edge exposure is zero.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100214238A CN102610490A (en) | 2011-01-19 | 2011-01-19 | Method for manufacturing trench of super junction |
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| CN2011100214238A CN102610490A (en) | 2011-01-19 | 2011-01-19 | Method for manufacturing trench of super junction |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN103984212A (en) * | 2014-05-27 | 2014-08-13 | 上海华力微电子有限公司 | Method for improving exposure shape of photoresist and method for patterning semiconductor substrate |
-
2011
- 2011-01-19 CN CN2011100214238A patent/CN102610490A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN103035506B (en) * | 2012-08-09 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | The lithographic method of RFLDMOS spacer medium layer depth groove |
| CN103984212A (en) * | 2014-05-27 | 2014-08-13 | 上海华力微电子有限公司 | Method for improving exposure shape of photoresist and method for patterning semiconductor substrate |
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Application publication date: 20120725 |