CN106128952A - Improve method and the MOS transistor of defects of wafer edge - Google Patents
Improve method and the MOS transistor of defects of wafer edge Download PDFInfo
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- CN106128952A CN106128952A CN201610596459.1A CN201610596459A CN106128952A CN 106128952 A CN106128952 A CN 106128952A CN 201610596459 A CN201610596459 A CN 201610596459A CN 106128952 A CN106128952 A CN 106128952A
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- 230000007547 defect Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/08—Etching
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- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of method improving defects of wafer edge and MOS transistor.The method improving defects of wafer edge includes: in semiconductor fabrication, and on wafer, coating is for defining initial first photoresist layer of the active area of MOS transistor, and the marginal area of initial first photoresist layer defines redundancy edge chamfer region；Remove the redundancy edge chamfer region of initial first photoresist layer；Utilize the first photoresist layer, by the active area of photoetching with etching technics definition MOS transistor；Perform form well region and form the step of field oxide to form oxide layer；On wafer, coating is for defining initial second photoresist layer of the trench region of MOS transistor, and the marginal area of the second photoresist layer defines redundancy edge chamfer region；Remove the second photoresist layer redundancy edge chamfer region, expose the described oxide layer that redundancy edge chamfer region is covered；Utilize the second photoresist layer, by the trench region of photoetching with etching technics definition MOS transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of defects of wafer edge of improving
Method and use the MOS transistor that the method for this improvement makes.
Background technology
At semiconductor applications, U-shaped trenched mos transistor (U-groove MOSFET) is widely adopted.And U-shaped groove
MOS transistor has the deepest silicon trench (grid), and the degree of depth of silicon trench is generally 1um to 2.5um.
When carrying out etching groove, silicon pin defect (silicon grass can be produced on wafer edge portion nude film
Defect, also referred to as silicon tip thorn defect).Specifically, the photoresist on crystal round fringes is often uneven, and wafer limit
Photoresist thickness at edge can be thinning, thus can not resist etching groove, thus can form defects of wafer edge further (such as figure
1, shown in the microscopical view of Fig. 2 and Fig. 3).
Such defect can fall into follow-up wet-cleaning instrument, and can pollute the follow-up product being fabricated by.
Accordingly, it is desirable to a kind of skill of silicon pin defect that can eliminate or improve crystal round fringes at least in part can be provided
Art scheme.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can eliminate
Or the method improving the silicon pin defect of crystal round fringes at least in part and the MOS crystal using the method for this improvement to make
Pipe.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of method improving defects of wafer edge, bag
Include:
First step: in semiconductor fabrication, on wafer, coating is for defining at the beginning of the active area of MOS transistor
Begin the first photoresist layer；Wherein, the marginal area of initial first photoresist layer defines redundancy edge chamfer region；
Second step: remove the redundancy edge chamfer region of initial first photoresist layer；
Third step: after removing redundancy edge chamfer region, utilize the first photoresist layer, by photoetching and etching work
The active area of skill definition MOS transistor；
4th step: perform form well region and form the step such as field oxide, removed the at the end of this step
Thick oxide layer is defined in one photoresist layer redundancy edge chamfer region；
5th step: coating is for defining initial second photoresist layer of the trench region of MOS transistor on wafer；Its
In, the marginal area of the second photoresist layer defines redundancy edge chamfer region；
6th step: remove the second photoresist layer redundancy edge chamfer region, exposes redundancy edge chamfer region and is covered
Described oxide layer；
7th step: after removing redundancy edge chamfer region, utilize the second photoresist layer, by photoetching and etching work
The trench region of skill definition MOS transistor.
Preferably, wafer includes substrate area and epi region.
Preferably, the size of initial second photoresist layer is equal to the size of initial first photoresist layer.
Preferably, the size removing the second photoresist layer after redundancy edge chamfer region is fallen more than removing redundancy edge
The size of the first photoresist layer after angular zone.
Preferably, it is superfluous that the overlay area of the second photoresist layer after removing redundancy edge chamfer region is completely covered removal
The overlay area of the first photoresist layer after remaining edge chamfer region.
Preferably, described MOS transistor is U-shaped trenched mos transistor.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of use the above-mentioned defects of wafer edge that improves
The MOS transistor that method is made.
Preferably, described MOS transistor is U-shaped trenched mos transistor.
In the present invention, when etching groove, the surface that edge exposes is oxide rather than silicon, even if photoresist is uneven
Even and edge bead is relatively thin and etching can not be resisted, the etching of oxide is also the slowest, from without formed silicon pin lack
Fall into.Thus, the invention provides a kind of method of silicon pin defect that can eliminate or improve crystal round fringes at least in part.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the microscopical view of defects of wafer edge.
Fig. 2 schematically shows another microscopical view of defects of wafer edge.
Fig. 3 schematically shows another microscopical view of defects of wafer edge.
Fig. 4 schematically shows the microscopical view improving crystal round fringes of preferred embodiment, and (the second photoresist 300 defines
Edge).
Fig. 5 schematically shows another microscopical view (first photoresist 200 improving crystal round fringes of preferred embodiment
The edge of definition).
Fig. 6 schematically shows the flow process of the method improving defects of wafer edge according to the preferred embodiment of the invention
Figure.
Fig. 7 schematically shows the photoresist of the method improving defects of wafer edge according to the preferred embodiment of the invention
The schematic diagram of size.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 6 schematically shows the flow process of the method improving defects of wafer edge according to the preferred embodiment of the invention
Figure.
Specifically, as shown in Figure 6, the method improving defects of wafer edge according to the preferred embodiment of the invention includes depending on
The following step of secondary execution:
First step S1: in semiconductor fabrication, on wafer 100, coating is for defining the active of MOS transistor
Initial first photoresist layer 200 in district；Wherein, the marginal area of initial first photoresist layer 200 defines redundancy edge chamfer
Region；
Typically, wafer 100 includes substrate area and epi region.
Second step S2: remove the redundancy edge chamfer region of initial first photoresist layer 200；
Third step S3: removing after redundancy edge chamfer region, utilizes the first photoresist layer 200, by photoetching with
The active area of etching technics definition MOS transistor；
4th step S4: perform to form well region, form the steps such as field oxide, to form oxide layer；
5th step S5: coating is for defining initial second photoresist of the trench region of MOS transistor on wafer 100
Layer 300；Wherein, the marginal area of the second photoresist layer 300 defines redundancy edge chamfer region；
Wherein, typically, the size of initial second photoresist layer 300 is equal to the size of initial first photoresist layer 200.
6th step S6: remove the redundancy edge chamfer region of the second photoresist layer 300, exposes redundancy edge chamfer region
The described oxide layer covered；
Remove the size of the second photoresist layer 300 after redundancy edge chamfer region more than removing redundancy edge chamfer district
The size of the first photoresist layer 200 after territory.And, remove the second photoresist layer 300 after redundancy edge chamfer region
Overlay area the overlay area of removing first photoresist layer 200 redundancy edge chamfer region after is completely covered.
The second photoresist layer 300 after wafer 100, removal redundancy edge chamfer region, removal redundancy edge chamfer district
The size relationship between the first photoresist layer 200 and overlay area relation after territory can be as shown in Figure 7.
7th step S7: removing after redundancy edge chamfer region, utilizes the second photoresist layer 300, by photoetching with
The trench region of etching technics definition MOS transistor.
Fig. 4 schematically shows the microscopical view improving crystal round fringes of preferred embodiment, and (the second photoresist 300 defines
Edge).Fig. 5 schematically shows another microscopical view (first photoresist 200 improving crystal round fringes of preferred embodiment
The edge of definition).Wherein demonstrate, after using the method for the present invention, the picture of crystal round fringes diverse location, do not find silicon tip
Thorn defect.
The oxide layer formed in technique between two-layer lithography layer can be exposed after determining the edge photoetching of second layer photoresist
This layer of oxide layer, it is ensured that ensuing edge etch is to be engraved in oxide layer rather than on silicon, protects following silicon layer.Cause
For the difference of rate of etch, it is very slow that oxide layer is carved, and will not form the defect of spine.
Thus, in the present invention, when etching groove, the surface that edge exposes is oxide rather than silicon, though photoetching
Glue is uneven and edge bead is relatively thin and can not resist etching, and the etching of oxide is also the slowest, from without being formed
Silicon pin defect.Thus, the invention provides a kind of silicon pin defect that can eliminate or improve crystal round fringes at least in part
Method.
According to another preferred embodiment of the invention, it is provided that a kind of use the above-mentioned method system improving defects of wafer edge
The MOS transistor become.
Preferably, described MOS transistor is U-shaped trenched mos transistor.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (8)
1. the method improving defects of wafer edge, it is characterised in that including:
First step: in semiconductor fabrication, on wafer, coating is for defining initial the of the active area of MOS transistor
One photoresist layer；Wherein, the marginal area of initial first photoresist layer defines redundancy edge chamfer region；
Second step: remove the redundancy edge chamfer region of initial first photoresist layer；
Third step: after removing redundancy edge chamfer region, utilize the first photoresist layer, fixed with etching technics by photoetching
The active area of justice MOS transistor；
4th step: perform form well region and form the steps such as field oxide, at removed first light at the end of this step
Photoresist layer redundancy edge chamfer defines thick oxide layer in region；
5th step: coating is for defining initial second photoresist layer of the trench region of MOS transistor on wafer；Wherein,
The marginal area of the second photoresist layer defines redundancy edge chamfer region；
6th step: remove the second photoresist layer redundancy edge chamfer region, expose the institute that redundancy edge chamfer region is covered
State oxide layer；
7th step: after removing redundancy edge chamfer region, utilize the second photoresist layer, fixed with etching technics by photoetching
The trench region of justice MOS transistor.
The method improving defects of wafer edge the most according to claim 1, it is characterised in that wafer include substrate area and
Epi region.
The method improving defects of wafer edge the most according to claim 1 and 2, it is characterised in that initial second photoresist
The size of layer is equal to the size of initial first photoresist layer.
The method improving defects of wafer edge the most according to claim 1 and 2, it is characterised in that remove redundancy edge and fall
The size of the second photoresist layer after angular zone is more than the chi of the first photoresist layer removed after redundancy edge chamfer region
Very little.
The method improving defects of wafer edge the most according to claim 1 and 2, it is characterised in that remove redundancy edge and fall
The overlay area of the second photoresist layer after angular zone is completely covered the first photoetching removed after redundancy edge chamfer region
The overlay area of glue-line.
The method improving defects of wafer edge the most according to claim 1 and 2, it is characterised in that described MOS transistor is
U-shaped trenched mos transistor.
7. one kind uses the MOS transistor that the method improving defects of wafer edge according to claim 1 and 2 is made.
MOS transistor the most according to claim 7, it is characterised in that described MOS transistor is U-shaped groove MOS crystal
Pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596459.1A CN106128952A (en) | 2016-07-27 | 2016-07-27 | Improve method and the MOS transistor of defects of wafer edge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610596459.1A CN106128952A (en) | 2016-07-27 | 2016-07-27 | Improve method and the MOS transistor of defects of wafer edge |
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| Publication Number | Publication Date |
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| CN106128952A true CN106128952A (en) | 2016-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610596459.1A Pending CN106128952A (en) | 2016-07-27 | 2016-07-27 | Improve method and the MOS transistor of defects of wafer edge |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291315B1 (en) * | 1996-07-11 | 2001-09-18 | Denso Corporation | Method for etching trench in manufacturing semiconductor devices |
| KR20070003043A (en) * | 2005-06-30 | 2007-01-05 | 주식회사 하이닉스반도체 | Method for fabricating trench isolation in semiconductor device |
| US20070145474A1 (en) * | 2005-11-10 | 2007-06-28 | Stmicroelectronics S.R.L. | Vertical-gate mos transistor for high voltage applications with differentiated oxide thickness |
| US20080003830A1 (en) * | 2006-06-30 | 2008-01-03 | Su Ruo Qing | Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge |
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN103050404A (en) * | 2011-10-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Method of manufacturing grooves and protective rings of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device |
| CN105097531A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device terminal structure manufacturing method |
| CN105679667A (en) * | 2016-03-09 | 2016-06-15 | 上海道之科技有限公司 | Manufacturing method for terminal structure of trench IGBT device |
-
2016
- 2016-07-27 CN CN201610596459.1A patent/CN106128952A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291315B1 (en) * | 1996-07-11 | 2001-09-18 | Denso Corporation | Method for etching trench in manufacturing semiconductor devices |
| KR20070003043A (en) * | 2005-06-30 | 2007-01-05 | 주식회사 하이닉스반도체 | Method for fabricating trench isolation in semiconductor device |
| US20070145474A1 (en) * | 2005-11-10 | 2007-06-28 | Stmicroelectronics S.R.L. | Vertical-gate mos transistor for high voltage applications with differentiated oxide thickness |
| US20080003830A1 (en) * | 2006-06-30 | 2008-01-03 | Su Ruo Qing | Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge |
| CN103050404A (en) * | 2011-10-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Method of manufacturing grooves and protective rings of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device |
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN105097531A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device terminal structure manufacturing method |
| CN105679667A (en) * | 2016-03-09 | 2016-06-15 | 上海道之科技有限公司 | Manufacturing method for terminal structure of trench IGBT device |
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Application publication date: 20161116 |
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