CN102522363A - Production method of deep groove isolation structure - Google Patents

Production method of deep groove isolation structure Download PDF

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Publication number
CN102522363A
CN102522363A CN2011104357103A CN201110435710A CN102522363A CN 102522363 A CN102522363 A CN 102522363A CN 2011104357103 A CN2011104357103 A CN 2011104357103A CN 201110435710 A CN201110435710 A CN 201110435710A CN 102522363 A CN102522363 A CN 102522363A
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China
Prior art keywords
silicon dioxide
deep groove
silicon nitride
silicon
deep trouth
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CN2011104357103A
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Chinese (zh)
Inventor
遇寒
梅绍宁
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Priority to CN2011104357103A priority Critical patent/CN102522363A/en
Publication of CN102522363A publication Critical patent/CN102522363A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a production method of a deep groove isolation structure. After an epitaxial layer is grown, the method produces the deep groove isolation structure in the following steps: 1) growing silicon dioxide and silicon nitride in a furnace tube, and depositing silicon dioxide on silicon nitride; 2) performing exposure and development, and opening an area where a deep groove is to be etched in a dry etching mode; 3) utilizing silicon dioxide-silicon nitride-silicon dioxide formed by the step 1) to serve as an etching blocking layer, and forming the deep groove in the dry etching mode; 4) performing furnace pipe oxidation again, growing silicon dioxide, and fully oxidizing silicon below silicon nitride of a deep groove isolation area; 5) depositing silicon dioxide and sealing an opening of the deep groove; and 6) carrying out planarization of the surface of the deep groove. The method forms an ultra-thick field oxidation isolation layer by means of a deep groove etching and oxidation technology, and utilizes silicon nitride to serve as the blocking layer of planarization, thereby not only achieving isolation effect, but also greatly improving evenness in the surface and reducing difficulty of rear-end process.

Description

The manufacturing approach of deep groove isolation structure
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of manufacturing approach of deep groove isolation structure.
Background technology
RF LDMOS power device is because good electrology characteristic (for example, high linearity, high-gain; High-output power; High thermal stability, high working voltage, biasing circuit is simple; Input impedance is constant etc.) and with the favorable compatibility of existing CMOS integrated circuit technology, be widely used in wireless communication field at present.
General common STI (deep trench isolation) of employing of traditional LDMOS device and thick oxygen are isolated; This isolation technology can bring inner evenness poor, cause problems such as soup is residual easily, thereby limited the application of RF LDMOS device on the high-speed high frequency device to a certain extent.
Summary of the invention
The technical problem that the present invention will solve provides a kind of manufacturing approach of deep groove isolation structure, and it can improve the inner evenness of RF LDMOS device.
For solving the problems of the technologies described above, the manufacturing approach of deep groove isolation structure of the present invention may further comprise the steps:
1) at the silicon substrate growing epitaxial layers;
2) advance boiler tube grow up successively silicon dioxide and silicon nitride, deposit layer of silicon dioxide on silicon nitride again;
3) exposure is developed, and opens the zone of wanting the etching deep trouth with dry etching method;
4) with step 2) silicon dioxide-silicon nitride-silicon dioxide of forming is as etching barrier layer, and dry etching forms deep trouth;
5) furnace oxidation, growth silicon dioxide all oxidizes away the silicon below the silicon nitride in deep trench isolation zone;
6) deposit silicon dioxide is sealed the deep trouth opening;
7) deep trouth flattening surface.
The present invention is through deep plough groove etched and oxidation technology; Form ultra thick oxidation separator; Increase the barrier layer of silicon nitride simultaneously as flatening process; Thereby not only reached the effect of isolating, also improved the inner evenness of oxide layer greatly, effectively reduced the difficulty of the backend process that brings because of inhomogeneities in difference in height and the face and the hidden danger of device stability aspect.
Description of drawings
Fig. 1 is the manufacturing approach flow chart of embodiment of the invention deep groove isolation structure.
Description of reference numerals is following among the figure:
1: silicon substrate
2: epitaxial loayer
3,5,7,8: oxide layer (silicon dioxide)
4: silicon nitride
6: deep trouth
Embodiment
Understand for technology contents of the present invention, characteristics and effect being had more specifically, combine illustrated execution mode at present, to the manufacturing process flow of the deep groove isolation structure in the RFLDMOS device, details are as follows:
Step 1 is at silicon substrate 1 growing epitaxial layers 2, shown in Fig. 1 (a).
Step 2 is advanced furnace oxidation, and the layer thickness of growing up is the oxide layer 3 of 150~300 Ethylmercurichlorendimides; Advance the grow up silicon nitride 4 of a layer thickness 500~800 Ethylmercurichlorendimides of boiler tube then; Deposit forms the oxide layer 5 that a layer thickness is 2000~5000 Ethylmercurichlorendimides on silicon nitride 4 again, shown in Fig. 1 (b).
Step 3, exposure is developed, and with the method for dry etching, opens the zone of wanting the etching deep trouth, shown in Fig. 1 (c).
Step 4, as etching barrier layer, with the method for dry etching, etching forms trapezoid deep trouth 6, shown in Fig. 1 (d) with oxide layer 3, silicon nitride 4 and oxide layer 5.The angle of this trapezoid deep trouth 6 is 80~89 degree.
Step 5 is advanced furnace oxidation, growth oxide layer 7.Since there is oxide layer 3 below the silicon nitride 4, therefore, through the whole oxidations of SI post after the furnace oxidation that deep trouth is middle, shown in Fig. 1 (e).
Step 6 with chemical gaseous phase depositing process deposit layer of oxide layer 8, is sealed the opening of deep trouth 6, shown in Fig. 1 (f).
Step 7 is utilized flatening process, and with the deep trouth surface rubbing, the large-area deep groove isolation structure of the 5 μ m left and right sides degree of depth that complete is shown in Fig. 1 (g).Because the etching selection ratio of silicon nitride and silicon dioxide is very high, therefore, silicon nitride 4 can be used as the barrier layer; The difference in height of isolated area and active area is remained in 1000 Ethylmercurichlorendimides; Like this, both reach the effect of isolating, improved the inner evenness of oxide layer again; Effectively reduce the difficulty of the backend process that brings by inhomogeneities in difference in height and the face, guaranteed the stability of device.

Claims (8)

1. the manufacturing approach of deep groove isolation structure is characterized in that, may further comprise the steps:
1) at the silicon substrate growing epitaxial layers;
2) advance boiler tube grow up successively silicon dioxide and silicon nitride, deposit layer of silicon dioxide on silicon nitride again;
3) exposure is developed, and opens the zone of wanting the etching deep trouth with dry etching method;
4) with step 2) silicon dioxide-silicon nitride-silicon dioxide of forming is as etching barrier layer, and dry etching forms deep trouth;
5) furnace oxidation, growth silicon dioxide all oxidizes away the silicon below the silicon nitride in deep trench isolation zone;
6) deposit silicon dioxide is sealed the deep trouth opening;
7) deep trouth flattening surface.
2. method according to claim 1 is characterized in that step 2), the thickness of the silicon dioxide that boiler tube is grown up is 150~300 Ethylmercurichlorendimides.
3. method according to claim 1 is characterized in that step 2) thickness of the silicon nitride of growing up is 500~800 Ethylmercurichlorendimides.
4. method according to claim 1 is characterized in that step 2), the thickness of the silicon dioxide that deposit forms is 2000~5000 Ethylmercurichlorendimides.
5. method according to claim 1 is characterized in that, step 4), and said deep trouth is trapezoid.
6. method according to claim 5 is characterized in that, the angle of said trapezoid is 80~88 degree.
7. method according to claim 1 is characterized in that, step 4), the degree of depth of said deep trouth are 5 μ m.
8. method according to claim 1 is characterized in that, chemical gaseous phase depositing process is adopted in the deposit of silicon dioxide.
CN2011104357103A 2011-12-22 2011-12-22 Production method of deep groove isolation structure Pending CN102522363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011104357103A CN102522363A (en) 2011-12-22 2011-12-22 Production method of deep groove isolation structure

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Application Number Priority Date Filing Date Title
CN2011104357103A CN102522363A (en) 2011-12-22 2011-12-22 Production method of deep groove isolation structure

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CN102522363A true CN102522363A (en) 2012-06-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035506A (en) * 2012-08-09 2013-04-10 上海华虹Nec电子有限公司 Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove
CN104576393A (en) * 2013-10-22 2015-04-29 上海华虹宏力半导体制造有限公司 Manufacturing method of RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994201A (en) * 1998-07-14 1999-11-30 United Microelectronics Corp. Method for manufacturing shallow trench isolation regions
US6074930A (en) * 1998-01-07 2000-06-13 Samsung Electronics Co., Ltd. Method for forming a trench isolation structure comprising an interface treatment for trench liner and a subsequent annealing process
US6828212B2 (en) * 2002-10-22 2004-12-07 Atmel Corporation Method of forming shallow trench isolation structure in a semiconductor device
CN101459108A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Method for forming shallow groove isolation structure and etching method for forming shallow groove
CN102117748A (en) * 2009-12-31 2011-07-06 上海华虹Nec电子有限公司 Method for manufacturing collector region and collector region buried layer of bipolar transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074930A (en) * 1998-01-07 2000-06-13 Samsung Electronics Co., Ltd. Method for forming a trench isolation structure comprising an interface treatment for trench liner and a subsequent annealing process
US5994201A (en) * 1998-07-14 1999-11-30 United Microelectronics Corp. Method for manufacturing shallow trench isolation regions
US6828212B2 (en) * 2002-10-22 2004-12-07 Atmel Corporation Method of forming shallow trench isolation structure in a semiconductor device
CN101459108A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Method for forming shallow groove isolation structure and etching method for forming shallow groove
CN102117748A (en) * 2009-12-31 2011-07-06 上海华虹Nec电子有限公司 Method for manufacturing collector region and collector region buried layer of bipolar transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035506A (en) * 2012-08-09 2013-04-10 上海华虹Nec电子有限公司 Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove
CN103035506B (en) * 2012-08-09 2015-10-14 上海华虹宏力半导体制造有限公司 The lithographic method of RFLDMOS spacer medium layer depth groove
CN104576393A (en) * 2013-10-22 2015-04-29 上海华虹宏力半导体制造有限公司 Manufacturing method of RFLDMOS (radio frequency laterally diffused metal oxide semiconductor) device
CN104576393B (en) * 2013-10-22 2017-08-08 上海华虹宏力半导体制造有限公司 The manufacture method of RFLDMOS devices

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Application publication date: 20120627