CN101459108A - Method for forming shallow groove isolation structure and etching method for forming shallow groove - Google Patents
Method for forming shallow groove isolation structure and etching method for forming shallow groove Download PDFInfo
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- CN101459108A CN101459108A CNA2007100944662A CN200710094466A CN101459108A CN 101459108 A CN101459108 A CN 101459108A CN A2007100944662 A CNA2007100944662 A CN A2007100944662A CN 200710094466 A CN200710094466 A CN 200710094466A CN 101459108 A CN101459108 A CN 101459108A
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Abstract
A method for forming a shallow trench isolation structure comprises the steps of providing a semiconductor substrate equipped with a pad oxide layer and a corrosion barrier layer sequentially, forming a mask layer on the corrosion barrier layer, wherein an opening corresponding to the position of a shallow trench is formed on the mask layer, utilizing the mask layer as a mask to etch the corrosion barrier layer along the opening until exposing to the pad oxide layer, utilizing the mask layer and the corrosion barrier layer as masks to etch the pad oxide layer and the semiconductor substrate, thereby forming the shallow trench, depositing a lining oxide layer at the inner side of the shallow trench after removing the mask layer, filling the shallow trench with an insulating oxide layer, and finally removing the corrosion barrier layer and the pad oxide layer to form the shallow trench isolation structure. The invention further provides an etching method for forming the shallow trench. The invention protects the mask layer of the corrosion barrier layer during the process of etching on the corrosion barrier layer, thereby enabling etching gas not to affect the corrosion barrier layer, leading the thickness of the corrosion barrier layer not to be changed, and increasing the isolation effect of the shallow trench isolation structure.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly form the method for fleet plough groove isolation structure and the lithographic method of formation shallow trench.
Background technology
Along with reducing of integrated circuit size, the device of forming circuit must be placed more thick and fast, to adapt to the confined space available on the chip.Because present research is devoted to increase the density of active device on the unit are of Semiconductor substrate, becomes more important so the effective insulation between circuit is isolated.The method that forms area of isolation in the prior art mainly contains carrying out local oxide isolation (LOCOS) technology or shallow trench isolation from (STI) technology.LOCOS technology is at wafer surface deposit one deck silicon nitride, and then carries out etching, and the part recessed region is carried out the oxidation growth silica, and active device generates in the determined zone of silicon nitride.For isolation technology, the effective carrying out local oxide isolation of LOCOS technology in circuit still has problems, one of them problem is exactly " beak " phenomenon in the silicon nitride marginal growth, and this is owing to the hot expansibility difference between silicon nitride in the process of oxidation and the silicon causes.This " beak " taken actual space, increased the volume of circuit, and in oxidizing process, wafer produced stress rupture.Therefore LOCOS technology only is applicable to the design and the manufacturing of large-size device.
Shallow trench isolation has multinomial processing procedure and electrical isolation advantage from (STI) technology, comprises reducing the integrated level that the area that takies silicon wafer surface increases device simultaneously, keeps surface flatness and less channel width erosion etc.Therefore, the following element of present 0.18 μ m for example the active area isolation layer of MOS circuit adopt shallow ditch groove separation process to make mostly.
Fig. 1 to Fig. 4 is the generalized section that forms fleet plough groove isolation structure according to conventional method.At first, with reference to figure 1, form pad oxide 102 with thermal oxidation method on Semiconductor substrate 100, the material of described pad oxide 102 can be silica; Form corrosion barrier layer 104 with chemical vapour deposition technique on pad oxide 102, the material of described corrosion barrier layer 104 can be silicon nitride; On corrosion barrier layer 104, form photoresist layer 108 with spin-coating method, through exposure imaging technology, definition shallow trench figure 109.
As shown in Figure 2, serve as the cover curtain with photoresist layer 108,, form and follow-up shallow trench position corresponding opening to exposing pad oxide 102 with dry etching method etching corrosion barrier layer 104; Ashing method is removed photoresist layer 108, removes residual photoresist layer 108 with the wet etching method; Then, serve as the cover curtain with corrosion barrier layer 104, along opening,, form shallow trench 110 with dry etching method etching pad oxide 102 and Semiconductor substrate 100.
Then, with reference to figure 3, form lining oxide layer 112 with thermal oxidation method at the bottom and the sidewall of shallow trench 110, the material of described lining oxide layer 112 is generally silica; On corrosion barrier layer 104, form insulating oxide 114 by usefulness high density plasma CVD method (HDPCVD), and insulating oxide 114 is filled full shallow trench 110; Insulating oxide 114 is carried out planarization, as adopting the insulating oxide 114 on the CMP (Chemical Mechanical Polishing) process removing corrosion barrier layer 104.
As shown in Figure 4, remove corrosion barrier layer 104 and pad oxide 102, form the fleet plough groove isolation structure 115 that is made of lining oxide layer in the shallow trench 112 and insulating oxide 114, the technology of removing corrosion barrier layer 104 and pad oxide 102 generally adopts wet etching.
Can also find more information relevant in Chinese patent application 03825402, form fleet plough groove isolation structure with technique scheme.
Prior art with the corrosion barrier layer is being the cover curtain, with dry etching method etching pad oxide and Semiconductor substrate, form in the shallow trench process, certain corrasion can take place to corrosion barrier layer in etching gas equally, the thickness of corrosion barrier layer is changed, and the thickness of corrosion barrier layer directly influences the degree of depth of shallow trench, thereby the isolation effect of fleet plough groove isolation structure is reduced.
Summary of the invention
The problem that the present invention solves provides a kind of lithographic method that forms the method for fleet plough groove isolation structure and form shallow trench, prevents from owing to the varied in thickness of corrosion barrier layer the shallow trench degree of depth to be affected, and improves the isolation effect of fleet plough groove isolation structure.
For addressing the above problem, the invention provides a kind of method that forms fleet plough groove isolation structure, comprising: the Semiconductor substrate that has pad oxide and corrosion barrier layer successively is provided; On corrosion barrier layer, form mask layer, be formed with on the described mask layer and shallow trench position corresponding opening; Is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide; With mask layer and corrosion barrier layer is the cover curtain, and etching pad oxide and Semiconductor substrate form shallow trench; After removing mask layer, at the inboard deposition of shallow trench lining oxide layer, and with the full shallow trench of insulating oxide filling; Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure.
Optionally, the method for formation mask layer is a chemical vapour deposition technique.Described mask layer is the bottom anti-reflective material.The thickness of described mask layer is 200 dusts～400 dusts.
Optionally, further comprise at formation opening on the mask layer: on mask layer, form photoresist layer, the shallow trench figure is arranged on the described photoresist layer; With the photoresist layer is the cover curtain, along shallow trench pattern etching mask layer, forms and shallow trench position corresponding opening.
Optionally, further comprise at formation opening on the mask layer: on mask layer, form barrier layer and photoresist layer successively, the shallow trench figure is arranged on the described photoresist layer; With the photoresist layer is the cover curtain, along shallow trench pattern etching barrier layer; After removing photoresist layer, be the cover curtain with the barrier layer, the etch mask layer forms and shallow trench position corresponding opening.
Optionally, the technology on described formation barrier layer is chemical vapour deposition technique.The thickness on described barrier layer is 150 dusts～450 dusts.The material on described barrier layer is a cryogenic oxidation silicon.The formation condition of described cryogenic oxidation silicon is 200 ℃～300 ℃.
Optionally, the technology of etch mask layer is the dry etching method.
The invention provides a kind of lithographic method that forms shallow trench, comprising: the Semiconductor substrate that has pad oxide and corrosion barrier layer successively is provided; On corrosion barrier layer, form mask layer, be formed with on the described mask layer and shallow trench position corresponding opening; Is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide; With mask layer and corrosion barrier layer is the cover curtain, and etching pad oxide and Semiconductor substrate form shallow trench.
Compared with prior art; such scheme has the following advantages: the mask layer that forms protection corrosion barrier layer in the etching process on corrosion barrier layer; etching gas can not exerted an influence to corrosion barrier layer; the thickness of corrosion barrier layer does not change yet, thereby the isolation effect of fleet plough groove isolation structure is improved.
Description of drawings
Fig. 1 to Fig. 4 is the existing schematic diagram that forms fleet plough groove isolation structure;
Fig. 5 is the embodiment flow chart that the present invention forms fleet plough groove isolation structure;
Fig. 6 is the embodiment flow chart that etching of the present invention forms shallow trench;
Fig. 7 to Figure 13 is the embodiment schematic diagram that the present invention forms fleet plough groove isolation structure.
Embodiment
The present invention forms the mask layer of protection corrosion barrier layer in the etching process on corrosion barrier layer, etching gas can not exerted an influence to corrosion barrier layer, and the thickness of corrosion barrier layer does not change yet, thereby the isolation effect of fleet plough groove isolation structure is improved.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 is the embodiment flow chart that the present invention forms fleet plough groove isolation structure.As shown in Figure 5, execution in step S101 provides the Semiconductor substrate that has pad oxide and corrosion barrier layer successively.
The method that forms pad oxide can be thermal oxidation method, and the material of pad oxide can be silica.
The method that forms corrosion barrier layer can be chemical vapour deposition technique, and the material of corrosion barrier layer can be silicon nitride, act as in subsequent etching to form in the shallow trench process influence that pad oxide that protection is following and Semiconductor substrate are avoided etching gas.
Execution in step S102 forms mask layer on corrosion barrier layer, be formed with on the described mask layer and shallow trench position corresponding opening.
The method that forms mask layer can be chemical vapour deposition technique, and described mask layer can be the bottom anti-reflective material, and the thickness of mask layer protection corrosion barrier layer does not change in etching process.
Execution in step S103 is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide.
The technology of etching corrosion barrier layer can be the dry etching method.
Execution in step S104 serves as the cover curtain with mask layer and corrosion barrier layer, and etching pad oxide and Semiconductor substrate form shallow trench.
The technology of etching pad oxide and Semiconductor substrate can be the dry etching method.
Execution in step S105, behind the removal mask layer, at the inboard deposition of shallow trench lining oxide layer, and with the full shallow trench of insulating oxide filling.
The method of removing mask layer can be the oxygen gas plasma etching.
Execution in step S106 removes corrosion barrier layer and pad oxide, forms fleet plough groove isolation structure.
The method of removing corrosion barrier layer and pad oxide can be the wet etching method.
Fig. 6 is the embodiment flow chart that etching of the present invention forms shallow trench.As shown in Figure 6, execution in step S201 provides the Semiconductor substrate that has pad oxide and corrosion barrier layer successively; Execution in step S202 forms mask layer on corrosion barrier layer, be formed with on the described mask layer and shallow trench position corresponding opening; Execution in step S203 is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide; Execution in step S204 serves as the cover curtain with mask layer and corrosion barrier layer, and etching pad oxide and Semiconductor substrate form shallow trench.
Fig. 7 to Figure 13 is the embodiment schematic diagram that the present invention forms fleet plough groove isolation structure.As shown in Figure 7, form pad oxide 202 with thermal oxidation method on Semiconductor substrate 200, the material of described pad oxide 202 can be a silica.Form corrosion barrier layer 204 with chemical vapour deposition technique on pad oxide 202, the material of described corrosion barrier layer 204 is silicon nitride or silicon oxynitride etc.On corrosion barrier layer 204, form mask layer 206 with chemical gaseous phase depositing process, described mask layer 206 can be the bottom anti-reflective material, be used for avoiding the influence of etching gas, guarantee that the thickness of corrosion barrier layer 204 is constant at subsequent etching process protection corrosion barrier layer 204; And the thickness of mask layer 206 determines according to different process, can cover corrosion barrier layer 204 for good.Form barrier layer 208 with chemical gaseous phase depositing process on mask layer 206, be used for as the barrier layer, protection mask layer 206 is damaged in photoetching process, and the material on described barrier layer 208 is a cryogenic oxidation silicon etc.; On barrier layer 208, form photoresist layer 212 with spin-coating method, through exposure imaging technology, definition shallow trench figure 213.
Except that present embodiment, if the material of mask layer 206 both can be protected corrosion barrier layer 204 in etching process, can in photoetching process, avoid again damaging, on mask layer 206, do not need to add again one deck barrier layer 208 so.
In the present embodiment, the thickness of described mask layer 206 is 200 dusts～400 dusts, and concrete thickness is 200 dusts, 220 dusts, 240 dusts, 260 dusts, 280 dusts, 300 dusts, 320 dusts, 340 dusts, 360 dusts, 380 dusts or 400 dusts etc. for example.
In the present embodiment, the thickness on described barrier layer 208 is 150 dusts～450 dusts, and concrete thickness is 150 dusts, 200 dusts, 250 dusts, 300 dusts, 350 dusts or 400 dusts etc. for example.
In the present embodiment, when the material on described barrier layer 208 was cryogenic oxidation silicon, the temperature that forms cryogenic oxidation silicon was 200 ℃～300 ℃, for example 200 ℃, 220 ℃, 240 ℃, 260 ℃, 280 ℃ of actual temps or 300 ℃ etc.
As shown in Figure 8, serve as the cover curtain with photoresist layer 212, elder generation to exposing mask layer 206, forms first opening 214 corresponding with follow-up shallow trench position with dry etching method etching barrier layer 208 in barrier layer 208.
In the present embodiment, the gas of etching barrier layer 208 can be CHF
3And O
2Combination, wherein, CHF
3Flow be 20sccm (cubic centimetre/minute)～100sccm, concrete flow is 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example; O
2Flow be 10sccm～100sccm, concrete flow is 10sccm, 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example.
As shown in Figure 9, remove photoresist layer 212 with ashing method; Then, remove residual photoresist layer 212 with the wet etching method; With barrier layer 208 is the cover curtain, along first opening 214, to exposing corrosion barrier layer 204, forms second opening 215 with dry etching method etch mask layer 206 in corrosion barrier layer 204.
In the present embodiment, the used gas of etch mask layer can be CF
4And O
2Combination, wherein, CF
4Flow be 50sccm～200sccm, concrete flow is 50sccm, 80sccm, 100sccm, 120sccm, 140sccm, 150sccm, 180sccm or 200sccm etc. for example; O
2Flow be 10sccm～100sccm, concrete flow is 10sccm, 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example.
As shown in figure 10, remove barrier layer 208; With mask layer 206 is the cover curtain, along second opening 215, to exposing pad oxide 202, form the 3rd opening 216 with dry etching method etching corrosion barrier layer 204 in corrosion barrier layer 204, the method for described dry etching method etching corrosion barrier layer 204 is for well known to a person skilled in the art technology.
As shown in figure 11, with mask layer 206 and corrosion barrier layer 204 is the cover curtain, along the 3rd opening 216, with dry etching method etching pad oxide 202 and Semiconductor substrate 200, form shallow trench 217, the method for described etching pad oxide 202 and Semiconductor substrate 200 is a technology as well known to those skilled in the art.
Then, with reference to Figure 12, remove mask layer 206; Form lining oxide layer 218 with thermal oxidation method at the bottom and the sidewall of shallow trench 217, the material of described lining oxide layer 218 is generally silica; Insulating oxide 220 is filled full shallow trench 217, and insulating oxide 220 covering corrosion barrier layers 204, the material of described insulating oxide 220 can be a silica etc.The technology of deposition insulating oxide 220 can adopt chemical vapour deposition technique in shallow trench 217 and on the corrosion barrier layer 204, and relatively the technical scheme of You Huaing is for example with oxygen (O
2) and monosilane (SiH
4) be reacting gas, with high density plasma chemical vapor deposition method (HDPCVD), deposition one deck is the insulating oxide 220 of material with the silica in shallow trench 217 and on the surface of corrosion barrier layer 204.
Insulating oxide 220 is carried out planarization, and described flatening process is chemical mechanical polishing method for example, until exposing corrosion barrier layer 204; It is a flat structures that described flatening process also can adopt chemical mechanical polishing method to be polished to insulating oxide 220 surfaces, adopts etching technics to be etched to then and exposes corrosion barrier layer 204 to the open air.
In the present embodiment, the method for removing mask layer 206 can be the wet etching method.
As shown in figure 13, remove corrosion barrier layer 204 and pad oxide 202, form the fleet plough groove isolation structure 222 that constitutes by lining oxide layer in the shallow trench 218 and insulating oxide 220.The technology of removing corrosion barrier layer 204 for example adopts the wet etching method that contains the pentavalent hot phosphoric acid solution; The technology of removing pad oxide 202 generally also adopts the wet etching method, for example adopts hydrofluoric acid solution to carry out etching.
Continuation to Figure 11, provides a kind of embodiment that forms the lithographic method of shallow trench with reference to figure 7, as shown in Figure 7, forms pad oxide 202 with thermal oxidation method on Semiconductor substrate 200, and the material of described pad oxide 202 can be a silica.Form corrosion barrier layer 204 with chemical vapour deposition technique on pad oxide 202, the material of described corrosion barrier layer 204 is silicon nitride or silicon oxynitride etc.On corrosion barrier layer 204, form mask layer 206 with chemical gaseous phase depositing process, described mask layer 206 can be the bottom anti-reflective material, be used for avoiding the influence of etching gas, guarantee that the thickness of corrosion barrier layer 204 is constant at subsequent etching process protection corrosion barrier layer 204; And the thickness of mask layer 206 determines according to different process, can cover corrosion barrier layer 204 for good.Form barrier layer 208 with chemical gaseous phase depositing process on mask layer 206, be used for as the barrier layer, protection mask layer 206 is damaged in photoetching process, and the material on described barrier layer 208 is a cryogenic oxidation silicon etc.; On barrier layer 208, form photoresist layer 212 with spin-coating method, through exposure imaging technology, definition shallow trench figure 213.
Except that present embodiment,, on mask layer 206, do not need to add again one deck barrier layer 208 so if mask layer 206, can be avoided the material that damages again for both protecting corrosion barrier layer 204 in etching process in photoetching process.
As shown in Figure 8, serve as the cover curtain with photoresist layer 212, elder generation to exposing mask layer 206, forms first opening 214 corresponding with follow-up shallow trench position with dry etching method etching barrier layer 208 in barrier layer 208.
In the present embodiment, the gas of etching barrier layer 208 can be CHF
3And O
2Combination, wherein, CHF
3Flow be 20sccm (cubic centimetre/minute)～100sccm, concrete flow is 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example; O
2Flow be 10sccm～100sccm, concrete flow is 10sccm, 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example.
As shown in Figure 9, remove photoresist layer 212 with ashing method; Then, remove residual photoresist layer 212 with the wet etching method; With barrier layer 208 is the cover curtain, along first opening 214, to exposing corrosion barrier layer 204, forms second opening 215 with dry etching method etch mask layer 206 in corrosion barrier layer 204.
In the present embodiment, the used gas of etch mask layer can CF
4And O
2Combination, wherein, CF
4Flow be 50sccm～200sccm, concrete flow is 50sccm, 80sccm, 100sccm, 120sccm, 140sccm, 150sccm, 180sccm or 200sccm etc. for example; O
2Flow be 10sccm～100sccm, concrete flow is 10sccm, 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm or 100sccm etc. for example.
As shown in figure 10, remove barrier layer 208; With mask layer 206 is the cover curtain, along second opening 215, to exposing pad oxide 202, form the 3rd opening 216 with dry etching method etching corrosion barrier layer 204 in corrosion barrier layer 204, the method for described dry etching method etching corrosion barrier layer 204 is for well known to a person skilled in the art technology.
As shown in figure 11, with mask layer 206 and corrosion barrier layer 204 is the cover curtain, along the 3rd opening 216, with dry etching method etching pad oxide 202 and Semiconductor substrate 200, form shallow trench 217, the method for described etching pad oxide 202 and Semiconductor substrate 200 is a technology as well known to those skilled in the art.
Except that present embodiment, if on mask layer 206, there is not barrier layer 208, then etching process is: with photoresist layer 212 is the cover curtain, and elder generation, forms and follow-up shallow trench position corresponding opening in mask layer 206 to exposing corrosion barrier layer 204 with dry etching method etch mask layer 206; After removing photoresist layer 212, serve as cover act with mask layer 206, along opening etching corrosion barrier layer 204 to exposing pad oxide 202; With mask layer 206 and corrosion barrier layer 204 is the cover curtain, and etching pad oxide 202 and Semiconductor substrate 200 form shallow trench 217.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. a method that forms fleet plough groove isolation structure is characterized in that, comprising:
The Semiconductor substrate that has pad oxide and corrosion barrier layer successively is provided;
On corrosion barrier layer, form mask layer, be formed with on the described mask layer and shallow trench position corresponding opening;
Is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide;
With mask layer and corrosion barrier layer is the cover curtain, and etching pad oxide and Semiconductor substrate form shallow trench;
After removing mask layer, at the inboard deposition of shallow trench lining oxide layer, and with the full shallow trench of insulating oxide filling;
Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure.
2. according to the method for the described formation fleet plough groove isolation structure of claim 1, it is characterized in that the method that forms mask layer is a chemical vapour deposition technique.
3. according to the method for claim 1 or 2 described formation fleet plough groove isolation structures, it is characterized in that described mask layer is the bottom anti-reflective material.
4. according to the method for the described formation fleet plough groove isolation structure of claim 3, it is characterized in that the thickness of described mask layer is 200 dusts～400 dusts.
5. according to the method for the described formation fleet plough groove isolation structure of claim 1, it is characterized in that, on mask layer, form opening and further comprise:
On mask layer, form photoresist layer, the shallow trench figure is arranged on the described photoresist layer;
With the photoresist layer is the cover curtain, along shallow trench pattern etching mask layer, forms and shallow trench position corresponding opening.
6. according to the method for the described formation fleet plough groove isolation structure of claim 1, it is characterized in that, on mask layer, form opening and further comprise:
On mask layer, form barrier layer and photoresist layer successively, the shallow trench figure is arranged on the described photoresist layer;
With the photoresist layer is the cover curtain, along shallow trench pattern etching barrier layer;
After removing photoresist layer, be the cover curtain with the barrier layer, the etch mask layer forms and shallow trench position corresponding opening.
7. according to the method for the described formation fleet plough groove isolation structure of claim 6, it is characterized in that the technology on described formation barrier layer is chemical vapour deposition technique.
8. according to the method for claim 6 or 7 described formation fleet plough groove isolation structures, it is characterized in that the thickness on described barrier layer is 150 dusts～450 dusts.
9. according to the method for claim 6 or 7 described formation fleet plough groove isolation structures, it is characterized in that the material on described barrier layer is a cryogenic oxidation silicon.
10. according to the method for the described formation fleet plough groove isolation structure of claim 9, it is characterized in that the formation condition of described cryogenic oxidation silicon is 200 ℃～300 ℃.
11. the method according to claim 5 or 6 described formation fleet plough groove isolation structures is characterized in that, the technology of etch mask layer is the dry etching method.
12. a lithographic method that forms shallow trench is characterized in that, comprising:
The Semiconductor substrate that has pad oxide and corrosion barrier layer successively is provided;
On corrosion barrier layer, form mask layer, be formed with on the described mask layer and shallow trench position corresponding opening;
Is the cover curtain with the mask layer, along opening etching corrosion barrier layer to exposing pad oxide;
With mask layer and corrosion barrier layer is the cover curtain, and etching pad oxide and Semiconductor substrate form shallow trench.
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| CN102522363A (en) * | 2011-12-22 | 2012-06-27 | 上海华虹Nec电子有限公司 | Production method of deep groove isolation structure |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103247565A (en) * | 2012-02-10 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation structure and manufacturing method thereof |
| CN108666208A (en) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109950148A (en) * | 2017-12-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110911343A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method thereof |
| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
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Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6821883B1 (en) * | 1998-11-25 | 2004-11-23 | Advanced Micro Devices, Inc. | Shallow trench isolation using antireflection layer |
| US6890859B1 (en) * | 2001-08-10 | 2005-05-10 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby |
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| CN102522363A (en) * | 2011-12-22 | 2012-06-27 | 上海华虹Nec电子有限公司 | Production method of deep groove isolation structure |
| CN103247565A (en) * | 2012-02-10 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation structure and manufacturing method thereof |
| CN103247565B (en) * | 2012-02-10 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of fleet plough groove isolation structure and preparation method thereof |
| CN103035514A (en) * | 2012-05-16 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103035514B (en) * | 2012-05-16 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | Manufacture method for forming thick silicon oxide isolation layer in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN108666208A (en) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109950148A (en) * | 2017-12-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110911343A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method thereof |
| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
| CN113140500B (en) * | 2021-04-19 | 2023-08-22 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
| CN116581085A (en) * | 2023-07-11 | 2023-08-11 | 江苏鲁汶仪器股份有限公司 | Preparation method of shallow trench isolation structure |
| CN116581085B (en) * | 2023-07-11 | 2023-09-29 | 江苏鲁汶仪器股份有限公司 | Preparation method of shallow trench isolation structure |
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