CN105702736B - Shield grid-deep trench MOSFET shielding gate oxide and forming method thereof - Google Patents

Shield grid-deep trench MOSFET shielding gate oxide and forming method thereof Download PDF

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CN105702736B
CN105702736B CN201610064114.1A CN201610064114A CN105702736B CN 105702736 B CN105702736 B CN 105702736B CN 201610064114 A CN201610064114 A CN 201610064114A CN 105702736 B CN105702736 B CN 105702736B
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oxide
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oxide layer
nitration case
gate oxide
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CN105702736A (en
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陈正嵘
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

The invention discloses a kind of shield grid-deep trench MOSFET shielding gate oxides and forming method thereof, comprising: step 1, etching is formed with groove on epitaxial layer, and the bottom surface and sidewall surfaces using thermal oxide growth technique in groove form the first oxide layer；Step 2 forms nitration case on the surface of the first oxide layer；Step 3 forms depositing polysilicon layer on the surface of nitration case using polycrystalline silicon deposition process；Step 4 carries out thermal oxide, depositing polysilicon layer is fully oxidized to the second oxide layer, shielding gate oxide is collectively formed in first oxide layer, nitration case and the second oxide layer.The present invention pass through the depositing polysilicon on nitration case and to polysilicon carry out thermal oxide by way of instead of it is existing on nitration case directly by way of SACVD deposited oxide layer, it can not only guarantee the thickness of the shielding gate oxide between shield grid and trenched side-wall and channel bottom for being isolated, and simplify process conditions, production cost is reduced, production capacity is improved.

Description

Shield grid-deep trench MOSFET shielding gate oxide and forming method thereof
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process area, in particular to a kind of shield grid-deep trench MOSFET In be located at the shielding gate oxide of trenched side-wall, further relate to the screen for being located at trenched side-wall in a kind of shield grid-deep trench MOSFET Cover the forming method of gate oxide.
Background technique
As shown in Figure 1, being the existing trench gate with shield grid (Shield Gate Trench, abbreviation SGT) structure The structural schematic diagram of MOSFET is illustrated by taking N-type device as an example, the list of the trench gate mosfet with shielded gate structures Meta structure includes:
N-type silicon epitaxy layer 101, is formed on silicon substrate, and silicon substrate is heavy doping and is overleaf formed with drain electrode, silicon epitaxy Layer 101 is used to form drift region to be lightly doped；
P-well 102 is formed in the surface of silicon epitaxy layer 101；
Groove passes through p-well 102 and enters in silicon epitaxy layer 101, there is polysilicon gate 103a and polysilicon shield grid in groove The isolation of the sidewall surfaces of 104a, polysilicon gate 103a and groove has gate oxide (gate oxide) 105a, polysilicon gate 103a Isolation has polysilicon interlevel oxide layer (inter poly oxide) 106a, polysilicon shield between polysilicon shield grid 104a The sidewall surfaces and bottom of grid 104a and groove, which are directly isolated, shielding gate oxide (shielding oxide) 107a；
Source region 108 is formed in p-well 102, and polysilicon gate 103a covers source region 108 and p-well 102, polysilicon gate from side The depth of 103a is greater than the junction depth of p-well 102, and is used to form connection by the surface for the p-well 102 that the side polysilicon gate 103a covers The channel of source region 108 and bottom silicon epitaxy layer 101；
Source contact openings 109 pass through source region 108 and simultaneously and source region 108 and p-well 102 contact, shield grid contact hole 110a passes through oxide layer and polysilicon shield grid 104a contact, source contact openings 109 and screen at the top of polysilicon shield grid 104a It covers in grid contact hole 110a and is filled with metal；
It is formed with contact hole in interlayer film 111 and draws source electrode and grid respectively, wherein source contact openings 109 and shield grid connect Contact hole 110a is all connected to source electrode.
It is illustrated by taking the trench gate structure comprising middle pressure SGT (80V~200V) as an example, trench depth is generally 4~6 Microns, the thickness for shielding gate oxide form shielding in the 5000 Izods right side, this trench gate structure with shield grid The method of gate oxide includes the following steps:
Step 1 forms groove 2 on epitaxial layer 1, and as shown in Figure 2 A, the etching depth of groove 2 is 4 microns~6 microns；
Step 2, thermal oxide formed oxide layer 3, as shown in Figure 2 B, the oxide layer 3 with a thickness of 4000 angstroms~6000 angstroms；
Step 3, groove 2 is filled up completely by the first polysilicon layer 4 of deposit, and carries out dry back quarter to the first polysilicon layer 4 It is flushed to silicon face holding, as shown in Figure 2 C；
Step 4 is etched to inside groove 2 first polysilicon layer 4 for the second time, as shown in Figure 2 D, is located in groove 2 The first polysilicon layer 4 form shield grid；
Step 5 carries out wet etching, by the oxide layer 3 of silicon face and is formed in trenched side-wall and is located on shield grid The oxide layer 3 of side etches completely, and as shown in Figure 2 E, the region etched in groove is used to form polysilicon gate, and wherein width is 2 micro- Rice, depth are 1.5 microns；
Groove is fully filled with by step 6 by HDP (high-density plasma)+SACVD (sub-atmospheric pressure chemical vapor deposition) Oxide layer, as shown in Figure 2 F, since the width and depth of groove are larger, so in order to ensure subsequent CMP (chemically mechanical polishing) Technology stability, need pass through HDP fill 15500 angstroms and by SACVD filling 10000 angstroms could groove be filled up and be guaranteed Enough thickness is to carry out subsequent CMP processing procedure；
Step 7 carries out CMP (chemically mechanical polishing) processing procedure and polishes the oxide layer on surface, makes the oxidation thickness of silicon face Degree is maintained at 2000 angstroms~3000 angstroms, as shown in Figure 2 G；
Step 8 carries out wet process Hui Kezhi certain depth to oxide layer, shields the oxide layer above gate polysilicon and forms polycrystalline Silicon interlevel oxide layer 5, the oxide layer between shield grid and trenched side-wall and channel bottom forms shielding gate oxide 3, such as Fig. 2 H institute Show；
Step 9 forms gate oxide by thermal oxide；
Step 10, deposit the second polysilicon, groove is filled up completely, and to the second polysilicon carry out dry back carve to silicon Surface keeps flushing, and forms polysilicon gate.
Since the cost of HDP technique is very high, therefore polysilicon interlevel oxide layer is formed by thermal oxide mostly at present, wherein one Kind mode is that gate oxide 6 and polysilicon interlevel oxide layer 5 aoxidize completion together, because of the thickness of polysilicon interlevel oxide layer 5 It is required that at 2000 angstroms or more, so need to form the oxidizing condition that oxide thickness differs greatly using in polysilicon and silicon face, Guarantee the ratio between the oxide thickness of the top of the first polysilicon layer 4 and oxide thickness of silicon face of trenched side-wall in 3:1 or more, As shown in figure 3, and this oxidizing condition is limited by existing patent and is protected.
Other than the method that above-mentioned gate oxide aoxidizes together with polysilicon interlevel oxide layer, ordinary hot is used in order to subsequent Oxidation forms polysilicon interlevel oxide layer to avoid the patent protection oxidizing condition of the use of device shown in Fig. 3, and there are also another Method as shown in Figure 4 A, is then being shielded that is, by depositing a nitration case 7 in the oxide layer 3 for forming shielding gate oxide Polysilicon interlevel oxide layer 5 is formed when covering the oxidation of grid can thus pass through common thermal oxidizing conditions oxygen as shown in Figure 4 B Change forms sufficiently thick polysilicon interlevel oxide layer 5.The overall thickness that oxide layer 3 and nitration case 7 add up is about the 5000 Izods right side, Wherein 3500 angstroms~4000 angstroms of the thickness of oxide layer 3,1000 angstroms~1500 angstroms of the thickness of nitration case 7.Pass through oxygen on the polysilicon After change forms polysilicon interlevel oxide layer 5, wet etching is carried out to nitration case 7 and oxide layer 3 respectively, because wet etching is each The property of the item same sex, nitration case 7 and oxide layer 3 will form the pattern of oblique triangle after etching, influence device property, such as scheme Shown in 4C, Fig. 4 D.
So it is further, first pass through the gate oxide that first step thermal oxidation technology directly forms required thickness in the trench 6, nitration case 7 is then deposited on gate oxide 6 again may be implemented 6 one-pass molding of gate oxide, so as shown in Figure 5A in this way The overall thickness of shielding gate oxide required for being supplied in such a way that SACVD is deposited afterwards, it is desirable that on the 5000 Izods right side.And The sum of thickness and the thickness of nitration case 7 of the gate oxide 6 that preceding method is formed are about 1000 angstroms~1500 angstroms, and oxidation film is straight It connects and is used as gate oxide, it is subsequent without using wet etching.The thickness of nitride film is also relatively thin, is formed after subsequent wet etching Chamfering is smaller.Final pattern is more excellent, and as shown in Figure 5 B, general at present is the oxidation that 9000 angstroms are deposited using SACVD Layer 8, this high process cost and needs to use specific condition, therefore yield is very low.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of shield grid-deep trench MOSFET shielding gate oxide and its Forming method, process conditions are simple, it is easy to accomplish, and production cost can be reduced, improve production efficiency.
In order to solve the above technical problems, shield grid provided by the invention-deep trench MOSFET shielding gate oxide, including First oxide layer, nitration case and the second oxide layer, first oxide layer are formed in the bottom surface and sidewall surfaces of groove, institute The surface that nitration case is formed in first oxide layer is stated, second oxide layer is formed in the surface of the nitration case, and institute The second oxide layer is stated by polycrystalline silicon deposit and thermal oxide forms.
A further improvement is that the polysilicon with a thickness of 1000 angstroms~2500 angstroms.
A further improvement is that the depth of the groove is 4 microns~6 microns, Sidewall angles are 86.5 °~88.5 °.
A further improvement is that the thickness of first oxide layer is identical as the thickness of gate oxide in MOSFET, it is described Nitration case with a thickness of 500 angstroms~1500 angstroms.
In order to solve the above technical problems, trenched side-wall forms shielding in shield grid provided by the invention-deep trench MOSFET The method of gate oxide, includes the following steps:
Step 1, etching is formed with groove on epitaxial layer, using thermal oxide growth technique in the bottom surface of the groove and Sidewall surfaces form the first oxide layer；
Step 2 forms nitration case on the surface of first oxide layer；
Step 3 forms depositing polysilicon layer on the surface of the nitration case using polycrystalline silicon deposition process；
Step 4 carries out thermal oxide, and the depositing polysilicon layer is fully oxidized to the second oxide layer, first oxidation Shielding gate oxide is collectively formed in layer, nitration case and the second oxide layer.
A further improvement is that the depositing polysilicon layer with a thickness of 1000 angstroms~2500 angstroms.
A further improvement is that the depth of the groove is 4 microns~6 microns, Sidewall angles are 86.5 °~88.5 °.
A further improvement is that the thickness of first oxide layer is identical as the thickness of gate oxide in MOSFET, it is described Nitration case with a thickness of 500 angstroms~1500 angstroms.
The present invention has the method for forming shielding gate oxide in trenched side-wall in shield grid-deep trench MOSFET, passes through On nitration case depositing polysilicon and to polysilicon carry out thermal oxide mode to form the shielding gate oxidation for meeting thickness requirement Layer, instead of it is existing on nitration case directly by way of SACVD deposited oxide layer, can not only guarantee shield grid and ditch Thickness between groove sidewall and channel bottom for the shielding gate oxide of isolation, and process conditions are simplified, reduce life Cost is produced, production capacity is improved.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the existing trench gate mosfet with shielded gate structures；
Fig. 2A to Fig. 2 H is that existing formed in the trench with shield grid-deep trench MOSFET shields gate oxide Device architecture schematic diagram in each step；
Fig. 3 is the existing device architecture signal that polysilicon interlevel oxide layer and gate oxide are formed using a thermal oxide Figure；
Fig. 4 A to Fig. 4 D is the existing device that polysilicon interlevel oxide layer is formed using deposit nitration case+common thermal oxide Structural schematic diagram；
Fig. 5 A to Fig. 5 B is that existing formed using gate oxide one-pass molding+nitration case deposit+deposited oxide layer is shielded The device architecture schematic diagram of gate oxide；
Fig. 6 A to Fig. 6 B is the device architecture schematic diagram that the present invention forms shielding gate oxide；
Fig. 6 C to Fig. 6 G is the device architecture schematic diagram that the present invention forms shield grid and each step of polysilicon gate；
Fig. 7 is the method flow diagram that the present invention forms shielding gate oxide.
Specific embodiment
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
Shield grid provided by the invention-deep trench MOSFET shielding gate oxide, as shown in Figure 6B, including the first oxidation Layer (i.e. the gate oxide 6 of MOSFET), nitration case 7 and the second oxide layer 8, first oxide layer are formed in the bottom table of groove Face and sidewall surfaces, the nitration case 7 are formed in the surface of first oxide layer, and second oxide layer 8 is formed in described The surface of nitration case 7, and second oxide layer 8 is formed by polycrystalline silicon deposit and thermal oxide.By first oxygen in the present invention Change layer (i.e. gate oxide 6), ONO layer that the nitration case 7 and second oxide layer 8 superposition are formed in MOSFET as shielding The shielding gate oxide (Shielding Oxide) being directly isolated between grid and the bottom surface of groove and sidewall surfaces.Preferably Selection be, the polysilicon with a thickness of 1000 angstroms~2500 angstroms, grid oxygen in the thickness and MOSFET of first oxide layer The thickness for changing layer is identical, first oxide layer with a thickness of 400 angstroms~1000 angstroms, the nitration case 7 with a thickness of 500 angstroms~ 1000 angstroms.
The groove is formed in epitaxial layer such as silicon epitaxy layer 1, and the depth for being preferably selected as groove is 4 microns~6 micro- Rice, Sidewall angles are 86.5 °~88.5 °.
The forming method of the shielding gate oxide of trenched side-wall in above-mentioned shield grid-deep trench MOSFET, as shown in fig. 7, Include the following steps:
Step 1, etching is formed with groove on epitaxial layer 1, using thermal oxide growth technique the groove bottom surface The first oxide layer is formed with sidewall surfaces；
It is preferably selected as, epitaxial layer 1 is silicon epitaxy layer, and the depth of groove is 4 microns~6 microns, and Sidewall angles are 86.5 ° ~88.5 °, the thickness of the first oxide layer is identical as the thickness of gate oxide 6 in MOSFET, first oxide layer with a thickness of 400 angstroms~1000 angstroms；
Step 2 forms nitration case 7 on the surface of first oxide layer (i.e. gate oxide 6)；
Preferably be selected as, the nitration case 7 with a thickness of 500 angstroms~1500 angstroms；
Step 3 forms depositing polysilicon layer 9 on the surface of the nitration case 7 using polycrystalline silicon deposition process, such as Fig. 6 A institute Show；
Preferably be selected as, the depositing polysilicon layer 9 with a thickness of 1000 angstroms~2500 angstroms；
Step 4 carries out thermal oxide, the depositing polysilicon layer 9 is fully oxidized to the second oxide layer 8, such as Fig. 6 B institute Show, shielding gate oxide is collectively formed in first oxide layer 6, nitration case 7 and the second oxide layer 8, which makees For the separation layer between the shield grid being subsequently formed and trench bottom surfaces and sidewall surfaces.
The formation for carrying out shield grid and polysilicon gate after this, includes the following steps:
Step 5, deposition gate polysilicon 10 are first returned with dry etching and are carved into silicon face, are then returned and are carved with dry etching To groove, as shown in Figure 6 C；
Step 6 is aoxidized on shielding gate polysilicon 10, forms polysilicon interlevel oxide layer 5, as shown in Figure 6 D；
The second layer oxide layer 8 that the oxidation of depositing polysilicon layer 9 is formed all is etched to nitrogen by wet etching by step 7 Change layer 7, as illustrated in fig. 6e；
Step 8 will be located at the nitration case on polysilicon interlevel oxide layer 57 and all removed, such as schemed by wet etching Shown in 6F；
Step 9 deposits grid polycrystalline silicon 11, and by dry etching to silicon face, polysilicon gate is formed, such as Fig. 6 G institute Show.
After this, p-well, source region, source contact hole, shield grid contact hole etc. are formed according to common process, for ability These are all routine techniques for field technique personnel, are not described in detail herein.
The present invention has the method for forming shielding gate oxide in trenched side-wall in shield grid-deep trench MOSFET, passes through On nitration case depositing polysilicon and to polysilicon carry out thermal oxide mode to form the shielding gate oxidation for meeting thickness requirement Layer, instead of it is existing on nitration case directly by way of SACVD deposited oxide layer, can not only guarantee shield grid and ditch Thickness between groove sidewall and channel bottom for the shielding gate oxide of isolation, and process conditions are simplified, reduce life Cost is produced, production capacity is improved.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can make many modification and improvement, these should also be regarded For protection scope of the present invention.

Claims (4)

1. the method that trenched side-wall forms shielding gate oxide in a kind of shield grid-deep trench MOSFET, which is characterized in that including Following steps:
Step 1, etching is formed with groove on epitaxial layer, using thermal oxide growth technique the groove bottom surface and side wall Surface forms the first oxide layer；
Step 2 forms nitration case on the surface of first oxide layer；
Step 3 forms depositing polysilicon layer on the surface of the nitration case using polycrystalline silicon deposition process；
Step 4 carries out thermal oxide, the depositing polysilicon layer is fully oxidized to the second oxide layer, first oxide layer, nitrogen Change layer and shielding gate oxide is collectively formed in the second oxide layer.
2. the method that trenched side-wall forms shielding gate oxide in shield grid according to claim 1-deep trench MOSFET, It is characterized in that, the depositing polysilicon layer with a thickness of 1000 angstroms~2500 angstroms.
3. the method that trenched side-wall forms shielding gate oxide in shield grid according to claim 1-deep trench MOSFET, It is characterized in that, the depth of the groove is 4 microns~6 microns, Sidewall angles are 86.5 °~88.5 °.
4. the method that trenched side-wall forms shielding gate oxide in shield grid according to claim 1-deep trench MOSFET, It is characterized in that, the thickness of first oxide layer is identical as the thickness of gate oxide in MOSFET, the thickness of the nitration case It is 500 angstroms~1500 angstroms.
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