CN105700076B - A kind of lithographic method of optical waveguide shielded layer - Google Patents
A kind of lithographic method of optical waveguide shielded layer Download PDFInfo
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- CN105700076B CN105700076B CN201610033839.4A CN201610033839A CN105700076B CN 105700076 B CN105700076 B CN 105700076B CN 201610033839 A CN201610033839 A CN 201610033839A CN 105700076 B CN105700076 B CN 105700076B
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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Abstract
The invention discloses a kind of lithographic methods of optical waveguide shielded layer, comprising: S1) the first silicon oxide layer, polysilicon layer and silicon nitride layer are sequentially depositing in surface of silicon；S2 the shielding figure of photoresist) is formed on silicon nitride layer surface；S3 first time etching) is carried out to silicon nitride layer, the polymer and photoresist on surface are removed after etching, silicon nitride layer groove is formed and exposes partial polysilicon layer；S4 second) is carried out to polysilicon layer to etch, and forms polysilicon layer groove and exposes partial silicon substrate；S5 the second silicon oxide layer) is deposited in the silicon chip surface, and is connected with the first silicon oxide layer；S6) the second silicon oxide layer is ground using chemical mechanical milling method, until exposed silicon nitride layer；S7 remaining silicon nitride layer and polysilicon layer remained on surface, the optical waveguide shielded layer needed) are removed.The present invention can substantially improve the sidewall roughness of silicon trench, reduce the scattering loss and transmission loss of silicon substrate optical waveguide.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method more particularly to a kind of etching sides of optical waveguide shielded layer
Method.
Background technique
The advantage that silicon materials make optical waveguide is that sandwich layer and covering have high refractive index contrast, the integrated level in unit area
Higher, the size that can be done can be done smaller.But many problems that the development of silicon-based photonics integration technology is also faced with, wherein
A problem be exactly optical waveguide loss.
In semiconductor integrated circuit manufacture, generally require to perform etching silicon substrate, such as the STI of integrated circuit
(shallow trench isolation) isolation technology deposits a thin layer silica in silicon chip surface, deposits on silica
One layer of silicon nitride forms the graphical window of needs by photoetching process, so in silicon nitride surface coating photoresist on a photoresist
Afterwards using photoresist as shielded layer, silicon nitride layer is carried out using dry plasma etching process and silicon oxide layer etches, next
Photoresist remained on surface is removed, silicon trench etching is carried out by shielded layer of silicon nitride, etches and need depth, Sidewall angles
Silicon trench fills silica in the silicon trench of formation and realizes STI isolation technology.
In actual production process, there are the stripeds of vertical direction (usually to cry for the side wall of silicon trench after etching
The side wall for having this striped is known as " coarse side wall " in the present invention by " striation ", is evaluated with " sidewall roughness " this
The severity of striped.), since STI isolation technology only keeps apart different functional structures physically, this striped
Influence can also receive.But this technique is applied in the optical waveguide forming process of optical device, can be formed in waveguide sidewalls
The striped of this vertical direction, increases the scattering loss of transmission light in waveguide, and then leads to the increase of the transmission loss of optical waveguide.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of lithographic methods of optical waveguide shielded layer, can substantially improve
The sidewall roughness of silicon trench reduces the scattering loss and transmission loss of silicon substrate optical waveguide.
The present invention is to solve above-mentioned technical problem and the technical solution adopted is that provide a kind of etching of optical waveguide shielded layer
Method includes the following steps: S1) the first silicon oxide layer, polysilicon layer and silicon nitride layer are sequentially depositing in surface of silicon；
S2) the shielding figure of photoresist is formed on silicon nitride layer surface using optical waveguide processing reticle；S3 dry plasma) is used
Etching technics carries out first time etching to the silicon nitride layer, and the polymer and photoresist on surface are removed after etching, forms nitrogen
SiClx layer groove simultaneously exposes partial polysilicon layer；S4 the silicon nitride layer after) being etched using first time is shielded layer, using dry method etc.
Plasma etching technique carries out second to the polysilicon layer and etches, and forms polysilicon layer groove and exposes part silicon lining
Bottom；S5 the second silicon oxide layer) is deposited in the silicon chip surface, the surface at the low step of second silicon oxide layer is higher than silicon nitride
The upper surface of layer, and be connected with the first silicon oxide layer；S6) the second silicon oxide layer is ground using chemical mechanical milling method
Mill, until exposed silicon nitride layer；S7) wet process removes remaining silicon nitride layer, removes table using dry plasma etching process
The remaining polysilicon layer in face, the optical waveguide shielded layer needed.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein the thickness of silicon nitride layer is according to chemistry in the step S1
The horizontal breadth that silicon nitride is consumed when mechanical lapping is preset.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein when polysilicon layer etches in the step S4, control polycrystalline
Sidewall angles of the silicon at silicon oxide layer grooved position are 87 degree~90 degree, and are heat-treated to the polysilicon layer after etching.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein heat treatment process is as follows in the step S4: in polysilicon
Layer surface carries out smooth treatment, the thermal oxide to polysilicon sidewall using the method that wet-oxygen oxidation growth thermal oxide layer is removed again
The thickness range of layer is 150nm~200nm；And controlling heat treatment temperature is 1150 degree, heat treatment time is greater than 0.5 hour, right
Polysilicon layer side wall carries out recrystallization processing.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein the chemistry of the second silicon oxide layer is completed in the step S6
After mechanical lapping, continue to the second silicon oxide layer carry out dry etching processing so that the upper surface of the second silicon oxide layer be equal to or
The slightly below upper surface of polysilicon layer.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein after removing polysilicon layer in the step S7, using oxidation
Silicon wet corrosion technique does following micro process to exposed surface of silicon: remaining first oxidation after removal removing polysilicon layer
Silicon layer reduces the roughness of the bottom surface of silicon trench etching.
The lithographic method of above-mentioned optical waveguide shielded layer, wherein second of etching gas is had based on Cl/HBr
A small amount of CF4, pressure 15mt, upper electrode power is 600W, and lower electrode power is 140W, etch period 80s.
The present invention compare the prior art have it is following the utility model has the advantages that optical waveguide shielded layer provided by the invention etching side
Method, after heat treatment using etching polysilicon side wall feature more lower than the roughness of oxide etch side wall and polysilicon
The advantages such as better sidewall roughness, using the figure of the cvd silicon oxide realization optical waveguide shielded layer etching in polysilicon window
Transmitting, the final sidewall roughness for reducing silicon trench etching, reduces the transmission loss for the optical waveguide processed with the technique.
Detailed description of the invention
Fig. 1 is existing silicon trench and shielded layer sidewall surfaces pattern photo figure；
Fig. 2 is existing silicon trench shielded layer and photoresist sidewall surfaces pattern photo figure；
Fig. 3 is to illustrate after present invention silicon chip surface to be processed deposits the first silicon oxide layer, polysilicon layer and silicon nitride layer
Figure；
Fig. 4 is silicon chip surface coating photoresist of the present invention and forms graphic structure on a photoresist by photoetching；
Fig. 5 is that the present invention completes the structural schematic diagram after silicon nitride layer etching and removal photoresist layer；
Fig. 6 is that the present invention completes the structural schematic diagram after polysilicon layer etching；
Fig. 7 is that the present invention continues to deposit the structural schematic diagram after the second silicon oxide layer；
Fig. 8 is that the present invention completes the structural schematic diagram after planarization grinding；
Fig. 9 is the structure that the present invention completes that silicon etching shields layer pattern transmitting；
Figure 10 is that the present invention carries out the structural schematic diagram after dry etching optimization to the second silicon oxide layer；
Figure 11 is to complete the structural schematic diagram that silicon etching shields layer pattern transmitting after present invention grinding optimizes.
In figure:
11 silicon substrate, 21 polysilicon layer, 31 first silicon oxide layer
41 silicon nitride layer, 51 photoresist window, 61 second silicon oxide layer
Specific embodiment
The invention will be further described with reference to the accompanying drawings and examples.
Fig. 1 is existing silicon trench and shielded layer sidewall surfaces pattern photo figure；Fig. 2 is existing silicon trench shielded layer and photoetching
Glue sidewall surfaces pattern photo figure.
Referring to Fig. 1 and Fig. 2, the source that the bed-by-bed analysis striped generates finds the striped and shielded layer nitrogen of silicon trench side wall
The side wall striped of SiClx is consistent, is to be transmitted by silicon nitride (or silica) side wall striped, and from the top of silicon trench
To bottom, striped has the tendency that gradually becoming shallower as.Striped on silicon nitride is to do shielded layer etch silicon nitride with photoresist again
When generate.Therefore it is the side wall shape of shielded layer after shielded layer etching that silicon trench side wall, which generates the source of vertical direction striped,
At the striped of vertical direction.
Analyze reason: using dry etching when silicon nitride mask layer etches, dry etching be a kind of physical action and
The etching technics that chemical action coexists has the advantages of ion sputtering etching and plasma chemical etch concurrently, not only high resolution, and
And etch rate is fast, by adjusting the strong and weak ratio of the two, angle, the rate of etching of adjustable etched sidewall etc..And nitrogen
The shielded layer of SiClx etching is photoresist, pair that photoresist is made of three kinds of photosensitive resin, sensitizer and solvent main components
The mixing liquid of photaesthesia, after photoetching process is handled, the ability of the anti-plasma bombardment of photoresist is also weaker, bombards meeting
Scraggly pattern is formed on the surface of photoresist, while during dry etching, can also generate a kind of polymer
(polymer), this polymer can be deposited on the surface of photoresist and the surface and etching window side wall of side wall and silicon nitride,
There is the position of polymer deposits, the silicon nitride below polymer will not be etched away.By bombarding the convex-concave of the photoresist formed not
The collective effect on flat surface and polymer deposits protection, forms the vertical direction striped of silicon nitride etch rear wall.
In order to solve the above technical problems, the present invention does silicon etching by using polysilicon layer or amorphous silicon layer substitution photoresist
The shielded layer of shielded layer is eliminated or is reduced using polysilicon layer or amorphous silicon layer anti-dry etching ability more better than photoresist
The striped in the sidewalls vertical direction formed after silicon nitride (or silica) etching, and then improve the sidewall profile of silicon trench etching,
Reduce the transmission loss for the optical waveguide processed with the technique.The specific process steps are as follows:
S1: the first silicon oxide layer 31, polysilicon layer 21 and silicon nitride layer 41 are sequentially depositing on 11 surface of silicon substrate；It is described
The horizontal breadth that silicon nitride is consumed when the thickness of silicon nitride layer 41 is ground according to subsequent chemical mechanical is preset, the polysilicon
The silica shielding thickness that the thickness of layer 21 needs when etching according to silicon trench is determining, as shown in Figure 3.
S2: the shielding figure of photoresist is formed on 41 surface of silicon nitride layer using optical waveguide processing reticle, in Fig. 4
Photoresist window 51.
S3: first time etching is carried out to the silicon nitride layer 41 using dry plasma etching process, is removed after etching
The polymer and photoresist on surface form silicon nitride layer shield trenches and expose partial polysilicon layer 21, as shown in Figure 5；
Etching uses standard conditions for the first time, for example gas is with C4F6Based on, have a certain amount of O2And Ar, pressure 40mt, on
Portion electrode power 1200W, magnetic field 15Gaus.
S4: the silicon nitride layer 41 after being etched with first time is shielded layer, using dry plasma etching process to described
Polysilicon layer 21 carries out second and etches, and forms polysilicon layer groove and exposes partial silicon substrate 21, as shown in Figure 6；Second
Secondary etching gas is based on Cl/HBr, with a small amount of CF4, pressure 15mt, upper electrode power is 600W, lower electrode function
Rate is 140W, etch period 80s.When etching to polysilicon layer 21, polysilicon is controlled at silicon oxide layer grooved position
Sidewall angles are 87 degree~90 degree, and are heat-treated to the polysilicon layer 21 after etching, and the roughness water of polycrystalline side wall is improved
It is flat.Heat treatment process is as follows: on 21 surface of polysilicon layer using the method that wet-oxygen oxidation growth thermal oxide layer is removed again to polycrystalline
Sidewall silicon carries out smooth treatment, and the thickness range of the thermal oxide layer is 150nm~200nm；And it controls heat treatment temperature and is
1150 degree, heat treatment time is greater than 0.5 hour, carries out recrystallization processing to 21 side wall of polysilicon layer.
S5: the second silicon oxide layer 61 is deposited in the silicon chip surface, the surface at the low step of second silicon oxide layer 61
It is connected higher than the upper surface of silicon nitride layer 41, and with the first silicon oxide layer 31, as shown in Figure 7；
S6: grinding the second silicon oxide layer 61 using chemical mechanical milling method, until exposed silicon nitride layer 41, such as schemes
Shown in 8；
S7: wet process removes remaining silicon nitride layer 41, is removed using dry plasma etching process remained on surface more
Crystal silicon layer 21, the optical waveguide shielded layer needed, as shown in Figure 9.
The lithographic method of optical waveguide shielded layer provided by the invention can continue to the second silicon oxide layer after chemical mechanical grinding
61 carry out dry etching processing, so that the upper surface of the second silicon oxide layer 61 is equal to or slightly lower than the upper surface of polysilicon layer 21,
As shown in Figure 10.Wet process removes remaining silicon nitride layer 41, is removed using dry plasma etching process remained on surface more
Crystal silicon layer 21, the optical waveguide shielded layer needed are as shown in figure 11.It, can over etching polycrystalline in polysilicon layer dry method stripping process
The first oxide layer between monocrystalline silicon, causes the first oxide layer to be stripped, but can unevenly during removing, meeting in this way
Cause the bottom surface of next silicon trench etching uneven, silica wet process also can be used after removing polysilicon layer 21 in the present invention
Etching process does following micro process to exposed 11 surface of silicon substrate: remaining first silica after removal removing polysilicon layer 21
Layer 31 reduces the roughness of the bottom surface of silicon trench etching.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (7)
1. a kind of lithographic method of optical waveguide shielded layer, which comprises the steps of:
S1: the first silicon oxide layer (31), polysilicon layer (21) and silicon nitride layer (41) are sequentially depositing on silicon substrate (11) surface；
S2: the shielding figure of photoresist is formed on silicon nitride layer (41) surface using optical waveguide processing reticle；
S3: first time etching is carried out to the silicon nitride layer (41) using dry plasma etching process, in etching process
A kind of polymer can be generated, can be deposited on after etching polysilicon layer (21) surface, photoresist (51) surface and side wall and
Silicon nitride layer (41) side wall removes above-mentioned polymer and photoresist after etching, and forming nitridation silicon trench, simultaneously to expose part more
Crystal silicon layer (21)；
S4: the silicon nitride layer (41) after being etched with first time is shielded layer, using dry plasma etching process to described more
Crystal silicon layer (21) carries out second and etches, and forms polysilicon layer groove and exposes partial silicon substrate (11)；
S5: the second silicon oxide layer (61) are deposited on the surface that the silicon substrate (11) exposes, second silicon oxide layer (61)
Surface at low step is higher than the upper surface of silicon nitride layer (41), and is connected with the first silicon oxide layer (31)；
S6: grinding the second silicon oxide layer (61) using chemical mechanical milling method, until exposed silicon nitride layer (41)；
S7: wet process removes remaining silicon nitride layer (41), removes polycrystalline remained on surface using dry plasma etching process
Silicon layer (21), the optical waveguide shielded layer needed.
2. the lithographic method of optical waveguide shielded layer as shown in claim 1, which is characterized in that silicon nitride layer in the step S1
(41) thickness is preset according to the horizontal breadth for consuming silicon nitride when chemical mechanical grinding, the thickness of the polysilicon layer (21)
Degree is greater than or equal to the thickness of the second silicon oxide layer (61) after grinding in the step S6.
3. the lithographic method of optical waveguide shielded layer as shown in claim 1, which is characterized in that polysilicon layer in the step S4
(21) when etching, controlling Sidewall angles of the polysilicon at silicon oxide layer grooved position is 87 degree~90 degree, and to etching after
Polysilicon layer (21) is heat-treated.
4. the lithographic method of optical waveguide shielded layer as stated in claim 3, which is characterized in that heat treated in the step S4
Journey is as follows: being carried out using the method that wet-oxygen oxidation growth thermal oxide layer is removed again to polysilicon sidewall on polysilicon layer (21) surface
Smooth treatment, the thickness range of the thermal oxide layer are 150nm~200nm；And controlling heat treatment temperature is 1150 degree, heat treatment
Time is greater than 0.5 hour, carries out recrystallization processing to polysilicon layer (21) side wall.
5. the lithographic method of optical waveguide shielded layer as shown in claim 1, which is characterized in that complete second in the step S6
After the chemical mechanical grinding of silicon oxide layer (61), continue to carry out dry etching processing to the second silicon oxide layer (61), so that second
The upper surface of silicon oxide layer (61) is equal to or slightly lower than the upper surface of polysilicon layer (21).
6. the lithographic method of optical waveguide shielded layer as shown in claim 1, which is characterized in that remove polycrystalline in the step S7
After silicon layer (21), do following micro process to exposed silicon substrate (11) surface using silica wet corrosion technique: removal is removed
Remaining first silicon oxide layer (31) after polysilicon layer (21) reduces the roughness of the bottom surface of silicon trench etching.
7. the lithographic method of optical waveguide shielded layer as shown in any one of claim 1~6, which is characterized in that described second
Etching gas is based on Cl/HBr, with a small amount of CF4, pressure 15mt, upper electrode power is 600W, lower electrode power
For 140W, etch period 80s.
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| CN113654600A (en) * | 2021-07-23 | 2021-11-16 | 无锡莱斯能特科技有限公司 | Manufacturing method of flow sensor |
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| US6194284B1 (en) * | 1999-08-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method for forming residue free etched silicon layer |
| CN103035561A (en) * | 2012-08-31 | 2013-04-10 | 上海华虹Nec电子有限公司 | Process method for forming inclined angle at top of deep groove |
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN104299938A (en) * | 2013-07-16 | 2015-01-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming a shallow trench isolation structure |
| CN104701158A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Self-aligning double patterning formation method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194284B1 (en) * | 1999-08-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method for forming residue free etched silicon layer |
| CN103035506A (en) * | 2012-08-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Etching method for radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) isolation medium layer deep groove |
| CN103035561A (en) * | 2012-08-31 | 2013-04-10 | 上海华虹Nec电子有限公司 | Process method for forming inclined angle at top of deep groove |
| CN104299938A (en) * | 2013-07-16 | 2015-01-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming a shallow trench isolation structure |
| CN104701158A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Self-aligning double patterning formation method |
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