KR101161661B1 - Method for forming isolation layer of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a device isolation film of a semiconductor device. The disclosed method includes providing a silicon substrate having an isolation region and an active region, forming a hard mask layer on the silicon substrate, and etching the hard mask layer to expose the substrate in the isolation region. Forming a trench by etching the exposed portion of the substrate, forming a sidewall oxide film on the surface of the trench, forming a liner nitride film on the entire surface of the substrate including the sidewall oxide film, and the liner In the method of forming a device isolation film of a semiconductor device comprising the step of embedding an oxide film in the trench in which the nitride film is formed, the forming of the trench, the first etching by anisotropic etching, the hard trench obtained by the first etching Secondary etching by isotropic etching to enter the mask layer The features.

Description

Method for forming isolation layer of semiconductor device

1A to 1C are cross-sectional views of processes for describing a method of forming a device isolation layer using a conventional STI process.

Figure 2a is a photograph of the liner nitride film is lost when forming a device isolation film using a conventional STI process.

Figure 2b is a graph showing the difference in sputtering yield (sputtering yield) according to the angle incident on the silicon substrate when the oxide film deposition by HDP-CVD method.

3A to 3D are cross-sectional views of processes for explaining a method of forming an isolation layer using an STI process according to the present invention.

4 is a view of the liner nitride film formed in accordance with the present invention.

5A to 5D are cross-sectional views illustrating processes of forming device isolation layers using an STI process according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21,31: silicon substrate 22,32: pad oxide film

23,33: pad nitride film 24,34: hard mask film

25, 35: trench 26, 37: sidewall oxide film

27,38: liner nitride film 28,39: device isolation film

36: thermal oxide film

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film using a shallow trench isolation (STI) process.

With the progress of semiconductor technology, the speed and the high integration of semiconductor devices are progressing rapidly, and with this, the demand for refinement | miniaturization of a pattern and high precision of a pattern dimension is increasing. This requirement also applies to device isolation films. This is because, in the trend of decreasing width of device regions, the width of device isolation regions must also be reduced.

In the manufacture of semiconductor devices, device isolation layers are formed for electrical separation between devices, and LOCOS and Shallow Trench Isolation (STI) processes are used to form such device isolation layers.

However, the device isolation film by the LOCOS process has a disadvantage of reducing the device formation area because bird's-beak of the beak shape is generated at the upper corner thereof, and thus has a limitation in its use. Accordingly, a method of forming a device isolation layer using a shallow trench isolation (STI) process has been proposed. Most semiconductor devices have a small width and excellent device isolation characteristics. Forming.

Here, a method of forming a device isolation layer using an STI process currently being performed will be briefly described with reference to FIGS. 1A to 1C.

Referring to FIG. 1A, after the pad oxide film 2 and the pad nitride film 3 are sequentially formed on the silicon substrate 1 having the device isolation region and the active region, the substrate portion corresponding to the device isolation region is exposed. After etching the pad nitride film 3 so as to etch the pad oxide film 2 using the pad nitride film 3, the exposed silicon substrate portion is subsequently etched to form the trench 4.

Referring to FIG. 1B, a sacrificial oxidation process, a cleaning process, and a wall oxidation process are sequentially performed on the substrate resultant, whereby the sidewall oxide film 5 of the thin film is formed on the trench surface. To form. Then, a liner nitride film 6 is deposited on the entire surface of the substrate in order to suppress the oxidation of the substrate in the stress buffering role of the Si and the subsequent device isolation buried oxide film and the subsequent oxidation process.

Referring to FIG. 1C, the buried oxide layer 8 is thickly deposited on the substrate resultant by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) so that the trench 4 on which the liner nitride layer 6 is deposited is buried. .

Subsequently, although not shown, after the buried oxide film 8 is chemical mechanical polished (CMP) until the pad nitride film 3 is exposed, the pad nitride film and the pad oxide film are removed to form an isolation layer.

As described above, in the device isolation film forming method according to the conventional STI process, the buried oxide film deposition for filling the trench is performed by the HDP-CVD method. Here, in the HDP-CVD method, sputtering or etching is performed simultaneously with the deposition of a thin film, so that the fine pattern embedding property is excellent.

On the other hand, when the buried oxide film is deposited by the HDP-CVD method, there is a problem in that the liner nitride film formed in the trench is lost due to sputtering or etching occurring during the deposition process.

In other words, referring to FIG. 2A, when the buried oxide film is deposited by HDP-CVD, the sidewall oxide film protrudes more than the hard mask film at the boundary between the silicon substrate and the hard mask film, while being substantially perpendicular to the incident angle of the implanted ions. As the liner nitride film is deposited as it is, the liner nitride film is lost while acting as a high sputtering yield.

Figure 2b is a graph showing the sputtering yield difference according to the angle of the ions incident on the substrate when depositing the buried oxide film by HDP-CVD method, the sputtering is hardly seen when the angle is vertical, while the incidence angle is the highest sputtering yield at 60 degrees Can be.

As a result, when the liner nitride film formed in the trench is partially lost, the liner nitride film may not function as a liner nitride film, and the increase in the threshold voltage may cause a decrease in device characteristics and a decrease in yield.

Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the loss of a liner nitride film in the process of forming the device isolation film. .

In order to achieve the above object, the present invention provides a silicon substrate having a device isolation region and an active region; Forming a hard mask film on the silicon substrate; Etching the hard mask layer to expose a substrate in an isolation region; Etching the exposed substrate portion to form a trench; Forming a sidewall oxide film on a surface of the trench; Forming a liner nitride film on the entire surface of the substrate including the sidewall oxide film; And embedding an oxide film in the trench in which the liner nitride film is formed. In the method of forming a device isolation film of a semiconductor device, the forming of the trench may include: first etching by anisotropic etching; Provided is a device isolation film of a semiconductor device, characterized in that the secondary trench is etched by isotropic etching so that the obtained trench enters the inside of the hard mask film.

Here, the hard mask film is a film in which a pad oxide film and a pad nitride film are laminated.

The first etching is characterized in that performed using HBr and O2 gas.

The etched trench is formed in the width of 50 ~ 300Å of the hard mask film.

The secondary etching is characterized in that the RF power is performed by dry etching with 50 to 300 kW while using any one gas or mixed gas selected from the group consisting of SF6, HBr and O2 as reactive ion etching.

The secondary etching is characterized in that the hydrofluoric acid, hydrogen peroxide, and pure water is performed by a washing process using a mixed solution mixed in a volume ratio of 1: 300 ~ 900: 450 ~ 1300.

The secondary etching is characterized in that the hydrofluoric acid and hydrogen peroxide are performed by a washing process using a mixed solution mixed in a volume ratio of 1:10 to 30.

The secondary etching is characterized in that the hydrofluoric acid, hydrogen peroxide and nitric acid is characterized in that the washing process using a mixed solution mixed in a volume ratio of 1: 150 ~ 400: 150 ~ 400.

The sidewall oxide film is formed to a thickness of 50 ~ 300Å.

In addition, the present invention provides a silicon substrate having a device isolation region and an active region; Forming a hard mask film on the silicon substrate; Etching the hard mask layer to expose a substrate in an isolation region; Etching the exposed substrate portion to form a trench; Performing an oxidation process on the substrate resultant, thereby forming a thermal oxide film on a surface of the trench; Removing the thermal oxide film formed on the sidewalls of the trench to form the trench into the hard mask film; Forming a sidewall oxide film on a trench surface including the thermal oxide film; Forming a liner nitride film on the entire surface of the substrate including the sidewall oxide film; And embedding an oxide film in the trench in which the liner nitride film is formed.

Here, the hard mask film is a film in which a pad oxide film and a pad nitride film are laminated.

The oxidation process is characterized in that carried out in a furnace of O 2 or H 2 O atmosphere.

The thermal oxide film is characterized in that it is formed to a thickness of 50 ~ 150Å.

The thermal oxide film may be removed by HF or BOE solution so that the thermal oxide film is completely removed and the trench enters a width of 50 to 300 kPa of the hard mask film.

The sidewall oxide film is formed to a thickness of 50 ~ 300Å.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention, the present invention in the etching process for forming the trench, the substrate is first etched, and the trench obtained by the first etching is etched second to enter the inside of the hard mask film.

In this way, after the liner nitride film is formed in the trench, it is possible to prevent the loss of the liner nitride film during the deposition of the buried oxide film by the HDP-CVD method.

That is, conventionally, when depositing a buried oxide film by the HDP-CVD method, there is a problem that the liner nitride film formed in the trench is lost, but in the present invention, the first etching process is performed after etching the substrate in the etching process of the trench. The secondary etching is performed to form trenches inside the hard mask film in the trenches obtained.

Accordingly, since the formation of the liner nitride layer in the trench does not protrude at the edge of the hard mask layer, the liner nitride layer is not lost during subsequent HDP-CVD oxide deposition.

In detail, FIGS. 3A to 3C are cross-sectional views illustrating processes of forming an isolation layer of a semiconductor device according to the present invention.

Referring to FIG. 3A, a hard mask film 24 including a pad oxide film 22 and a pad nitride film 23 is formed on a silicon substrate 21 having a device isolation region and an active region, and then, in the device isolation region. The hard mask layer 24 is etched to expose the corresponding substrate portion.

Referring to FIG. 3B, in order to prevent the subsequent sidewall oxide layer from protruding beyond the hard mask layer 24 after the first etching of the exposed silicon substrate portion, the trench obtained by the first etching may be hard mask layer 24. To form a complete trench (25) by second etching to enter the 50 ~ 300Å wide gap.

Here, the primary etching is performed using HBr and O 2 gas. In addition, the secondary etching may be performed by dry etching with one or a mixture of SF6, HBr, or O2 as the reactive ion etching, and RF power of 50 to 300 kW, or 1: 300 of hydrofluoric acid, hydrogen peroxide, and pure water. Carry out a washing process using a mixed solution mixed at a volume ratio of ˜900: 450-1300, or a washing process using a mixed solution mixed with hydrofluoric acid and hydrogen peroxide at a volume ratio of 1: 10-30. Or, it is carried out by a washing step using a mixed solution in which hydrofluoric acid, hydrogen peroxide and nitric acid are mixed in a volume ratio of 1: 150 to 400: 150 to 400.

 Referring to FIG. 3C, a sacrificial oxidation process, a cleaning process, and a wall oxidation process are sequentially performed on the substrate resultant, whereby the sidewall oxide layer 26 of the thin film is formed on the trench surface. Form 50 to 300Å thick. In this case, the sidewall oxide layer 26 is formed only on the sidewalls and the bottom of the trench.

Next, a liner nitride layer 27 is deposited on the entire surface of the substrate without the sidewall oxide layer 26 protruding from the hard mask layer 24.

Figure 4 can be seen that the liner nitride film formed in accordance with the present invention is not lost.

Here, the present invention performs the trench etching process in two steps to form the trench inside the hard mask layer. Therefore, the sidewall oxide film formed on the trench surface is formed so as not to protrude at the edge of the hard mask film, and as a result, a liner nitride film is formed in the state where the sidewall oxide film does not protrude on the hard mask film, so that subsequent HDP-CVD in the trench is performed. It is possible to prevent the loss of the liner nitride film during the oxide film deposition in a manner.

Referring to FIG. 3D, when the hard mask layer 24 is exposed, a thick oxide film is deposited on the substrate resultant by the HDP-CVD method so that the trench 25 in which the liner nitride layer 27 is deposited is embedded. CMP the oxide film until. Then, the hard mask film is removed to form the device isolation film 28 according to the present invention.

(Another embodiment)

5A through 5D are cross-sectional views illustrating processes of forming a device isolation film of a semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 5A, a hard mask layer 34 including a pad oxide layer 32 and a pad nitride layer 33 is formed on a silicon substrate 31 having a device isolation region and an active region, and then formed in a device isolation region. The hard mask layer 34 is etched to expose a corresponding substrate portion.

Referring to FIG. 5B, a portion of the exposed silicon substrate is etched to form a trench 35. Then, the substrate product is subjected to an oxidation process, whereby a thermal oxide film 36 is formed on the surface of the trench to a thickness of 50 to 150 kPa. Here, the oxidation process is carried out in a furnace (furnace) of O 2 or H 2 O atmosphere.

Referring to FIG. 5C, the hard oxide layer 34 is formed inside the trench 35 by removing the thermal oxide layer formed on the sidewalls of the trench, wherein the thermal oxide layer is removed by HF or BOE solution. The thermal oxide film is completely removed, and the trench 35 is inserted into the hard mask film 34 by 50 to 300 mm wide.

Thereafter, the sacrificial oxidation process, the cleaning process, and the sidewall oxidation process are sequentially performed on the substrate resultant, thereby forming a sidewall oxide film 37 of a thin film on the trench surface having a thickness of 50 to 300 GPa. In this case, the sidewall oxide layer 37 is formed only on the sidewalls and the bottom of the trench. Next, a liner nitride film 38 is deposited on the entire surface of the substrate without the sidewall oxide film 37 protruding from the hard mask film.

Here, the present invention is performed by forming a thermal oxide film on the surface of the trench, and then removing the thermal oxide film to form the trench inside the hard mask film. Therefore, the sidewall oxide film formed on the trench surface is formed so as not to protrude at the edge of the hard mask film, and as a result, the liner nitride film is formed in the state where the sidewall oxide film does not protrude on the hard mask film, so that subsequent HDP-CVD in the trench is performed. It is possible to prevent the loss of the liner nitride film during the oxide film deposition in a manner.

Referring to FIG. 5D, an oxide film is thickly deposited by HDP-CVD on the substrate resultant so that the trench in which the liner nitride film 38 is deposited is filled, and then the oxide film is exposed until the hard mask film 34 is exposed. CMP. Thereafter, the hard mask layer is removed to form the device isolation layer 39 according to the present invention.

As described above, the present invention can prevent the liner nitride film from disappearing even when the oxide film is deposited by the HDP-CVD method by etching the trench to form the trench inside the hard mask film when forming the device isolation film. Therefore, the liner nitride film can be maintained uniformly, thereby improving the uniformity of the threshold voltage, and forming the liner nitride film on the trench sidewall without loss, thereby reducing stress relief and preventing oxidation.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (15)

Providing a silicon substrate having an isolation region and an active region; Forming a hard mask film on the silicon substrate; Etching the hard mask layer to expose a substrate in an isolation region; Etching the exposed substrate to form a trench; Recessing a portion of the substrate on which the trench is formed so that the trench enters inwardly than the etched side of the hard mask layer; Forming a sidewall oxide layer on a surface of the substrate on which the trench is formed, wherein the sidewall oxide layer does not protrude from an etched side of the hard mask layer; Forming a liner nitride film on the entire surface of the substrate including the sidewall oxide film; And Embedding an oxide film in the trench in which the liner nitride film is formed; And partially recessing the substrate on which the trench is formed are performed by an etching process. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein the hard mask layer is a layer in which a pad oxide layer and a pad nitride layer are stacked. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, wherein the forming of the trench is performed by an anisotropic etching process using HBr and O 2 gas. Claim 4 was abandoned when the registration fee was paid. 2. The device isolation film of claim 1, wherein the recessing of the thickness of the substrate on which the trench is formed is performed so that the trench enters an inner side of the hard mask layer by a width of 50 to 300 μs. Formation method. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the etching process is performed by dry etching having an RF power of 50 to 300 kW while using any one gas or a mixed gas selected from the group consisting of SF 6, HBr, and O 2 as reactive ion etching. A device isolation film forming method of a semiconductor device. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, wherein the etching process is performed by using a mixed solution in which hydrofluoric acid, hydrogen peroxide, and pure water are mixed at a volume ratio of 1: 300 to 900: 450 to 1300. . Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the etching process is performed by a cleaning process using a mixed solution in which hydrofluoric acid and hydrogen peroxide are mixed at a volume ratio of 1:10 to 30. 9. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, wherein the etching process is performed by using a mixed solution in which hydrofluoric acid, hydrogen peroxide, and nitric acid are mixed at a volume ratio of 1: 150 to 400: 150 to 400. 9. . Claim 9 has been abandoned due to the setting registration fee. Providing a silicon substrate having an isolation region and an active region; Forming a hard mask film on the silicon substrate; Etching the hard mask layer to expose a substrate in an isolation region; Etching the exposed substrate portion to form a trench; Recessing a portion of the substrate on which the trench is formed so that the trench enters an inside side of the hard mask layer; forming a sidewall oxide layer on a surface of the substrate on which the trench is formed, wherein the sidewall oxide layer is formed on the hard mask. Not protruding beyond the etched side of the membrane; Forming a liner nitride film on the entire surface of the substrate including the sidewall oxide film; And Embedding an oxide film in the trench in which the liner nitride film is formed; Recessing the thickness of the trench is formed in the substrate, Performing an oxidation process to form a thermal oxide film on the surface of the trench; And removing the thermal oxide film. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, wherein the hard mask layer is a layer in which a pad oxide layer and a pad nitride layer are stacked. Claim 12 is abandoned in setting registration fee. Claim 13 was abandoned upon payment of a registration fee. The method of claim 10, wherein the thermal oxide film is formed to a thickness of 50 ~ 150Å. Claim 14 has been abandoned due to the setting registration fee. The device isolation film of claim 10, wherein the thermal oxide film is removed by HF or BOE solution so that the thermal oxide film is completely removed and the trench enters a width of 50 to 300 Å of the hard mask film. Formation method. Claim 15 was abandoned upon payment of a registration fee. The method of claim 10, wherein the sidewall oxide film is formed to have a thickness of 50 to 300 Å.

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