CN110176501A - A kind of preparation method of MPS structure process silicon carbide diode - Google Patents
A kind of preparation method of MPS structure process silicon carbide diode Download PDFInfo
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- CN110176501A CN110176501A CN201910464011.8A CN201910464011A CN110176501A CN 110176501 A CN110176501 A CN 110176501A CN 201910464011 A CN201910464011 A CN 201910464011A CN 110176501 A CN110176501 A CN 110176501A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000008569 process Effects 0.000 title claims abstract description 33
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000407 epitaxy Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 238000001459 lithography Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 239000010936 titanium Substances 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- -1 aluminum ion Chemical class 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000005036 potential barrier Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000001947 vapour-phase growth Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000005275 alloying Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000009835 boiling Methods 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The present invention discloses a kind of preparation method of MPS structure process silicon carbide diode, comprising the following steps: forms N-type epitaxy layer on N-type semiconductor substrate；Zero layer exposure mask is formed, zero layer exposure mask is etched to form lithography layer artoregistration label；The structural area MPS and protection ring region are formed, and carries out ion implanting；It forms cut-off ring region and carries out ion implanting；Form field cut-off ring, protection ring and MPS structure；Expose MPS structure Schottky window region；Form MPS structure Schottky barrier；It carries out front metal to sputter to form metal layer, draws anode；Metal layer on back is formed at the back side of N-type semiconductor substrate, and draws cathode.The forward conduction voltage drop and leakage current of traditional devices can be effectively reduced in the MPS structure silicon carbide diode of the method for the present invention manufacture compared with the silicon carbide diode that prior art manufactures, and improves higher device temperature reliability.
Description
Technical field
The present invention relates to semiconductor power device manufacturing technology field more particularly to a kind of MPS structure process silicon carbide two
The preparation method of pole pipe.
Background technique
Conventional power devices semiconductor nearly all uses silicon substrate material, and the power electronic technique based on silicon device is
Quite mature, the potentiality for continuing to improve and improve power electronic equipment and system performance by silicon device are extremely limited.By
New material meets power electronic equipment of new generation and system to the requirements at the higher level of device performance, just in electricity before explaining in century
Power electronics educational circles builds consensus with technos.Hot spot is subsequently formed to the research and development of silicon carbide power electronic device.
Silicon carbide is a kind of wide bandgap semiconductor, has superior performance, and material property determines that they can take into account
The power and frequency and high-temperature stability of device, therefore Deep trench termination can be made.
For conventional diode, PIN structural has good reverse characteristic, and SBD structure has preferable positive special
Property.But the forward conduction voltage drop and leakage current of conventional diode how is effectively reduced, while improving higher device temperature reliability
Research puzzle as researcher.
Therefore, the prior art is defective, needs to improve.
Summary of the invention
The purpose of the present invention is overcome the deficiencies of the prior art and provide a kind of system of MPS structure process silicon carbide diode
Preparation Method.
Technical scheme is as follows: a kind of preparation method of MPS structure process silicon carbide diode, including following step
It is rapid:
S1, N-type epitaxy layer is formed on N-type semiconductor substrate；
S2, zero layer exposure mask is formed in the N-type epitaxy layer, technique is etched to the zero layer exposure mask and forms subsequent optical
Carve layer artoregistration label；
S3, etch process formation litho pattern is carried out on the zero layer exposure mask, form the structural area MPS and protection ring later
Area, and high energy large dosage ion implanting is carried out to the structural area MPS and protection ring region；
S4, field cut-off ring litho pattern processing is carried out, cut-off ring region on the scene carries out the heavily doped ion implanting of high energy large dosage；
S5, the cut-off of device field is formed to field cut-off ring region, protection ring region and the structural area MPS progress superhigh temperature annealing activation
Ring, protection ring and MPS structure；
S6, hole photoetching treatment exposing MPS structure Schottky window region is carried out；
S7, metal sputtering and short annealing formation MPS structure Schottky barrier are carried out；
S8, progress front metal sputter to form metal layer, are covered on the MPS structure Schottky window region, and pass through quarter
Etching technique completes metal and connects extraction wire, forms anode；
S9, metal layer on back is formed at the back side of N-type semiconductor substrate, and draws cathode.
Further, the N-type semiconductor substrate in the step S1 is N-type silicon substrate, and the epitaxial layer is N-type silicon epitaxy
Layer, the N-type epitaxy layer with a thickness of 5~10 microns, drift doping concentration range is 1 × 1016cm-3~1.5 × 1016cm-3。
Further, the etch process in the step S2 includes photoetching process and etching technics, and the zero layer exposure mask is
Photoresist layer, the thickness of photoresist layer are 0.8~1 micron, formed using dry etch process to the zero layer exposure mask subsequent
Lithography layer artoregistration label, dry etching depth are 0.4~0.6 micron.
Further, etch process includes photoetching process and etching technics in the step S3, and the step S3's is specific
Step includes:
S31, a silica deposition layer is deposited on the zero layer exposure mask using low-pressure chemical vapor phase deposition method；
S32, the processing of P+ trap litho pattern is carried out in the silica deposition layer；
S33, MPS structure and P+ protection ring are formed using trench technique；
S34, the injection of p-type high-energy aluminum ion band photoresist is carried out to the MPS structure and P+ protection ring；
After the completion of S34, ion implanting, carries out wet-dry change and remove photoresist.
Further, the field cut-off ring in the step S4 is N+ cut-off rings, and it is big to carry out high energy in the cut-off ring region
The heavily doped N-type Nitrogen ion band photoresist of dosage injects, and wet-dry change is carried out after the completion of ion implanting and is removed photoresist.
Further, superhigh temperature annealing is carried out to the cut-off ring region, protection ring region and the structural area MPS in the step S5
Processing removes the silica deposition layer, and then exposes the N-type epitaxy layer.
Further, the specific steps of the step S6 include:
S61, low-pressure chemical vapor phase deposition method is used to deposit layer of silicon dioxide sedimentary, institute in the N-type epitaxy layer
State silica deposition layer with a thickness of 5000-6000 angstroms；
S62, photoresist layer is formed in the silica deposition layer；
S63, hole photoetching treatment exposing MPS structure Schottky window region is carried out；
Further, the specific steps of the step S7 include:
S71, photoresist layer is removed using wet-dry change；
S72, Ti sputtering is carried out in the MPS structure Schottky window region；
S73, short annealing is carried out to form Ti silicide, and then form MPS structure Ti barrier schottky, wherein Ti potential barrier
With a thickness of 500~800 angstroms, annealing temperature is 950 DEG C~1000 DEG C for sputtering；
S74, Ti silicide remove the Ti potential barrier of the silicon dioxide layer excess surface using the sour mode of boiling after being formed.
Further, the specific steps of the step S8 include:
S81, metal deposit formation front metal layer, institute are carried out using sputtering method in the MPS structure Schottky window region
Stating front metal layer is aluminum metal layer, with a thickness of 2~3 microns；
S82, the front metal layer is patterned using photoetching and wet-etching technology, draws anode；
S83, alloying is carried out to the front metal layer.
Further, N-type semiconductor substrate back is carried out in the step S9 that remarks, and the N-type after being thinned is thinned
The back side of semiconductor substrate forms metal layer on back using evaporation deposited metal, and the metal layer on back is by titanium layer, nickel layer
With the complex metal layer of silver layer composition, the composite bed thickness is 1000~2000 angstroms of titanium, 2000~3000 angstroms of nickel, silver 10000
~15000 angstroms, the thinning back side of the N-type semiconductor substrate is with a thickness of 250-300 microns.
Using the above scheme, the carbonization of the MPS structure silicon carbide diode of the method for the present invention manufacture and prior art manufacture
Silicon diode compares the forward conduction voltage drop and leakage current that traditional devices can be effectively reduced, and improves higher device temperature reliability.
Detailed description of the invention
Fig. 1 to Figure 13 is the flow chart of the preparation method of MPS structure process silicon carbide diode of the present invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Fig. 1 to Figure 13 is please referred to, the present invention provides a kind of preparation method of MPS structure process silicon carbide diode, including
Following steps:
The preparation method of S1, reference standard type silicon carbide diode grow N-type epitaxy layer 2, specifically in N-type substrate 1
, heretofore described N-type substrate 1 is N-type silicon substrate, and the N-type epitaxy layer 2 is N-type silicon epitaxy layer, the N-type epitaxy layer
With a thickness of 5-10 microns, drift doping concentration range is 1 × 1016cm-3~1.5 × 1016cm-3, as shown in Figure 1.
S2, in the N-type epitaxy layer 2 formed zero layer exposure mask, to the zero layer exposure mask be etched technique formed it is subsequent
Lithography layer artoregistration label.Wherein etch process includes photoetching process and etching technics, and the zero layer exposure mask is photoresist layer, light
The thickness of photoresist layer is 0.8~1 micron, carries out forming subsequent lithography layer from right using dry etch process to the zero layer exposure mask 3
Position label, dry etching depth are 0.4~0.6 micron, as shown in Figure 2.
S3, low-pressure chemical vapor phase deposition method is used to deposit a silica deposition layer on the zero layer exposure mask first, such as
Shown in Fig. 3；The processing of P+ trap litho pattern is carried out in the silica deposition layer, as shown in Figure 4；Trench technique is used again
MPS structure and P+ protection ring 3 are formed, and p-type high-energy aluminum ion band photoresist note is carried out to the MPS structure and P+ protection ring 3
Enter, prevents injection bring lattice damage, removed photoresist after final ion injection using wet-dry change, avoid the residual of photoresist, such as Fig. 5
It is shown.
S4, N+ cut-off ring litho pattern processing are carried out, as shown in Figure 6；High energy large dosage weight is carried out in N+ cut-off ring region
Doped type N Nitrogen ion band photoresist injects to form N+ cut-off rings 4, and band photoresist ion implanting is that injection bring is brilliant in order to prevent
Lattice damage is removed photoresist using wet-dry change after final ion injection, avoids the residual of photoresist, as shown in Figure 7.
S5, the superhigh temperature annealing removal dioxy is carried out to N+ cut-off ring regions, P+ protection ring region and the structural area MPS
SiClx sedimentary exposes the N-type epitaxy layer 2, and then activates and form N+ cut-off rings 4 of device, P+ protection ring 3 and MPS structure,
As shown in Figure 8.
S6, low-pressure chemical vapor phase deposition method is used to deposit layer of silicon dioxide sedimentary, institute in the N-type epitaxy layer 2
State silica deposition layer with a thickness of 5000-6000 angstroms, as shown in Figure 9；Light is formed in the silica deposition layer again
Photoresist layer, and carry out hole photoetching treatment and expose MPS structure Schottky window region, as shown in Figure 10.
S7, it uses wet-dry change to remove photoresist layer first, avoids the residual of photoresist, then in the MPS structure Schottky
Window region carries out Ti sputtering and short annealing to form Ti silicide, and then forms MPS structure Ti barrier schottky 5, finally
The Ti potential barrier of the silicon dioxide layer excess surface is removed using the acid mode of boiling, as shown in figure 11.Wherein Ti potential barrier sputters thickness
It is 500~800 angstroms, annealing temperature is 950 DEG C~1000 DEG C.
S8, metal deposit formation front metal layer is carried out using sputtering method in the MPS structure Schottky window region, used
Photoetching and wet-etching technology are patterned the front metal layer, draw anode 6, as shown in figure 12.Wherein it is described just
Face metal layer 6 is aluminum metal layer, with a thickness of 2~3 microns, finally carries out alloying, alloying energy to the front metal layer again
Enough make the front metal layer finer and close.
S9, N-type semiconductor substrate 1 back side is carried out that remarks, and the N-type semiconductor substrate 1 after being thinned is thinned first
The back side forms metal layer on back using evaporation deposited metal, and the metal layer on back is made of titanium layer, nickel layer and silver layer
Complex metal layer, the composite bed thickness are 1000~2000 angstroms of titanium, 2000~3000 angstroms of nickel, 10000~15000 angstroms of silver, institute
The thinning back side of N-type semiconductor substrate is stated with a thickness of 250-300 microns, then draws cathode 7, as shown in figure 13.
In conclusion the MPS structure silicon carbide diode of the method for the present invention manufacture and the silicon carbide two of prior art manufacture
Pole pipe compares the forward conduction voltage drop and leakage current that traditional devices can be effectively reduced, and improves higher device temperature reliability.
The above is merely preferred embodiments of the present invention, be not intended to restrict the invention, it is all in spirit of the invention and
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within principle.
Claims (10)
1. a kind of preparation method of MPS structure process silicon carbide diode, which comprises the following steps:
S1, N-type epitaxy layer is formed on N-type semiconductor substrate；
S2, zero layer exposure mask is formed in the N-type epitaxy layer, technique is etched to the zero layer exposure mask and forms subsequent lithography layer
Artoregistration label；
S3, etch process formation litho pattern is carried out on the zero layer exposure mask, form the structural area MPS and protection ring region later,
And high energy large dosage ion implanting is carried out to the structural area MPS and protection ring region；
S4, field cut-off ring litho pattern processing is carried out, cut-off ring region on the scene carries out the heavily doped ion implanting of high energy large dosage；
S5, cut-off ring in device field is formed to field cut-off ring region, protection ring region and the structural area MPS progress superhigh temperature annealing activation, is protected
Retaining ring and MPS structure；
S6, hole photoetching treatment exposing MPS structure Schottky window region is carried out；
S7, metal sputtering and short annealing formation MPS structure Schottky barrier are carried out；
S8, progress front metal sputter to form metal layer, are covered on the MPS structure Schottky window region, and pass through etching work
Skill completes metal and connects extraction wire, forms anode；
S9, metal layer on back is formed at the back side of N-type semiconductor substrate, and draws cathode.
2. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
N-type semiconductor substrate in rapid S1 is N-type silicon substrate, and the epitaxial layer is N-type silicon epitaxy layer, the thickness of the N-type epitaxy layer
It is 5~10 microns, drift doping concentration range is 1 × 1016cm-3~1.5 × 1016cm-3。
3. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Etch process in rapid S2 includes photoetching process and etching technics, and the zero layer exposure mask is photoresist layer, and the thickness of photoresist layer is
0.8~1 micron, the zero layer exposure mask is carried out to form subsequent lithography layer artoregistration label using dry etch process, dry method is carved
Losing depth is 0.4~0.6 micron.
4. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Etch process includes photoetching process and etching technics in rapid S3, and the specific steps of the step S3 include:
S31, a silica deposition layer is deposited on the zero layer exposure mask using low-pressure chemical vapor phase deposition method；
S32, the processing of P+ trap litho pattern is carried out in the silica deposition layer；
S33, MPS structure and P+ protection ring are formed using trench technique；
S34, the injection of p-type high-energy aluminum ion band photoresist is carried out to the MPS structure and P+ protection ring；
After the completion of S34, ion implanting, carries out wet-dry change and remove photoresist.
5. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Field cut-off ring in rapid S4 is N+ cut-off rings, carries out the heavily doped N-type Nitrogen ion band photoetching of high energy large dosage in the cut-off ring region
Glue injection, ion implanting carry out wet-dry change after the completion and remove photoresist.
6. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
It is heavy that the superhigh temperature annealing removal silica is carried out to the cut-off ring region, protection ring region and the structural area MPS in rapid S5
Lamination, and then expose the N-type epitaxy layer.
7. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Suddenly the specific steps of S6 include:
S61, in the N-type epitaxy layer using low-pressure chemical vapor phase deposition method deposit layer of silicon dioxide sedimentary, described two
Silicon oxide deposited layer with a thickness of 5000-6000 angstroms；
S62, photoresist layer is formed in the silica deposition layer；
S63, hole photoetching treatment exposing MPS structure Schottky window region is carried out.
8. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Suddenly the specific steps of S7 include:
S71, photoresist layer is removed using wet-dry change；
S72, Ti sputtering is carried out in the MPS structure Schottky window region；
S73, short annealing being carried out to form Ti silicide, and then forming MPS structure Ti barrier schottky, wherein Ti potential barrier sputters
With a thickness of 500~800 angstroms, annealing temperature is 950 DEG C~1000 DEG C；
S74, Ti silicide remove the Ti potential barrier of the silicon dioxide layer excess surface using the sour mode of boiling after being formed.
9. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
Suddenly the specific steps of S8 include:
S81, the MPS structure Schottky window region using sputtering method carry out metal deposit formed front metal layer, it is described just
Face metal layer is aluminum metal layer, with a thickness of 2~3 microns；
S82, the front metal layer is patterned using photoetching and wet-etching technology, draws anode；
S83, alloying is carried out to the front metal layer.
10. the preparation method of MPS structure process silicon carbide diode according to claim 1, which is characterized in that the step
N-type semiconductor substrate back is carried out in rapid S9 remarks are thinned, and the back side of the N-type semiconductor substrate after being thinned is using evaporation
Method deposited metal forms metal layer on back, and the metal layer on back is the complex metal layer being made of titanium layer, nickel layer and silver layer, institute
Stating composite bed thickness is 1000~2000 angstroms of titanium, 2000~3000 angstroms of nickel, 10000~15000 angstroms of silver, the N-type semiconductor lining
The thinning back side at bottom is with a thickness of 250-300 microns.
Priority Applications (1)
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