CN104201213A - Junction barrier schottky diode - Google Patents

Abstract

The invention discloses a junction barrier Schottky diode. The invention also provides a preparation method of the device. The junction barrier Schottky diode of the present invention includes the back metal, Si substrate, epitaxial layer, several concentric p+ rings on the epitaxial layer and doped regions between them, which are stacked in sequence, and are located on the epitaxial layer The silicide layer, the front metal on the silicide layer, the termination structure around the active area in the epitaxial layer, and the mask layer on the epitaxial layer. The invention can reduce the area of the device, improve the effective utilization rate of the device area, also increase the reverse voltage of the device and reduce the forward voltage and leakage current of the device; and make the performance of the device more stable and reliable.

Description

A Junction Barrier Schottky Diode

technical field

The invention relates to a junction barrier Schottky diode (JBS) device combining a Schottky diode (SBD) and a PiN diode.

Background technique

As the most basic, commonly used and indispensable part of the power semiconductor system, the power rectifier has attracted much attention for its important role in the fields of high-voltage direct current transmission, power supply and motor. At present, there are two main types of commercial power diodes: PiN diodes and Schottky barrier diodes (SBDs). However, due to some shortcomings of PiN diodes and SBD diodes, their application range is limited. In 1984, B.J.Baliga et al. proposed the combination of PiN diodes and SBD diodes, that is, junction barrier Schottky diodes (JBS), thus greatly expanding the application prospects of Schottky barrier diodes.

Junction barrier Schottky (JBS) diodes select the advantages of PiN junction diodes and Schottky barrier diodes while abandoning their respective shortcomings. In addition to high withstand voltage, high current, good high frequency characteristics and low turn-on voltage In addition to the characteristics of derating, it also has low switching loss and the ability to resist overcurrent and overvoltage.

At present, the 20A/600V-1200V SBD based on SiC has been used in the fields of motor drive, power factor control (PFC) and transformer secondary. The development of devices based on wide bandgap materials is emerging in an endless stream. In particular, the improved JBS structure of the active region of the device has attracted extensive attention from researchers because of its flexible structure and easy adjustment. In the past two years, the research on JBS structure has advanced by leaps and bounds, and the research results are too numerous to enumerate. A large number of experimental research results have also greatly promoted the commercialization process of JBS rectifiers. Represented by Cree, Microsemi, Infineon, Diodes, and Renesas Electronics Co., Ltd., semiconductor manufacturers in developed countries in Europe, America and Japan have continuously launched to the market. New products, and the voltage and current of their products cover a wide range. In China, Tyco Tianrun Semiconductor Technology (Beijing) Co., Ltd. announced the commercialization of four products of 600V-1200V/10A-50A for the first time at the beginning of this year, and two products of 1700V/10A and 3300V/5A are in the research and development stage.

In recent years, domestic research on junction barrier Schottky diodes has been increasing, and corresponding products have also been launched. However, due to some limitations of Si materials, the withstand voltage and turn-on power consumption of Si-based JBSs are not as good as SiC-based JBSs, so In this regard, the structure of Si-based JBS needs to be further improved.

When a forward voltage drop is applied on JBS, the pn junction in the device is in a conducting state, but since the turn-on voltage of SBD is lower than that of the pn junction, the forward current is from the Schottky barrier contact to the pn junction of the route between the SBD. Therefore, the size of the p ⁺ ring area determines the forward current of the device.

When a reverse voltage drop is applied on the JBS, the SBD in the device plays a major role and forms a depletion region between the pn junctions, so the Schottky barrier is affected by the applied voltage and is shielded by the depletion region, thereby effectively Ground suppresses the reduction of the Schottky barrier, thereby reducing the reverse leakage current.

To sum up, no matter when JBS is forward or reverse, the p ⁺ ring will have a certain influence on the current of the device. Therefore, to optimize the performance of JBS, the area of p ⁺ should be analyzed. Therefore, the present invention is a new and improved junction barrier Schottky diode, that is, a junction barrier Schottky diode with an annular longitudinal structure (annular longitudinal JBS). The present invention adopts a plurality of rings connected in parallel in the active area of the device, correspondingly increases the effective area of the device, improves the effective utilization rate of the device area, reduces the forward conduction voltage drop and leakage current of the device, and further improves the Device stability and reliability.

A paper by Wang Yifan of Lanzhou University (Preparation of new silicon-based JBS Schottky diodes above 300V. Wang Yifan, Wang Chaolin, Liu Su, He Shaobo. Electronic Devices. Volume 34, Issue 6, December 2011) mentioned that the honeycomb-like Although the junction barrier Schottky diode of the structure (as shown in Figure 1) optimizes the effective area of the p ⁺ region, it also relatively reduces its forward voltage and on-state resistance, but compared with the structure of the present invention, the former device's The stability and reliability are obviously not as good as the structure proposed by the present invention; Wang Ying from Harbin Engineering University applied for an invention patent application for "stacked p ⁺ -p junction barrier control Schottky diode" (application number 201110129276.6. Application publication number CN 102208456 A) The structure of the junction barrier controlled Schottky diode proposed is a stacked p ⁺ -p region type structure (as shown in Figure 2), which improves the reverse withstand voltage of the junction barrier Schottky diode device, However, its preparation process is relatively complicated; Liu Wei of Suzhou Silicon Energy Semiconductor Technology Co., Ltd. applied for an invention patent "Trench Schottky Barrier Diode Rectifier Device and Manufacturing Method" (application number 201010208580.5. Application publication number CN 101901807 A) The structure of the trench Schottky barrier diode rectifier device is proposed (as shown in Figure 3). This structure uses new technology to improve the reverse leakage of the device, etc., and also improves the reliability of the device, but the disadvantages remain It's a bit complicated.

Contents of the invention

The invention provides an improved junction barrier that can overcome the deficiencies of the prior art, increase the effective channel area of the device, improve the effective utilization rate of the device, and improve the leakage current of the device while reducing its forward voltage. Teky diode. The invention also provides a preparation method of the device.

The structure of the junction barrier Schottky diode of the present invention is shown in FIG. 5 , which includes back metal 9, Si substrate 1, epitaxial layer 2, and several concentric p+ rings 4 on the epitaxial layer that are stacked in sequence. and the doped region 5 therebetween, the silicide layer 6 on the epitaxial layer, the front metal 7 on the silicide layer 6, the terminal structure around the active region 10 in the epitaxial layer, and the mask on the epitaxial layer Membrane 8. The present invention is characterized in that it consists of several concentric p ⁺ rings 4 and doped regions 5 between them, as well as silicide, front metal or mask layer above this and epitaxial layer and substrate below this It is formed by connecting several JBS cells 3 in parallel with the back metal.

In the junction barrier Schottky diode of the present invention, the epitaxial layer has a low impurity doping concentration, the substrate layer has a high impurity doping concentration, and the concentric p ⁺ ring (4) region has a high doping concentration agent concentration.

In the junction barrier Schottky diode of the present invention, two continuously increasing depletion layers are formed between two adjacent concentric p ⁺ regions according to the PN junction principle, and a ring-shaped vertical channel is formed between the depletion layers, thereby increasing The effective channel area of the device is increased.

In the junction barrier Schottky diode of the present invention, the concentric p ⁺ ring region on the epitaxial region and the Schottky barrier region on the doping region are formed of metal silicide.

Junction barrier Schottky diode preparation method of the present invention is:

a. Provide a semiconductor substrate of silicon material;

b. forming a first mask layer on the substrate;

c. Perform the first photolithography process on the substrate to form concentric p ⁺ ring windows;

d. Perform ion implantation and annealing to form concentric p ⁺ ring junctions;

e. forming a second mask layer on the substrate;

f. Perform a second photolithography process on the substrate, draw the corresponding pattern on the photolithography board on the epitaxial layer of the device, and deposit metal on it, and then go through the silicide process to form a Schottky potential base;

g. Perform a third photolithography process on its substrate to form an anode;

i. Perform backside metal evaporation on the bottom of the substrate to form the cathode.

In the method of the present invention, the method for forming the first mask layer is a thermal oxidation process.

In the method of the present invention, the ion-implanted material of the concentric p ⁺ ring region is a common p-type dopant.

In the preparation method of the present invention, the first mask layer is a SiO ₂ layer, which acts as a mask for blocking the oxide layer. What grow directly on the silicon chip is the doped stop mask layer, what adopt in the present invention is the method of thermal oxidation, and its thickness is at 7000 ~11000 ; Serve as the _SiO2 layer of blocking oxide layer mask effect in the present invention, its thickness requires at 400 ~500 ; The field oxide layer is used as an isolation barrier between transistors, and its thickness requires 4000 ~5400 , wherein the blocking oxide layer and the field oxide layer belong to the second mask layer. Therefore the thickness of the second mask layer is smaller than that of the first mask layer.

In the preparation method of the present invention, the barrier metal used in the second photolithography is NiPt alloy (such as NiPt10, NiPt15 or NiPt60 and other materials).

In the preparation method of the present invention, the barrier metal formed by metal sputtering and the silicide formed by the silicide forming process can respectively form ohmic contacts and Schottky contacts with the p ⁺ ring and the epitaxial layer.

In the preparation method of the present invention, a layer of metal is deposited on the epitaxial wafer by metal sputtering to form the front metal as the anode of the device.

In the preparation method of the present invention, rapid thermal annealing is carried out after ion implantation. This technical measure can reduce the damage caused by ion implantation to the silicon wafer, and at the same time, the lifetime and mobility of minority carriers will also reach a certain degree in different degrees. Recovery, the impurity ions also get a certain proportion of electrical activation, thereby reducing the leakage current.

An annular longitudinal junction barrier Schottky diode (annular longitudinal JBS) device is obtained by the above method. The active area of the device is composed of several JBS cells connected in parallel; from the cross section, each JBS cell is located in the Between the back metal of the device and the front metal of the device; each cell also includes a heavily doped single crystal silicon substrate with a conductive layer connecting the lower part of the silicon chip to the back metal, located on the top of the silicon chip Lightly doped silicon epitaxial layer (2) with the conductive layer connected between the front metal and silicide, concentric p ⁺ rings (4) formed by ion implantation on the upper part of the silicon wafer epitaxial layer, and the silicon wafer epitaxial layer The Schottky barrier region (6) formed on the top through barrier metal deposition, silicide formation and metal corrosion, and the insulating mask layer as a blocking oxide layer mask, field oxidation and doping barrier ( 8).

In the preparation method of the present invention, the mask layer can be made of insulating materials such as silicon dioxide, polysilicon, phosphosilicate glass, silicon nitride glass or polyimide, and can be defined according to the required thickness, or can be made according to the general process conduct.

The material of the substrate region with conductivity type in the present invention is a semiconductor material (such as silicon, arsenic, silicon carbide, etc.). The material of the epitaxial region with conductivity type is a semiconductor material (such as silicon, silicon carbide, etc.), and has a certain thickness, and the thickness ratio of the substrate region with the same conductivity type is constant. The method of epitaxially growing an epitaxial layer on the substrate of the device can be physical vapor deposition epitaxy, or molecular beam epitaxy.

The Schottky contact located on the epitaxial layer has a certain relative width ratio to the multiple junction barrier Schottky contact JBS regions located on the surface of the epitaxial region adjacent to the Schottky contact, which is It is obtained by analyzing and analyzing it, so as to achieve the required conditions, and its ratio is about 7~4. Similarly, the doping in the JBS region is also calculated based on the required conditions. The doping level is about 10 ^13~16 cm ^-3 , and the doping depth is generally about 5~10um in the longitudinal direction.

An ohmic contact is formed between the back metal layer and the substrate; the silicide formed by the barrier metal forms a Schottky contact with the epitaxial layer; the silicide formed by the barrier metal forms an ohmic contact with the p ⁺ ring .

As the material of the back metal or the front metal, titanium (Ti) tungsten (W) aluminum (Al) alloy or titanium (Ti) nickel (Ni) silver (Ag) alloy is used.

The annular longitudinal junction barrier Schottky diode (JBS) of the present invention, firstly, the concentric p ⁺ rings of the device are evenly distributed on the top of the epitaxial layer of the silicon wafer, which can be formed by one photolithography and ion implantation technology, so the preparation process is simple; Secondly, the present invention distributes vertical channel devices laterally, and in addition, by designing the chip as a ring structure, the area of the device can be reduced, and the effective utilization rate of the device area can be improved; finally, the present invention can increase the channel of the device. The effective area of the track can reduce the forward voltage more effectively, and also improve the leakage current of the device. Due to the above-mentioned technical measures, the device will be more stable and the reliability of the device will be better. Herein lies the advantage of the present invention.

Description of drawings

Accompanying drawing 1 is the JBS profile diagram of dot matrix distribution in the prior art;

Accompanying drawing 2 is the JBS sectional view of stacked p ⁺ p structure in the prior art;

Accompanying drawing 3 is prior art trench type JBS sectional view;

Accompanying drawing 4 is a top view of the device structure (including terminal structure but no metal covering) of the present invention, the materials of the concentric rings in a and b in the figure refer to n-type or p-type respectively);

Accompanying drawing 5 is the longitudinal sectional view of the device of the present invention;

Accompanying drawing 6 is the top view of the active region of the JBS device of the present invention, the materials of the concentric rings in a and b in the figure refer to n-type or p-type respectively);

Accompanying drawing 7 is the JBS cell structure figure of the present invention;

Accompanying drawing 8～Fig. 16 are technological process schematic diagrams of the present invention;

Accompanying drawing 17 is the front plan view of device of the present invention;

Accompanying drawing 18 is the reverse characteristic curve of JBS diode of the present invention, when its leakage current is 20 μ A, withstand voltage capacity reaches 650V;

Accompanying drawing 19 is the forward characteristic curve of the JBS diode of the present invention, and when the forward current is 10 A, the voltage drop is within 1 V.

In the above drawings, 3 is the JBS cell, 1 is the silicon substrate, 2 is the epitaxial layer of the silicon wafer, 4 is the concentric p ⁺ ring, and 5 is the doped region on the top of the epitaxial layer of the silicon wafer except the p ⁺ ring, 6 is the silicide formed by the barrier metal, 7 is the front metal layer, 8 is the _SiO2 mask layer, 9 is the back metal layer, 10 is the active area, 11 is the cut-off ring, 12 is the field limiting ring, and 13 is the optical Resist, 14 is a silicon wafer.

Detailed ways

The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

Step 1: On a heavily doped single crystal silicon substrate 1 with a conductivity type, grow a lightly doped silicon epitaxial layer 2 with the same conductivity type (as shown in Figure 8);

Step 2: grow a barrier dielectric layer on top of the silicon epitaxial layer 2, which is a silicon dioxide layer (as shown in Figure 9);

Step 3: Perform photolithography on the silicon dioxide layer grown in the previous step, and define a p ⁺ ring window on the silicon wafer, as shown in Figure 10;

Step 4: Use wet etching or dry etching to selectively remove the silicon dioxide layer not covered by the photoresist, revealing the corresponding epitaxial layer shown in Figure 11, and the remaining silicon dioxide layer acts as a mask;

Step 5: By means of ion implantation, ions of p-type material are implanted into the window etched in the previous step, as shown in FIG. 12 . After rapid annealing, the lattice damage caused by the ion implantation process is eliminated, and the increase of defect centers and the increase of leakage current are avoided, as shown in Figure 13;

Step 6: The second photolithography forms the Schottky contact barrier window for the next barrier metal sputtering, as shown in Figure 14;

Step 7: Sputter the barrier metal in the window formed in the sixth step to form the front metal layer 7 as the anode of the device, and then form a good Schottky barrier after silicide heat treatment, and completely remove the unreacted The barrier metal is removed, and the silicide formed by the silicide formation process can form an ohmic contact or a Schottky contact with the p ⁺ ring and the epitaxial layer, as shown in Figure 15; Step 8: Reverse etching after sputtering the front metal , form lead holes, and finally obtain the structure shown in Figure 16 (Note: The lead hole structure is not shown in Figure 16);

Step 9: The back metal is evaporated to form the cathode metal and a good ohmic contact, and then the back is thinned, as shown in Figure 5.

After the above steps, the vertical structure with cross-section shown in Figure 5 and the JBS cell (3) structure formed by several concentric P ⁺ rings (4) separated from each other by epitaxial layers as shown in Figure 4 were finally prepared. In practical applications, the concentric rings of the present invention can be made of p-type or n-type materials. Fig. 7 is a schematic diagram of a JBS cell. Fig. 8 refers to a schematic cross-sectional view of the device, and indicates the description of each part.

In this implementation case, Si epitaxial wafers, concentric p ⁺ rings with 6um equal ring width and 36um equal ring spacing, and a terminal structure of 5 floating field limiting rings are used to make a junction barrier with a reverse withstand voltage of up to 600V Schottky diodes. In this example, while reducing the forward voltage of the JBS device, the effective area utilization rate of the device is improved, and the reverse leakage and reliability thereof can also be improved. The following are the measured IV characteristics for this example.

At room temperature (22°C) in a clean room, use Tektronix 576 Curve Tracer to test the breakdown characteristics of the JBS diode, as shown in Figure 18. The measured reverse characteristic of the JBS diode is that when the leakage current is 20μA, the withstand voltage capacity reaches 650V. the

It can be seen from Figure 18 that when the reverse leakage current of the device is not greater than 20μA, the withstand voltage capacity of the device reaches 650V, and it has relatively hard breakdown characteristics. When the leakage current is very small, there are large fluctuations or even double curves, which is due to the hysteresis phenomenon of the device caused by the sine wave of the applied scanning voltage.

The forward characteristic curve of the JBS diode of the present invention is shown in the accompanying drawing 19. It can be seen from FIG. 19 that the forward characteristic of the JBS diode of the present invention is: when the forward current is 10 A, the voltage drop is within 1 V. It can also be seen from FIG. 19 that the threshold voltage of the device of the present invention is about 0.3V. The increase of the on-state voltage drop gradually decreases with the increase of the current, indicating that after the device is in forward conduction, the on-state voltage drop becomes larger with the increase of the current, and at the same time, the modulation effect of the injection of minority carriers in the P ⁺ region is more significant, and the resistance of the drift region gradually decreases. Small, the negative feedback reduces the increase of the on-state voltage drop. When the forward current reaches 10A ( 33.3/cm ² ), the on-state voltage drop is less than 1V.

In the above-mentioned preparation method of the present invention, the first mask layer is a SiO ₂ layer, which acts as a mask for the blocking oxide layer. Of course, SiO ₂ can also be used for field oxidation and doping blocking, both of which can be used in the present invention. What grow directly on the silicon chip is the doped stop mask layer, what adopt in the present invention is the method of thermal oxidation, and its thickness is at 7000 ~11000 ; Serve as the _SiO2 layer of blocking oxide layer mask effect in the present invention, its thickness requires at 400 ~500 ; The field oxide layer is used as an isolation barrier between transistors, and its thickness requires 4000 ~5400 , wherein the blocking oxide layer and the field oxide layer belong to the second mask layer. Therefore the thickness of the second mask layer is smaller than that of the first mask layer.

An annular longitudinal junction barrier Schottky diode (annular longitudinal JBS) device is obtained by the above method. The active area of the device is composed of several JBS cells connected in parallel; from the cross section, each JBS cell is located in the Between the back metal of the device and the front metal of the device; each cell also includes a heavily doped single crystal silicon substrate with a conductive layer connecting the lower part of the silicon chip to the back metal, located on the top of the silicon chip Lightly doped silicon epitaxial layer (2) with the conductive layer connected between the front metal and silicide, concentric p ⁺ rings (4) formed by ion implantation on the upper part of the silicon wafer epitaxial layer, and the silicon wafer epitaxial layer The Schottky barrier region (6) formed on the top through barrier metal deposition, silicide formation and metal corrosion, and the insulating mask layer as a blocking oxide layer mask, field oxidation and doping barrier ( 8).

In the present invention, the conditions required for a series of processes carried out on the epitaxial layer of the JBS device are adjustable so as to achieve the required conditions. For example, the material used as the device mask layer or barrier layer can be Silicon can also be phosphosilicate glass, polysilicon, etc. The present invention only changes and optimizes the structure in the active area of the JBS device, and there is no special description for the terminal structure as a part of the device, so as long as it is a terminal structure that can be beneficial to the forward and reverse characteristics of the device, the structure of the present invention devices are equally suitable.

In summary, the present invention provides a device that can overcome the deficiencies of the prior art, while reducing its forward voltage, increase the channel effective area of the device and improve the effective area utilization of the device and improve the leakage current of the device. The improved junction barrier Schottky diode which further improves the stability and reliability of the device.

Claims (11)

1. a junction barrier schottky diode, comprise the back metal (9) that is cascading, Si substrate (1), epitaxial loayer (2), in the doped region (5) between Hep+ district, epitaxial loayer Shang p+ district, be arranged in disilicide layer (6) on epitaxial loayer, be positioned at front metal (7) on disilicide layer (6), be positioned at the terminal structure of epitaxial loayer active area (10) surrounding, and be positioned at mask layer on epitaxial loayer (8), it is characterized in that doped region (5) between Hep+ district, p+ district is by several concentric p ⁺annulus (4) and between doped region (5), and several JBS cellulars (3) that the silicide on this, front metal or mask layer and the epitaxial loayer under this, substrate and back metal form are formed in parallel.

2. junction barrier schottky diode according to claim 1, is characterized in that described in it epitaxial loayer has the doping content of low impurity, and substrate layer has the doping content of high impurity, with one heart p ⁺annulus (4) region has high dopant.

3. junction barrier schottky diode according to claim 1 and 2, is characterized in that concentric p on epitaxial region ⁺schottky barrier district on ring district (4) and doped region (5) is formed by metal silicide.

4. junction barrier schottky diode preparation method claimed in claim 1, is characterized in that:

A., the semiconductor substrate of one silicon materials is provided;

B. on this substrate, form the first mask layer;

C. this substrate is carried out to photoetching process for the first time, form concentric p ⁺ring window;

D. carry out Implantation, and annealing, and then form concentric p ⁺loops;

E. on this substrate, form the second mask layer;

F. this substrate is carried out to photoetching process for the second time, corresponding Patten drawing on photolithography plate, on the epitaxial loayer of device, and to depositing metal thereon, then the technique of passing through silicide, is formed to Schottky barrier;

G. its substrate is carried out to photoetching process for the third time, form anode;

H. back metal evaporation is carried out in the bottom of its substrate, form negative electrode.

5. method according to claim 4, the method that it is characterized in that forming the first mask layer is thermal oxidation technology.

6. method according to claim 5, is characterized in that described concentric p ⁺the material of the Implantation in ring district is common P type dopant.

7. according to the method for claim 6, it is characterized in that carrying out rapid thermal annealing after Implantation.

8. method according to claim 7, is characterized in that mask layer can be the materials such as silicon dioxide, polysilicon, phosphorosilicate glass, nitrogen silex glass or polyimides.

9. according to the method described in claim 4 or 5 or 6 or 7 or 8, it is characterized in that the barrier metal adopting in photoetching is for the second time NiPt alloy.

10. according to the method for claim 9, it is characterized in that the metal sputtering method that barrier metal adopts forms, then the silicide generating by Formation of silicide technique can be respectively and p ⁺ring, epitaxial loayer form ohmic contact or Schottky contacts.

11. according to the method for claim 10, it is characterized in that front metal deposit is to form by metal sputtering.