CN210110785U - Schottky device structure - Google Patents
Schottky device structure Download PDFInfo
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- CN210110785U CN210110785U CN201921026802.4U CN201921026802U CN210110785U CN 210110785 U CN210110785 U CN 210110785U CN 201921026802 U CN201921026802 U CN 201921026802U CN 210110785 U CN210110785 U CN 210110785U
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- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005036 potential barrier Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000008092 positive effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The utility model provides a Schottky device structure, which comprises a substrate material and a groove, wherein the substrate material comprises a substrate and an epitaxial layer, the epitaxial layer is arranged on one side surface of the substrate, and photoetching is formed on the epitaxial layer; the PN junction is formed on the side wall of the groove by ion implantation and is symmetrically arranged on the side wall of the groove; the oxide layer covers the surface of the groove; barrier metal deposited on the barrier region; the front metal is deposited on the barrier metal and the oxide layer. The utility model has the advantages that one-time photoetching can be omitted, the terminal structure size is reduced, the Schottky contact area is enlarged, and a way is provided for effectively improving the power consumption of the device; the process flow can reduce one-time photoetching, simplify the process flow and reduce the production cost.
Description
Technical Field
The utility model belongs to the technical field of semiconductor device, especially, relate to a schottky device structure.
Background
At present, most of terminal structures of common Schottky devices are terminal structures of a field plate and a protection ring, the protection ring and the field plate occupy a large part of the limited area of a chip, the space for reducing forward voltage drop and improving power consumption is limited, and the whole process needs three times of photoetching. In addition, in order to solve the problem of premature breakdown caused by over-concentration of fringe electric field lines, the schottky diode is added with a guard ring and a field plate process, but the current mainstream terminal structure occupies a large part of the chip area, so that the forward voltage drop cannot be further reduced; the chip size cannot be further reduced due to the large chip area occupied by the guard ring and the field plate, and the utilization rate of materials is limited.
Disclosure of Invention
In view of the above, the to-be-solved problem of the present invention is to provide a schottky device structure, increase the barrier area, reduce the consumption, increase the core number, improve material utilization rate.
In order to solve the technical problem, the utility model discloses a technical scheme is: a Schottky device structure comprises a substrate material including a substrate and an epitaxial layer disposed on one side of the substrate, an
The groove is formed on the epitaxial layer through photoetching;
the PN junction is formed on the side wall of the groove by ion implantation and is symmetrically arranged on the side wall of the groove;
the oxide layer covers the surface of the groove;
barrier metal deposited on the barrier region;
the front metal is deposited on the barrier metal and the oxide layer.
Furthermore, the cross section of the groove is U-shaped, and the groove is annular.
Furthermore, the front metal is arranged on the oxide layer of the side wall of the groove close to the potential barrier region.
Furthermore, the thickness of the oxide layer is 2000A-20000A.
Further, the oxide layer is silicon dioxide.
Further, the other side surface of the substrate is provided with back metal.
Further, the depth of the groove is larger than that of the PN junction.
Further, the PN junction is a P-type impurity.
The utility model has the advantages and positive effects that: one-time photoetching can be omitted, the size of a terminal structure is reduced, the Schottky contact area is enlarged, and a way is provided for effectively improving the power consumption of a device; one-time photoetching can be reduced in the process flow, the process flow is simplified, and the production cost is reduced; the size of the terminal structure is reduced, the area of a potential barrier region is increased, the forward voltage drop is reduced, and a new way is provided for reducing the power consumption; if the area of the chip is not increased, the size of the chip can be reduced on the basis of the original device structure, and the number of the cores is increased (for example, the number of cores can be increased by 10% after the original 60mil chip uses a new device structure); firstly, the barrier area can be increased, and the power consumption is considered to be reduced; and the second method can increase the core number, improve the utilization rate of materials and reduce the production cost.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
In the figure:
1. front metal 2, barrier metal 3, PN junction
4. Oxide layer 5, substrate material 6, back metal
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific embodiments.
Fig. 1 shows a schematic structural diagram of an embodiment of the present invention, specifically showing the structure of the embodiment, the embodiment relates to a schottky device structure, the size of the terminal structure is reduced, the area of the barrier region is increased, the forward voltage drop is reduced, and a new way is provided for reducing the power consumption; under the condition that the area of the original chip is not changed, the size of the chip can be reduced on the basis of the structure of the original device, and the number of the cores is increased; one-time photoetching is reduced in the process flow, the process flow is simplified, and the production cost is reduced.
Specifically, the schottky device structure, as shown in fig. 1, includes a substrate material 5, where the substrate material 5 includes a substrate and an epitaxial layer, the epitaxial layer is disposed on one side of the substrate, the epitaxial layer is formed on one side of the substrate by diffusion, and the substrate material 5 may be an N-type epitaxial substrate, for example, an N-epi on an N + substrate, an N + epi on an N-substrate, or other substrate materials, and is selected according to actual needs, and no specific requirement is made here. In this embodiment, an N-type epitaxial substrate material will be described as an example.
The total thickness of the substrate material 5 is 300-.
The groove is formed on the epitaxial layer through etching, the cross section of the groove is U-shaped, the groove is annular, the groove is formed on the epitaxial layer through photoetching and dry etching processes, the position is selected according to actual requirements, and the groove serves as a terminal structure of a device and is convenient for manufacturing electronic elements.
And the oxide layer 4 covers the surface of the groove, the oxide layer 4 is formed by pushing and growing a furnace tube, the thickness of the oxide layer 4 is 2000A-20000A, the oxide layer 4 is silicon dioxide, and the oxide layer serves as a passivation layer and protects the surface of the groove from being oxidized.
And the barrier metal 2 is formed on the barrier region through deposition, the barrier metal 2 is formed on the barrier region through evaporation or sputtering, and the barrier metal 2 is mainly Ti, Cr, Ni, Pt and NiPt alloy and has the function of forming a Schottky junction to play a rectifying role.
The front metal 1 is deposited on the barrier metal 2 and the oxide layer 4, and the front metal 1 is formed on the barrier metal 2 and the oxide layer 4 by evaporation or sputtering. The front metal 1 is arranged on the oxide layer 4 on the side wall of the groove close to the barrier region, and the other side wall and the bottom of the groove are not covered with the front metal 1. The front metal 1 is mainly Ti/Ni/Ag, Ti/Al/Ni/Ag or Ti/Al and is used as an electrode to encapsulate a welding surface, so that the front metal is conveniently connected with an external positive electrode or negative electrode, for example, the front metal is connected with the positive electrode when the front metal is in forward conduction, and the front metal is connected with the negative electrode when the front metal is in reverse cutoff.
The other side of the substrate is provided with a back metal 6, and the back metal 6 is prepared by a conventional wafer back processing technology. The back metal is used as an electrode to encapsulate the welding surface, so that the back metal can be conveniently connected with an external positive electrode or negative electrode.
The Schottky device structure is prepared by the following steps:
firstly, preparing a buffer layer on an epitaxial layer of a substrate material 5, wherein the thickness of the buffer layer is 500A-2000A, the buffer layer is prepared in a dry oxygen or wet oxygen mode, and the buffer layer is an oxide layer and mainly made of silicon dioxide; and depositing a mask layer on the buffer layer, wherein the thickness of the mask layer is 2000A-6000A, and the deposition mode can be chemical vapor deposition, including but not limited to low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition and plasma chemical vapor deposition. Preferably, the mask layer is silicon nitride. Coating photoresist on the mask layer, photoetching to form a pattern, etching the mask layer by adopting a dry etching process, and performing ion implantation with the dose of 1 × 1013～1*1016The dosage is determined by the pressure resistance;
and secondly, removing the photoresist, cleaning the wafer, removing impurities on the surface of the wafer, cleaning the surface of the wafer, pushing the wafer into a furnace tube, and growing a first oxidation layer on the upper surface of the substrate material 5, wherein the first oxidation layer is mainly silicon oxide.
And thirdly, etching the silicon in the protection ring area, wherein the PN junction 3 needs to be etched through during etching to form a groove, the groove depth of the groove is related to the advancing depth of the PN junction 3, and the groove depth is greater than the depth of the PN junction 3.
And fourthly, cleaning the wafer to clean impurities on the surface of the wafer, then putting the wafer into a furnace tube to push the wafer to grow an oxide layer 4, wherein the thickness of the oxide layer 4 is 2000-20000A, and the oxide layer 4 is silicon dioxide.
And fifthly, removing the mask layer, removing the silicon nitride of the mask layer by adopting phosphoric acid at 100-180 ℃ or a dry etching mode, and removing the oxide layer 4 of the barrier region by adopting a wet etching mode.
And sixthly, growing barrier metal 2 in the barrier region by evaporating or sputtering the barrier metal, wherein the barrier metal 2 is mainly Ti, Cr, Ni, Pt and NiPt alloy.
And seventhly, growing a front metal 1 on the barrier metal and the side wall of the groove by evaporating or sputtering the front metal, and photoetching to manufacture an electrode, wherein the front metal 1 is mainly Ti/Ni/Ag, Ti/Al/Ni/Ag or Ti/Al.
And eighthly, preparing back metal 6 on the other side surface of the substrate, wherein the back metal 6 is formed by a conventional wafer back processing technology, namely film pasting, thinning, corrosion, film uncovering, cleaning and back metallization to form the back metal.
The utility model has the advantages and positive effects that: one-time photoetching can be omitted, the size of a terminal structure is reduced, the Schottky contact area is enlarged, and a way is provided for effectively improving the power consumption of a device; one-time photoetching can be reduced in the process flow; the size of the terminal structure is reduced, the area of a potential barrier region is increased, the forward voltage drop is reduced, and a new way is provided for reducing the power consumption; if the area of the chip is not increased, the size of the chip can be reduced on the basis of the original device structure, and the number of the cores is increased (for example, the number of cores can be increased by 10% after the original 60mil chip uses a new device structure); firstly, the barrier area can be increased, and the power consumption is considered to be reduced; and the second method can increase the core number, improve the utilization rate of materials and reduce the production cost.
While one embodiment of the present invention has been described in detail, the present invention is only a preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. All the equivalent changes and improvements made according to the application scope of the present invention should still fall within the patent coverage of the present invention.
Claims (8)
1. A Schottky device structure characterized in that: comprising a substrate material comprising a substrate and an epitaxial layer, said epitaxial layer being provided on one side of said substrate, an
The groove is formed on the epitaxial layer in a photoetching mode;
the PN junction is formed on the side wall of the groove in an ion implantation mode and symmetrically arranged on the side wall of the groove;
the oxide layer covers the surface of the groove;
barrier metal deposited on the barrier region;
and the front metal is deposited on the barrier metal and the oxide layer.
2. The schottky device structure of claim 1 wherein: the cross section of the groove is U-shaped, and the groove is annular.
3. The schottky device structure of claim 2 wherein: the front metal is arranged on the oxide layer of the side wall of the groove close to the potential barrier region.
4. The schottky device structure of any one of claims 1 to 3 wherein: the thickness of the oxide layer is 2000A-20000A.
5. The schottky device structure of claim 4 wherein: the oxide layer is silicon dioxide.
6. The schottky device structure of claim 5 wherein: and the other side surface of the substrate is provided with back metal.
7. The schottky device structure of claim 5 or 6 wherein: the depth of the groove is greater than that of the PN junction.
8. The schottky device structure of claim 7 wherein: the PN junction is a P-type impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921026802.4U CN210110785U (en) | 2019-07-03 | 2019-07-03 | Schottky device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921026802.4U CN210110785U (en) | 2019-07-03 | 2019-07-03 | Schottky device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210110785U true CN210110785U (en) | 2020-02-21 |
Family
ID=69567941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921026802.4U Active CN210110785U (en) | 2019-07-03 | 2019-07-03 | Schottky device structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210110785U (en) |
-
2019
- 2019-07-03 CN CN201921026802.4U patent/CN210110785U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 300384 2nd floor, block a, 12 Haitai East Road, Huayuan Industrial Zone, Binhai New Area, Tianjin Patentee after: TCL Huanxin Semiconductor (Tianjin) Co.,Ltd. Country or region after: China Address before: 300384 2nd floor, block a, 12 Haitai East Road, Huayuan Industrial Zone, Binhai New Area, Tianjin Patentee before: TIANJIN HUANXIN TECHNOLOGY & DEVELOPMENT Co.,Ltd. Country or region before: China |