CN208478345U - A kind of high current low forward voltage drop SiC schottky diode chip - Google Patents
A kind of high current low forward voltage drop SiC schottky diode chip Download PDFInfo
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Abstract
This application provides a kind of high current low forward voltage drop SiC schottky diode chips, including back side stratiform metal electrode, positive stratiform metal electrode, ohmic contact layer, substrate, epitaxial layer one, epitaxial layer two, p-type protection ring, N-type ion implanted layer, Pt layers of schottky metal, cyclic annular passivation layer and cyclic oligoimides film；The application adulterates by using PN junction and schottky junction Parallel Design, two-layer epitaxial growth, ion implanting Nitrogen ion, generates big injection effect under high current using schottky metal Pt, reduce epilayer resistance rate, realize the production of low forward voltage drop Schottky diode under high current, low barrier metal and increase chip area is selected to increase device reverse leakage current while reducing device forward voltage drop in the prior art to overcome, device yield is reduced, the deficiency of manufacturing cost is increased.
Description
Technical field
The utility model relates to technical field of semiconductor device, more particularly, to a kind of high current low forward voltage drop silicon carbide
Schottky diode chip.
Background technique
SiC schottky diode based on semiconductor material with wide forbidden band compensates for silicon Schotty diode device not
Foot, the critical breakdown electric field intensity of 10 times of silicon materials ensures to work under higher backward voltage, while silicon carbide
Schottky diode have lower conducting resistance, quick switching characteristic and hot operation characteristic, make high-voltage high-speed,
Ideal component under the conditions of high temperature resistant and low-power consumption etc..SiC schottky diode can provide the dynamic property of near ideal,
There is no charge storage in the course of work, reverse recovery current is only caused by its depletion layer junction capacity, reverse recovery charge with
And its reverse recovery loss one to two orders of magnitude lower than silicon Ultrafast recovery diode.At normal temperature, silicon carbide schottky two
The conducting resistance of pole pipe has positive temperature coefficient, is conducive to multiple SiC schottky diodes are in parallel.In diode single
In the case where piece area and current limited, this can increase substantially the capacity of SiC schottky diode, make it larger
Application in capacity is possibly realized.
In traditional technology, Schottky diode selects low barrier metal and increases potential barrier area reduction forward voltage drop, but makes
With low barrier metal and increasing potential barrier area increases Schottky diode leakage current, and device junction temperature reduces；In the fabrication process
Increase layout size, one single chip size is bigger, and the probability for defect occur is bigger, is unfavorable for the raising of cost rate, influences device
Reliability and consistency；The chip area for increasing one single chip, reduce wafer goes out core number, increases device cost.
Therefore, how to overcome and select low barrier metal in the prior art and increase chip area in reduction device forward voltage drop
While increase device reverse leakage current, reduce device yield, the deficiency increased manufacturing cost is art technology
The problem of personnel's urgent need to resolve.
Utility model content
The utility model embodiment is designed to provide a kind of high current low forward voltage drop SiC schottky diode
Chip.
In order to solve the above technical problems, technical solution provided by the utility model are as follows:
A kind of high current low forward voltage drop SiC schottky diode chip, including back side stratiform metal electrode, front
Laminated metal electrode, ohmic contact layer, substrate, epitaxial layer one, epitaxial layer two, p-type protection ring, N-type ion implanted layer, Schottky
Pt metal layer, cyclic annular passivation layer and cyclic oligoimides film；
The back side stratiform metal electrode, ohmic contact layer, substrate, epitaxial layer one and epitaxial layer two are from the bottom up successively
It is superimposed, is provided with epitaxial layer one on the upper surface of the substrate, is provided with the epitaxial layer on the upper surface of the epitaxial layer one
Two, deposit is provided with the ohmic contact layer on the lower surface of the substrate, deposits and sets on the lower surface of the ohmic contact layer
It is equipped with the back side stratiform metal electrode；
P-type protection ring is provided with by ion implanting at the upper surface of the epitaxial layer two；
The epitaxial layer two and be located at the p-type protection ring ring in upper surface at by ion implanting be arranged
N-type ion implanted layer is stated, and the N-type ion implanted layer fills up the inner ring of the p-type protection ring；
The ring-type passivation layer is arranged on the upper surface of the epitaxial layer two and the lower cyclic annular table of the cyclic annular passivation layer
The inner ring in face covers the outer ring on the upper annular surface of the p-type protection ring；
Deposit is provided with described schottky metal Pt layers, and the Schottky on the upper surface of the N-type ion implanted layer
Pt metal layer fills up the inner ring of the cyclic annular passivation layer；
The front stratiform metal electrode is covered with schottky metal Pt layers of the upper surface and the cyclic annular passivation
The inner ring on the upper annular surface of layer；
The cyclic oligoimides film is covered with the upper surface of the positive stratiform metal electrode and the ring-type is passivated
The outer ring on the upper annular surface of layer and expose outside the positive stratiform metal electrode upper surface intermediate region.
Preferably, the p-type protection ring is Al ion doping p-type protection ring.
Preferably, the N-type ion implanted layer is Nitrogen ion doped N-type ion implanted layer.
Preferably, the positive stratiform metal electrode is Al metal layer or Au metal layer.
Preferably, the back side stratiform metal electrode includes the Ni metal layer and Ag metal layer being sequentially overlapped from top to bottom.
Preferably, the cyclic annular passivation layer is the mixture of silicon dioxide layer, silicon nitride layer or silica and silicon nitride
Layer.
Preferably, the ohmic contact layer is metal nickel layer, with a thickness of 200nm to 300nm.
This application provides a kind of high current low forward voltage drop SiC schottky diode chips, including back side stratiform gold
Belong to electrode, positive stratiform metal electrode, ohmic contact layer, substrate, epitaxial layer one, epitaxial layer two, p-type protection ring, N-type ion note
Enter layer, Pt layers of schottky metal, cyclic annular passivation layer and cyclic oligoimides film；
SiC schottky diode chip structure provided by the present application is made of PN junction and schottky junction, the phase from effect
When in parallel in PN junction and schottky junction, the forward voltage drop of Schottky diode is determined by schottky junction, Schottky diode just
To when conducting, the conduction voltage drop of schottky junction is less than the conduction voltage drop of PN junction, and schottky junction is preferentially connected, and PN junction diode is to Xiao
The forward voltage drop of special based diode without influence, the forward voltage drop of Schottky diode depend on barrier height at schottky junction,
Resistivity, epitaxy layer thickness and schottky junction junction area, the reverse biased of Schottky diode is determined by PN junction, reversed
When, PN junction increases the radius of curvature of Schottky diode edge depletion layer, weakens fringe field, improves two pole of Schottky
The reverse biased of pipe, the electrical resistivity and space-charge region that the reverse biased of Schottky diode depends at PN junction exhaust
Situation, the application is in the premise for not changing Schottky diode reverse biased (reverse biased is determined by the N- concentration at PN junction)
Under, change the epilayer resistance rate under schottky interface, reduces the forward voltage drop of Schottky diode；And use two-layer epitaxial
Growth, the doping of ion implanting low dosage Nitrogen ion generate big injection effect using the barrier metal in high complex centre under high current
It answers, reduces epilayer resistance rate, realize the production of low forward voltage drop Schottky diode under high current；It is existing to overcome
Have and low barrier metal and increase chip area is selected to increase device reverse leakage while reducing device forward voltage drop in technology
Stream reduces device yield, increases the deficiency of manufacturing cost.
Detailed description of the invention
Fig. 1 is a kind of high current low forward voltage drop SiC schottky diode core that the embodiments of the present invention provide
The structural schematic diagram of piece.
In figure: 1 back side stratiform metal electrode, 2 ohmic contact layers, 3 substrates, 4 epitaxial layers one, 5 epitaxial layers two, the protection of 6P type
Ring, 7N type ion implanted layer, 8 Pt layers of schottky metals, 9 positive stratiform metal electrodes, 10 cyclic annular passivation layers, 11 cyclic annular polyamides are sub-
Amine film.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is a part of the embodiment of the utility model, instead of all the embodiments.Based on the reality in the utility model
Apply example, those of ordinary skill in the art's every other embodiment obtained without making creative work, all
Belong to the range of the utility model protection.
In the description of the present invention, it should be understood that term " center ", " axial direction ", " radial direction ", " longitudinal direction ", " cross
To ", " length ", " width ", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outside", " clockwise ",
The orientation or positional relationship of the instructions such as " counterclockwise ", "vertical", "horizontal" is to be based on the orientation or positional relationship shown in the drawings, only
It is the utility model and simplified description for ease of description, rather than the device or element of indication or suggestion meaning must have spy
Fixed orientation is constructed and operated in a specific orientation, therefore should not be understood as limiting the present invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, also may include the first and second features be not direct contact but
Pass through the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
Fisrt feature is in the surface and oblique upper of second feature, or is merely representative of first feature horizontal height higher than second feature.
Fisrt feature includes fisrt feature in the underface of second feature and obliquely downward under the second feature " below ", " below " and " below "
Side, or first feature horizontal height is merely representative of less than second feature.
Referring to Fig.1, Fig. 1 is a kind of high current low forward voltage drop silicon carbide schottky that the embodiments of the present invention provide
The structural schematic diagram of diode chip for backlight unit.
This application provides a kind of high current low forward voltage drop SiC schottky diode chips, including back side stratiform gold
Belong to electrode 1, positive stratiform metal electrode 9, ohmic contact layer 2, substrate 3, epitaxial layer 1, epitaxial layer 25, p-type protection ring 6, N
Type ion implanted layer 7, schottky metal Pt layer 8, cyclic annular passivation layer 10 and cyclic oligoimides film 11；
The back side stratiform metal electrode 1, ohmic contact layer 2, substrate 3, epitaxial layer 1 and epitaxial layer 25 are from lower past
On be sequentially overlapped, epitaxial layer 1 is provided on the upper surface of the substrate 3, is arranged on the upper surface of the epitaxial layer 1
Epitaxial layer 25 is stated, is deposited on the lower surface of the substrate 3 and is provided with the ohmic contact layer 2, under the ohmic contact layer 2
Deposit is provided with the back side stratiform metal electrode 1 on surface；
P-type protection ring 6 is provided with by ion implanting at the upper surface of the epitaxial layer 25；
The epitaxial layer 25 and be located at the p-type protection ring 6 ring in upper surface at be provided with by ion implanting
The N-type ion implanted layer 7, and the N-type ion implanted layer 7 fills up the inner ring of the p-type protection ring 6；
The ring-type passivation layer 10 is arranged on the upper surface of the epitaxial layer 25 and the lower ring of the cyclic annular passivation layer 10
The inner ring on shape surface covers the outer ring on the upper annular surface of the p-type protection ring 6；
Deposit is provided with the schottky metal Pt layer 8, and the Xiao Te on the upper surface of the N-type ion implanted layer 7
Base Metal Pt layer 8 fills up the inner ring of the cyclic annular passivation layer 10；
The front stratiform metal electrode 9 be covered with the schottky metal Pt layer 8 upper surface and the ring-type it is blunt
Change the inner ring on the upper annular surface of layer 10；
The cyclic oligoimides film 11 be covered with the positive stratiform metal electrode 9 upper surface and the ring-type it is blunt
Change the outer ring on the upper annular surface of layer 10 and exposes outside the intermediate region of the upper surface of the positive stratiform metal electrode 9.
In one embodiment of the application, the p-type protection ring 6 is Al ion doping p-type protection ring.
In one embodiment of the application, the N-type ion implanted layer 7 is Nitrogen ion doped N-type ion implanted layer 7.
In one embodiment of the application, the front stratiform metal electrode 9 is Al metal layer or Au metal layer.
In one embodiment of the application, the back side stratiform metal electrode 1 includes the Ni being sequentially overlapped from top to bottom
Metal layer and Ag metal layer.
In one embodiment of the application, the ring-type passivation layer 10 is silicon dioxide layer, silicon nitride layer or titanium dioxide
The mixture layer of silicon and silicon nitride.
In one embodiment of the application, the ohmic contact layer 2 is metal nickel layer, with a thickness of 200nm to 300nm.
Present invention also provides a kind of preparations of above-mentioned high current low forward voltage drop SiC schottky diode chip
Method, comprising the following steps:
1) 3 growing epitaxial layers 1 of N-type silicon carbide substrates and epitaxial layer 25: substrate 3 is N-type carbofrax material, in institute
It states and grows epitaxial layer 1 on the upper surface of substrate 3, then grow epitaxial layer on the upper surface of the epitaxial layer 1 again
25；
The material of the epitaxial layer 1 is N-type carbofrax material, with a thickness of 0.5 μm to 2 μm, doping concentration 1017cm-3；
The material of the epitaxial layer 25 is N-type carbofrax material, with a thickness of 5 μm to 20 μm, doping concentration 1015cm-3；
2) grow oxide layer: thermal oxide goes out the oxidation of layer of silicon dioxide material on the upper surface of the epitaxial layer 25
Layer；
3) ion implanting p-type: then coating photoresist first makes P-doped zone domain by lithography using mask plate, then to institute
It states and carries out ion implanting formation p-type protection ring 6 at the upper surface of epitaxial layer 25；
4) ion implanting N-type: then coating photoresist first makes n-type doping region by lithography using mask plate, then to institute
Ion implanting, which is carried out, at upper surface that is stating epitaxial layer 25 and being located in the ring of the p-type protection ring 6 forms N-type ion injection
Layer 7；
5) activation annealing: after ion implanting, the oxide layer is removed first, then carries out activation annealing:
6) back surface ohmic contacts: metal is deposited on the back side of the substrate 3 and forms ohmic contact layer 2, then in hydrogen
Or it anneals in nitrogen atmosphere；
7) it deposits passivation layer: depositing passivation layer on the upper surface of the epitaxial layer 25, be then passivated again with dry etching
Layer pattern is to remove the passivation layer of schottky area；
8) splash-proofing sputtering metal potential barrier: Xiao is sputtered on the upper surface of the processing middleware obtained after the removal passivation layer of step 7)
Special Base Metal Pt；
9) it anneals: annealing in nitrogen and atmosphere of hydrogen after having sputtered schottky metal Pt, surface is removed after annealing
Unreacted Pt metal forms schottky metal Pt layer 8；
10) it deposits positive stratiform metal electrode 9: forming sediment on the upper surface of the processing middleware obtained after the annealing of step 9)
Product metal forms positive stratiform metal electrode 9；
11) it anti-carves metal electrode region: the positive stratiform metal electrode 9 is performed etching, by the positive stratiform gold
Outer make a circle for belonging to electrode 9 is etched away exposing passivation layer with forming region metal electrode；
12) it deposits back side stratiform metal electrode 1: depositing metal, shape on the back side of step 11) processing middleware obtained
At back side stratiform metal electrode 1；
13) coating polyimide film: polyamides is coated on the upper surface of the processing middleware obtained after the annealing of step 12)
The SiC schottky diode chip is made in imines film after the completion.
In one embodiment of the application, in step 3), the Doped ions of ion implanting are Al ion.
In one embodiment of the application, in step 4), ion implanting forms the Doped ions of N-type ion implanted layer 7
For Nitrogen ion, doping concentration is controlled 1016cm-3In range.
In step 1) in above-mentioned preparation method provided by the present application, the material of epitaxial layer 1 is N-type silicon carbide material
Material, with a thickness of 0.5 μm to 2 μm, doping concentration 1017cm-3, it is N-type semiconductor；
Epitaxial layer 25 is grown on epitaxial layer 1 so that for keeping out high pressure, the material of epitaxial layer 25 is N-type silicon carbide material
Material, with a thickness of 5 μm to 20 μm, doping concentration 1015cm-3, it is N-type semiconductor；
Depending on the thickness and doping concentration of epitaxial layer 1 and epitaxial layer 25 are according to device reverse biased actually required；
The prior art is made of one layer of single epitaxial layer, and the application is made of two layers of epitaxial layer, and epitaxial layer 1 is lining
The transition zone at bottom 3 and epitaxial layer 25, the device reverse biased of 25 doping concentration of epitaxial layer according to actual needs determine, extension
The thickness of layer 25 is 1 μm to 5 μm smaller than the thickness of common process epitaxial layer；
Epitaxial layer 1 is exactly that an intermediate concentration is adulterated between conventional expitaxial layer 25 and substrate 3 (N+ type semiconductor)
(concentration is about 10 in the area N17cm-3), the appropriate thickness for reducing epitaxial layer 25 forms P+N-NN+ structure, the electricity of PN junction interface
Field intensity is maximum, plays a decisive role to the reverse biased of device, and the electric field strength at substrate 3 gradually weakens, and changes lining
The doping concentration of epitaxial layer 1 is slightly larger than epitaxial layer 25 at bottom 3, and epitaxy layer thickness is controlled at 0.5 to 1 μm.Although the area N- is (outer
The decline of electric field can be generated under high current by prolonging layer 2 5), so that the voltage decline that the area N- is born, but due to epitaxial layer 1
In the presence of so that electric field increment of the space charge in the area N drift region is enough to make up and more than the loss amount of the area N- voltage, epitaxial layer one
4 presence can improve well the resistance to pressure of device, therefore can reduce epitaxial layer overall thickness, while the resistance of epitaxial layer 1
Rate is lower than the resistivity of epitaxial layer 25, so that its conduction voltage drop reduces；
Epitaxial layer 1 needs to meet following two condition, first is that epitaxy layer thickness is moderate, the area N- epitaxial thickness is lower than critical
Width is spreaded, punch-through breakdown occurs, guarantees that space-charge region broadening enters epitaxial layer 1；Second is that the concentration of epitaxial layer 1,
Concentration is unsuitable excessively high, guarantees that epitaxial layer 1 has conductivity modulation effect, also unsuitable too low, guarantees outside the not break-through of space-charge region
Prolong layer 1.
In step 2) in above-mentioned preparation method provided by the present application, using common process in the epitaxial layer 25
Thermal oxide goes out the oxide layer of layer of silicon dioxide material on upper surface, oxide layer with a thickness of 40nm to 80nm, as etching
The protective layer on barrier layer and ion implanting.
In step 3) in above-mentioned preparation method provided by the present application, due to Al ion have lower activationary temperature and
Low diffusion coefficient becomes most preferred Doped ions in p-type doping, and being used as termination environment formation p-type protection ring 6, (P+ type is partly led
Body), compare device gently to border extended in backward voltage electric field, weakens electric field and concentrate, improve the breakdown potential of device
Pressure.
In step 4) in above-mentioned preparation method provided by the present application, N-type ion implanted layer 7 is to form Schottky gesture
The Nitrogen ion doping that region carries out low dosage high-energy is built, doping concentration is controlled 1016cm-3In range, Xiao can be formed well
Te Ji effectively reduces the epilayer resistance rate below barrier region while contact；
N-type ion injection doping is carried out to the extension under schottky area, selects the N~+ implantation of low dosage high-energy,
So that device reverse breakdown voltage by PN junction doping concentration and field distribution determine, in the premise for not influencing device breakdown
Under, the extension concentration under schottky area is suitably increased, epilayer resistance rate is reduced, reduces forward voltage drop.
In step 5) in above-mentioned preparation method provided by the present application, the activation annealing temperature of silicon carbide is 1500 DEG C and arrives
1800 DEG C, to protect silicon carbide foreign ion not degenerate, one layer of carbon film protection first is generated in device surface before activation annealing,
The method that reusable heat aoxidizes after high annealing removes carbon film, with the oxide on diluted HF removal devices surface.
In step 6) in above-mentioned preparation method provided by the present application, metallic nickel is deposited on the back side of the substrate 3,
Then it anneals in hydrogen or nitrogen atmosphere, is arrived using conventional deposition method (sputtering or evaporation), such as evaporation 200nm
The Ni of 300nm thickness, then anneals in hydrogen atmosphere, and annealing temperature is 900 DEG C, and annealing time is 10 minutes, annealing
After remove unreacted W metal.
In step 7) in above-mentioned preparation method provided by the present application, the effect of passivation layer is to protect device surface
It is not stain by ion, improves the reliability of device.
In step 8) in above-mentioned preparation method provided by the present application, for herein, common process is typically chosen potential barrier
Lower Ti, Mo metal can reduce forward voltage drop, but can bring increased dramatically for electric leakage, and its amplitude for reducing forward voltage drop
Limited, the application selects Pt metal to do schottky metal thus, sputters thickness between 50nm to 100nm, under high current, choosing
Pt potential barrier is selected, due to the characteristic of conductance mediating effect+6 (Bulk current injection) and Pt barrier metal, forward voltage drop is instead than low gesture
Base metal it is smaller；
Pt metal forms complex centre in N-type silicon carbide at deep energy level, can effectively trapped electron and hole, platinum exist
Diffusion coefficient with higher in silicon carbide forms complex centre, effectively reduces the leakage current of device, and platinum diffuses to form
Displacement atom high-temperature stability it is good, there is good hot properties, complex centre accelerates the compound of electrons and holes,
Under high current, the concentration in non-equilibrium few sub (hole) in the area N- is injected near or above the concentration of the Qu Duozi (electronics), is
Holding electroneutral, the electronics (concentration of electronics) in the area N- accordingly increase equivalent amount, so that the area N- extension electron concentration is sent out
It is raw to change, the area N- resistivity is reduced, to further reduced the forward voltage drop of device.
In step 9) in above-mentioned preparation method provided by the present application, to improve the ideal factor of schottky metal and mentioning
The uniformity of high Schottky barrier is annealed after having sputtered schottky metal, and in nitrogen and atmosphere of hydrogen, annealing temperature is
It anneals 30 minutes at 535 DEG C, the barrier height of Pt metal is about 1.2eV under high current, and ideal factor is close to 1.
In step 10) in above-mentioned preparation method provided by the present application, positive stratiform metal electrode 9 is deposited: in step
9) metal electrode layer Al or Au are deposited on the upper surface of the processing middleware obtained after annealing, (is splashed using conventional deposition method
Penetrate or evaporate), for example the Al of 4 μ m thicks is evaporated, this layer of metal layer is used for bonding technology when die package.
In step 11) in above-mentioned preparation method provided by the present application, metal electrode region is anti-carved: to the positive layer
Shape metal electrode 9 performs etching, and outer make a circle of the positive stratiform metal electrode 9 is etched away exposing passivation layer to be formed
Compartmentalization metal electrode；The positive stratiform metal electrode 9 for etching metal Al material can use wet etching or dry etching, such as
With phosphoric acid wet etching Al.
In step 12) in above-mentioned preparation method provided by the present application, (sputters or evaporates) using conventional deposition method,
For example the Ag of 4 μ m thick of re-evaporation after the Ni of 0.5 μ m thick is evaporated, back side stratiform metal electrode 1 is used for weldering when die package
Connect technique.
In step 13) in above-mentioned preparation method provided by the present application, the thickness of polyimide film from 1 μm to 10 μm,
Polyimide film is negatively charged, can compensate SiO2In fixed positive charge；It can be to draw and as the final passivation layer of chip
The processing of the later process such as piece, frame, bonding provides the mechanical protection on surface, and polyimides membrane process is ripe for this field engineer
Know.
This application provides a kind of high current low forward voltage drop SiC schottky diode chips, including back side stratiform gold
Belong to electrode 1, positive stratiform metal electrode 9, ohmic contact layer 2, substrate 3, epitaxial layer 1, epitaxial layer 25, p-type protection ring 6, N
Type ion implanted layer 7, schottky metal Pt layer 8, cyclic annular passivation layer 10 and cyclic oligoimides film 11；
SiC schottky diode chip structure provided by the present application is made of PN junction and schottky junction, the phase from effect
When in parallel in PN junction and schottky junction, the forward voltage drop of Schottky diode is determined by schottky junction, Schottky diode just
To when conducting, the conduction voltage drop of schottky junction is less than the conduction voltage drop of PN junction, and schottky junction is preferentially connected, and PN junction diode is to Xiao
The forward voltage drop of special based diode without influence, the forward voltage drop of Schottky diode depend on barrier height at schottky junction,
Resistivity, epitaxy layer thickness and schottky junction junction area, the reverse biased of Schottky diode is determined by PN junction, reversed
When, PN junction increases the radius of curvature of Schottky diode edge depletion layer, weakens fringe field, improves two pole of Schottky
The reverse biased of pipe, the electrical resistivity and space-charge region that the reverse biased of Schottky diode depends at PN junction exhaust
Situation, the application is in the premise for not changing Schottky diode reverse biased (reverse biased is determined by the N- concentration at PN junction)
Under, change the epilayer resistance rate under schottky interface, reduces the forward voltage drop of Schottky diode；And use two-layer epitaxial
Growth, the doping of ion implanting low dosage Nitrogen ion generate big injection effect using the barrier metal in high complex centre under high current
It answers, reduces epilayer resistance rate, realize the production of low forward voltage drop Schottky diode under high current；It is existing to overcome
Have and low barrier metal and increase chip area is selected to increase device reverse leakage while reducing device forward voltage drop in technology
Stream reduces device yield, increases the deficiency of manufacturing cost.
The performance for the SiC schottky diode chip that embodiments herein provides and routine Xiao Te in the prior art
The comparing result of the performance of based diode is detailed in the following table 1.
The performance for the SiC schottky diode chip that 1 embodiments herein of table provides and conventional Xiao in the prior art
The comparing result of the performance of special based diode
The method and apparatus of the not detailed description of the utility model are the prior art, are repeated no more.
Specific embodiment used herein is expounded the principles of the present invention and embodiment, the above implementation
The explanation of example is merely used to help understand the method and its core concept of the utility model.It should be pointed out that for the art
Those of ordinary skill for, without departing from the principle of this utility model, can also to the utility model carry out it is several
Improvement and modification, modifications and modifications also fall within the protection scope of the claims of the utility model.
Claims (7)
1. a kind of high current low forward voltage drop SiC schottky diode chip, which is characterized in that including back side laminated metal
Electrode, positive stratiform metal electrode, ohmic contact layer, substrate, epitaxial layer one, epitaxial layer two, p-type protection ring, N-type ion injection
Layer, Pt layers of schottky metal, cyclic annular passivation layer and cyclic oligoimides film；
The back side stratiform metal electrode, ohmic contact layer, substrate, epitaxial layer one and epitaxial layer two are successively folded from the bottom up
Add, epitaxial layer one be provided on the upper surface of the substrate, the epitaxial layer two is provided on the upper surface of the epitaxial layer one,
Deposit is provided with the ohmic contact layer on the lower surface of the substrate, deposits and is provided on the lower surface of the ohmic contact layer
The back side stratiform metal electrode；
P-type protection ring is provided with by ion implanting at the upper surface of the epitaxial layer two；
The epitaxial layer two and the N is provided with by ion implanting at the upper surface that is located in the ring of the p-type protection ring
Type ion implanted layer, and the N-type ion implanted layer fills up the inner ring of the p-type protection ring；
The ring-type passivation layer is arranged on the upper surface of the epitaxial layer two and the lower annular surface of the cyclic annular passivation layer
Inner ring covers the outer ring on the upper annular surface of the p-type protection ring；
Deposit is provided with described schottky metal Pt layers, and the schottky metal on the upper surface of the N-type ion implanted layer
The Pt layers of inner ring for filling up the cyclic annular passivation layer；
The front stratiform metal electrode is covered with schottky metal Pt layer of the upper surface and the ring-type passivation layer
The inner ring on upper annular surface；
The cyclic oligoimides film be covered with the positive stratiform metal electrode upper surface and the cyclic annular passivation layer
The outer ring on upper annular surface and expose outside the positive stratiform metal electrode upper surface intermediate region.
2. SiC schottky diode chip according to claim 1, which is characterized in that the p-type protection ring is Al
Ion doping p-type protection ring.
3. SiC schottky diode chip according to claim 1, which is characterized in that the N-type ion implanted layer
For Nitrogen ion doped N-type ion implanted layer.
4. SiC schottky diode chip according to claim 1, which is characterized in that front laminated metal electricity
Extremely Al metal layer or Au metal layer.
5. SiC schottky diode chip according to claim 1, which is characterized in that the back side laminated metal electricity
Pole includes the Ni metal layer and Ag metal layer being sequentially overlapped from top to bottom.
6. SiC schottky diode chip according to claim 1, which is characterized in that the ring-type passivation layer is two
The mixture layer of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
7. SiC schottky diode chip according to claim 1, which is characterized in that the ohmic contact layer is gold
Belong to nickel layer, with a thickness of 200nm to 300nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821269958.0U CN208478345U (en) | 2018-08-07 | 2018-08-07 | A kind of high current low forward voltage drop SiC schottky diode chip |
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| CN201821269958.0U CN208478345U (en) | 2018-08-07 | 2018-08-07 | A kind of high current low forward voltage drop SiC schottky diode chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682695A (en) * | 2018-08-07 | 2018-10-19 | 济南晶恒电子有限责任公司 | A kind of high current low forward voltage drop SiC schottky diode chip and preparation method thereof |
| CN114023644A (en) * | 2021-10-29 | 2022-02-08 | 江苏索力德普半导体科技有限公司 | Fast recovery diode and preparation method thereof |
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2018
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682695A (en) * | 2018-08-07 | 2018-10-19 | 济南晶恒电子有限责任公司 | A kind of high current low forward voltage drop SiC schottky diode chip and preparation method thereof |
| CN108682695B (en) * | 2018-08-07 | 2023-12-22 | 济南晶恒电子有限责任公司 | High-current low-forward voltage drop silicon carbide Schottky diode chip and preparation method thereof |
| CN114023644A (en) * | 2021-10-29 | 2022-02-08 | 江苏索力德普半导体科技有限公司 | Fast recovery diode and preparation method thereof |
| CN114023644B (en) * | 2021-10-29 | 2024-02-23 | 江苏索力德普半导体科技有限公司 | Fast recovery diode and preparation method thereof |
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