JP5367332B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which reduces on-state resistance of an element by suppressing backward leakage current in a silicon carbide power semiconductor device having a diode with p-i-n and Schottky junctions. <P>SOLUTION: The method of manufacturing the semiconductor device includes the steps of: carrying out ion-implantation of p-type impurity in part of a region of a surface of a n-type epitaxial silicon carbide semiconductor layer disposed on the n-type silicon carbide semiconductor substrate so as to form a p-type impurity region; depositing a first metal layer for forming a Schottky barrier between n-type epitaxial silicon carbide semiconductor layeres, on the surface of the n-type epitaxial silicon carbide semiconductor layer; depositing a second metal layer for containing aluminum on the first metal layer; and annealing the second metal layer after the same is deposited. The annealing process allows the aluminum contained in the second metal layer to be selectively diffused to the p-type impurity region. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a silicon carbide power semiconductor device having a diode having a pin junction and a Schottky junction.

  In silicon carbide power semiconductor devices, impurity layers are widely formed by ion implantation. The junction barrier control Schottky structure to suppress leakage current due to the tunnel current from the Schottky interface in the reverse direction characteristic as well as the purpose of forming a breakdown voltage structure such as so-called junction termination, and hole injection on the high voltage side. The impurity ion implantation technique is also used to form a pin / Schottky mixed structure and the like that lower the on-resistance by performing a bipolar operation. In particular, a technique for implanting p-type impurity ions such as aluminum into an n-type semiconductor substrate and an n-type homoepitaxial layer thereon is essential.

In a power semiconductor device having a breakdown voltage of about 600 V, for example, in the case of a Schottky barrier diode using silicon carbide, the drift layer is formed with a relatively high carrier concentration of about 1 × 10 ¹⁶ cm ⁻³ and a relatively thin epitaxial layer of 10 μm or less. The layer is used as a drift layer. For this reason, it is easy to fabricate an element having a much lower on-resistance than a case where an element having a comparable breakdown voltage is realized by a conventional silicon pn diode. Therefore, the silicon carbide semiconductor device is mainly used in the junction barrier control Schottky structure provided for the purpose of suppressing the leakage current generated by the tunnel effect from the Schottky interface in the reverse characteristic, and in the high voltage region in the forward characteristic. In the conventional silicon, even if the resistance increase caused by current confinement occurs due to the formation of a pin / Schottky mixed structure that attempts to lower the on-resistance by bipolar operation by causing hole injection, Compared to power semiconductors, it was considered an acceptable range.

However, in recent years, power semiconductor devices intended to be mounted on a power unit such as a hybrid vehicle have come to require a 1200 V class element, and the drift layer is thicker than the 600 V class element, and the rise in drift layer resistance is increased. End up. For this reason, the structure causing the resistance increase due to the current confinement effect has become difficult to tolerate. For this reason, an example of shifting to a structure in which a p-layer is provided only for the Schottky end portion for the purpose of surge suppression has come to be seen. This is only an example, but various measures have been tried to come up with an approach to reduce the resistance of the substrate by thinning the substrate, and efforts to reduce the resistance are energetically promoted mainly by each research institution. (For example, Patent Document 1).
JP 2003-258271 A

  As described above, a reduction in loss by further reducing the on-resistance is also an essential issue in the silicon carbide semiconductor device, and there is a proposition of how to reduce the loss so as not to impair the characteristics of the semiconductor device. On the other hand, in order to achieve a stable low leakage current characteristic in the reverse direction characteristics with a high yield, the optimal trade-off relationship between breakdown voltage and on-resistance is controlled while controlling the Schottky barrier height to the minimum height. It is important to make it.

  However, until now there was something that aimed to improve the characteristics by the structure manufactured on the semiconductor side, but at the same time, there was hardly any idea to realize the low on-resistance of the element, and it was possible to obtain a semiconductor device with low on-resistance It has been considered difficult. For example, in order to form a conventional diode having a pin / Schottky mixed structure, the p-type impurity region is formed by aluminum ion implantation, so that the ohmic contact with the metal can be easily formed. Cannot be realized. In particular, the surface is roughened during the heat treatment for activating the implanted ion species, a leakage current path is formed at the grain boundary, and a high defect rate is inevitable. On the other hand, there has been a problem that a sufficiently low contact resistance cannot be obtained with a dose amount that does not cause surface roughness.

  The present invention has been made in view of the above circumstances, and its object is to suppress reverse leakage current in a silicon carbide power semiconductor device having a diode having a p-i-n junction and a Schottky junction. In addition, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that reduce the on-resistance of an element.

  In the method for manufacturing a semiconductor device according to the first aspect of the present invention, a p-type impurity is ion-implanted into a partial region of the surface of an n-type epitaxial silicon carbide semiconductor layer provided on an n-type silicon carbide semiconductor substrate. Forming a region; depositing a first metal layer forming a Schottky barrier between the n-type epitaxial silicon carbide semiconductor layer and the n-type epitaxial silicon carbide semiconductor layer; and Depositing a second metal layer containing aluminum on the metal layer, and a step of performing a heat treatment after the step of depositing the second metal layer, wherein the second metal layer is formed by the heat treatment. The contained aluminum is selectively diffused into the p-type impurity region.

  Here, in the first aspect, after the step of depositing the first metal layer, a step of selectively removing the first metal layer on the p-type impurity region, and the first metal layer A third metal layer having the same composition as the first metal layer is deposited on the first metal layer after the step of selectively removing the first metal layer and before the step of depositing the second metal layer. It is desirable to have the process of doing.

  Here, in the first aspect, it is desirable that the p-type impurity is aluminum.

  Here, in the first aspect, it is desirable that the first metal layer is formed of one metal selected from the group consisting of titanium, tungsten, molybdenum, nickel, or titanium silicide.

  A semiconductor device according to a second aspect of the present invention includes an n-type epitaxial silicon carbide semiconductor layer provided on an n-type silicon carbide semiconductor substrate, and a p-type formed on a part of the surface of the n-type epitaxial silicon carbide semiconductor layer. A first metal layer formed on the impurity region and the n-type epitaxial silicon carbide semiconductor layer, and forming a Schottky barrier between the n-type epitaxial silicon carbide semiconductor layer and the first metal layer; A second metal layer containing aluminum to be formed, and the thickness of the first metal layer on the p-type impurity region is the first metal on a region other than the p-type impurity region. It is characterized by being thinner than the thickness of the metal layer.

  Here, in the second aspect, the aluminum concentration at the interface between the n-type epitaxial silicon carbide semiconductor layer and the first metal layer is not more than the n-type carrier concentration in a region other than the p-type impurity region. Is desirable.

  Here, in the second aspect, it is desirable that the p-type impurity is aluminum.

  Here, in the second aspect, it is desirable that the first metal layer is formed of one metal selected from the group consisting of titanium, tungsten, molybdenum, nickel, or titanium silicide.

  Here, in the second aspect, it is desirable that the semiconductor device is a junction barrier Schottky diode or a pin / Schottky mixed diode.

  A semiconductor device according to a third aspect of the present invention includes an n-type epitaxial silicon carbide semiconductor layer provided on an n-type silicon carbide semiconductor substrate, and a p-type formed on a part of the surface of the n-type epitaxial silicon carbide semiconductor layer. A first metal layer formed on the impurity region and the n-type epitaxial silicon carbide semiconductor layer, and forming a Schottky barrier between the n-type epitaxial silicon carbide semiconductor layer and the first metal layer; A barrier metal layer formed between the first metal layer in a region other than the p-type impurity region and the second metal layer. It is characterized by being.

  Here, in the third aspect, the aluminum concentration at the interface between the n-type epitaxial silicon carbide semiconductor layer and the first metal layer is not more than the n-type carrier concentration in a region other than the p-type impurity region. Is desirable.

  Here, in the third aspect, it is desirable that the p-type impurity is aluminum.

  Here, in the third aspect, it is desirable that the first metal layer is formed of one metal selected from the group consisting of titanium, tungsten, molybdenum, nickel, or titanium silicide.

  Here, in the third aspect, it is desirable that the semiconductor device is a junction barrier Schottky diode or a pin / Schottky mixed diode.

  According to the present invention, in a silicon carbide power semiconductor device having a diode having a p-i-n junction and a Schottky junction, a method for manufacturing a semiconductor device that reduces the on-resistance of an element while suppressing reverse leakage current In addition, a semiconductor device can be provided.

  In general, titanium, tungsten, molybdenum, or the like is used as a Schottky electrode material formed on an n-type silicon carbide semiconductor. Further, when the anode electrode is mounted on the package by wire bonding or the like, it is desirable that the surface of the Schottky electrode material is covered with aluminum as the pad electrode material.

  The inventors have found a phenomenon in which the leakage current often increases in the reverse characteristics when the thickness of the Schottky electrode material is thin, and have conducted investigations to investigate the cause. As a result, when the thickness of the Schottky electrode material was thin, it was revealed by cross-sectional scanning electron microscope observation that aluminum diffused to the silicon carbide semiconductor surface through the Schottky electrode material. At this time, the silicon carbide semiconductor side is n-type, and it can be interpreted that the leakage current increases in the reverse characteristics because the Schottky barrier height is lowered. On the other hand, from the viewpoint of ohmic contact, the data could be interpreted so that a junction showing ohmic contact characteristics with low contact resistance was obtained.

  Therefore, in order not to deteriorate the reverse direction characteristics of the diode, the Schottky electrode material is rather thick so that it does not reach the silicon carbide semiconductor surface even if aluminum diffuses, and in particular, pin / shot. In the key mixed structure, in order to achieve both low contact resistance with the p-type silicon carbide semiconductor portion, the thickness of only the Schottky electrode material portion formed on the p-type silicon carbide semiconductor portion is reduced. It has been found that aluminum should reach the interface by diffusion.

  The present invention has been completed based on the above findings found by the inventors. Hereinafter, a semiconductor device manufacturing method and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
In the method of manufacturing a semiconductor device of the present embodiment, p-type impurities are ion-implanted into a partial region of the surface of an n-type epitaxial silicon carbide semiconductor layer provided on an n-type silicon carbide semiconductor substrate to form a p-type impurity region. And depositing a first metal layer that forms a Schottky barrier between the n-type epitaxial silicon carbide semiconductor layer including the p-type impurity region and the n-type epitaxial silicon carbide semiconductor layer other than the p-type impurity region. A step of depositing a second metal layer containing aluminum on the first metal layer, and a step of performing a heat treatment after the step of depositing the second metal layer. Then, the aluminum contained in the second metal layer is selectively diffused into the p-type impurity region by this heat treatment.

  1 to 9 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. Here, a description will be given by taking a breakdown voltage 3300 V class pin / Schottky mixed junction diode as an example of the semiconductor device.

First, as shown in FIG. 2, an n-type epitaxial silicon carbide semiconductor layer having a nitrogen concentration lower than that of the substrate 11 (hereinafter simply referred to as n-type epitaxial) is formed on the main surface of the (0001) plane n-type substrate 11 of 4H-silicon carbide. 12) (also referred to as a layer). A p-type ion implantation region (base region) 13 is formed in a part of the surface layer portion of the n-type epitaxial layer 12. This p-type ion implantation region (base region) 13 is formed by multi-stage ion implantation of aluminum, which is a p-type impurity. The impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more.

Further, a pattern of SiO ₂ 14 is formed above the outer periphery of the p-type ion implantation region 13. Thereafter, titanium 15a is deposited over the entire surface by, for example, sputtering so as to cover the SiO ₂ 14 and the n-type epitaxial layer 12 including the p-type ion implantation region 13.

  Next, as shown in FIG. 3, a photoresist 24 is applied on the titanium 15a employed as the Schottky electrode material. Then, after pre-baking, exposure is performed using a photomask, and after development, post-baking is performed. Here, the p-type ion implantation region 13 needs a fine pattern. For this reason, the process margin is severe due to the problem of mask alignment accuracy. Therefore, the photoresist 24 is designed to protrude into the p-type ion implantation region 13 in order to completely cover the portion without the p-type ion implantation region 13.

  Next, as shown in FIG. 4, the patterned photoresist 24 formed in this way is used as a mask material, and the titanium 15a where there is no photoresist is selectively etched away by wet etching. FIG. 5 is an enlarged schematic diagram of the dotted frame in FIG. As shown in the figure, the side etching of the titanium 15a occurs, but the titanium 15a remains immediately below the photomask resist 24.

  Then, as shown in FIG. 6, after the titanium 15a is left on the Schottky electrode surface by the above process, the photoresist 24 is removed.

  Next, as shown in FIG. 7, the titanium 15b is stacked on the titanium 15a.

  Thereafter, as shown in FIG. 8, aluminum 17 is deposited on titanium 15 having a partially laminated structure formed by deposition of titanium 15a and titanium 15b. FIG. 9 is an enlarged schematic diagram of the dotted frame in FIG.

  Next, as shown in FIG. 10, a photoresist 24 is coated on the aluminum 17, pre-baked, exposed using a photomask, developed, and post-baked. The patterned photoresist 24 thus formed is used as a mask material, and the aluminum 17 where there is no photoresist 24 is removed by, for example, acid treatment. Next, using the remaining aluminum as a mask material, for example, a reactive ion etching apparatus is used to etch the underlying titanium 15 to form a field plate.

  Thereafter, as shown in FIG. 1, a heat treatment for diffusing the aluminum 17 is performed in a nitrogen atmosphere at 300 ° C. to 350 ° C., for example, to form an aluminum diffusion titanium region 15 c in which aluminum is diffused in the titanium 15. The aluminum 17 is a pad electrode that serves as an anode electrode. Although not shown here, a cathode electrode is also provided on the n-type substrate 11 side by a known method, whereby a withstand voltage of 3300 V class pin / shot. A key mixed junction diode is manufactured.

  The heat treatment can also serve as a heat treatment for curing polyimide, for example.

  According to the method for manufacturing a semiconductor device of the present embodiment, aluminum diffuses into the interface between the p-type ion implantation region 13 and the titanium 15, thereby reducing the contact resistance in the p-type ion implantation region 13. Therefore, the on-resistance of the pin / Schottky mixed junction diode is reduced.

  On the other hand, the diffusion of aluminum to the interface between the n-type epitaxial layer 12 and the titanium 15 other than the p-type ion implantation region 13 is suppressed. The aluminum concentration at this interface is equal to or lower than the n-type carrier concentration. Therefore, the height of the Schottky barrier is not changed, and an increase in reverse leakage current and a change in on-voltage are not caused.

  As a result of trial manufacture of the device by the above manufacturing method, even if the aluminum 17 itself is not in contact with the silicon carbide epitaxial layer surface 12, it is sufficient that it is in contact as the aluminum diffusion titanium region 15c in which aluminum is diffused. As a result of the correspondence between the device characteristic measurement and the cross-sectional microscope observation, it was found that ohmic contact was formed without any problem between the type ion implantation region 13 and the Schottky electrode material, and a low on-resistance device was obtained.

  In particular, it operates as a Schottky diode in a low voltage state where hole injection does not occur, the Schottky barrier height does not change, and the on-state voltage is comparable to that of a normal Schottky barrier diode. . In a voltage range where bipolar operation occurs, a comparison of characteristics with a conventional device having the same withstand voltage that does not have the structure of the present invention has resulted in an improvement of about 15% in on-resistance.

  In the semiconductor device of the present embodiment shown in FIG. 1, the thickness of titanium 15 on p-type ion implantation region 13 is smaller than the thickness of titanium 15 on regions other than on p-type ion implantation region 13. Yes. In addition, the aluminum concentration at the interface between the n-type epitaxial layer 12 and the titanium 15 other than the p-type ion implantation region 13 is equal to or lower than the n-type carrier concentration. As a result, a good Schottky junction is formed between the n-type epitaxial layer 12 other than the p-type ion implantation region 13 and the titanium 15.

  As a result, a semiconductor device that reduces the on-resistance of the element while suppressing the reverse leakage current is realized.

  Here, although titanium has been described as an example of the Schottky electrode material, any metal that forms a Schottky barrier with the n-type epitaxial silicon carbide semiconductor layer, such as tungsten, molybdenum, nickel, or titanium silicide, Other metals can also be applied.

  In addition, the material for the pad electrode has been described by taking aluminum alone as an example, but other metals such as an alloy of aluminum and copper, an alloy of aluminum, copper and silicon, and the like can be used as long as the metal contains aluminum. It is also possible.

(Second Embodiment)
The semiconductor device and manufacturing method of the present embodiment apply the semiconductor device and manufacturing method of the first embodiment to a junction barrier Schottky diode. The difference in structure from the semiconductor device of the first embodiment is that the concentration of the p-type ion implantation region 13 is about 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ in the first embodiment. The point is that the concentration is low compared to the form. Hereinafter, the description overlapping with the first embodiment is omitted.

  According to the method for manufacturing a semiconductor device of the present embodiment, aluminum diffuses into the interface between the p-type ion implantation region 13 and the titanium 15, thereby reducing the contact resistance in the p-type ion implantation region 13. Therefore, the on-resistance of the junction barrier Schottky diode is reduced.

  Of course, introducing a large area of the p-type ion implantation region into the Schottky junction may narrow the current path and increase the resistance. Therefore, measures are taken in which nitrogen ions are previously implanted as counter ion implantation on the surface of the n-type epitaxial layer without the p-type ion implantation region, and the carrier concentration is increased so as to cancel the increase in resistance of the current confinement portion. It is desirable.

  The device was fabricated by performing the above manufacturing method and nitrogen counter ion implantation. As a result, the reverse leakage current can be suppressed to a value that does not cause a problem even at a high temperature of about 175 ° C. as compared with the conventional device having the same breakdown voltage. In addition, it is possible to achieve both the rise voltage as the forward characteristic as low as the Schottky diode and the on-resistance as low as the p-i-n diode.

  The semiconductor device of this embodiment has the same structure as that of FIG. 1 of the first embodiment except for the concentration of the p-type ion implantation region. The thickness of the titanium 15 on the p-type ion implantation region 13 is smaller than the thickness of the titanium 15 on the region other than on the p-type ion implantation region 13. In addition, the aluminum concentration at the interface between the n-type epitaxial layer 12 and the titanium 15 other than the p-type ion implantation region 13 is equal to or lower than the n-type carrier concentration.

  As a result, the semiconductor device that reduces the on-resistance of the element while suppressing the reverse leakage current is realized as in the first embodiment.

  In this case as well, titanium has been described as an example of the Schottky electrode material. However, other metal materials such as tungsten and molybdenum can be applied as in the first embodiment. However, since the Schottky barrier height changes with each metal, it is necessary to adjust design matters such as the interval between the p-type ion implantation regions, but titanium is not essential to obtain the same effect.

(Third embodiment)
The semiconductor device and the manufacturing method of the present embodiment are a Schottky diode having a structure in which a p-type ion implantation region is provided only at the Schottky end portion for the purpose of surge suppression, and a manufacturing method thereof.

  FIG. 11 is a cross-sectional view of the semiconductor device of this embodiment. The structural difference from the first embodiment shown in FIG. 1 is that a p-type ion implantation region 13 is provided only at the Schottky end. Accordingly, the description overlapping with the first embodiment is omitted.

  According to the Schottky diode of this embodiment, the p-type ion implantation region 13 at the Schottky end portion has a surge countermeasure effect. Further, the on-resistance of the element can be reduced by reducing the interface resistance between the p-type ion implantation region 13 and the titanium 15.

(Fourth embodiment)
The semiconductor device manufacturing method and the semiconductor device according to the present embodiment are characterized in that diffusion of aluminum from the pad electrode material is controlled by providing a barrier metal layer between the Schottky electrode material and the pad electrode material. And Hereinafter, the description overlapping with the first and second embodiments, such as selection of processes and materials, is omitted.

  12 to 15 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. Here, as a semiconductor device, a junction barrier Schottky diode will be described as an example as in the second embodiment.

  First, as shown in FIG. 12, a large number of p-type ion implantation regions 13 are formed in a Schottky junction, and then titanium 15 is formed as a Schottky electrode.

  Next, as shown in FIG. 13, tantalum nitride 16 is formed as a barrier metal layer on titanium 15. Any metal other than tantalum nitride can be used as long as it is a metal that serves as a barrier against aluminum diffusion. Next, a photoresist is applied, pre-baked, exposed using a photomask, developed, and post-baked. The patterned photoresist 24 formed in this way is designed to protrude into the p-type ion implantation region 13 in order to completely cover the portion without the p-type ion implantation region 13.

  Next, as shown in FIG. 14, the tantalum nitride 16 is etched by wet etching using the photoresist 24 as a mask. And after removing the photomask resist 24, the aluminum 17 used as a pad electrode material is formed. Thereafter, aluminum 17, tantalum nitride 16, and titanium 15 are etched to produce a field plate (not shown).

  Thereafter, as shown in FIG. 15, heat treatment for causing diffusion of aluminum is performed. Thereby, an aluminum diffusion titanium region 15c in which aluminum is diffused in the titanium 15 is formed. At this time, diffusion of aluminum to the n-type epitaxial layer 12 other than the p-type ion implantation region 13 is suppressed by the tantalum nitride 16 which is a barrier metal layer.

  According to the method for manufacturing a semiconductor device of the present embodiment, aluminum diffuses into the interface between the p-type ion implantation region 13 and the titanium 15, thereby reducing the contact resistance in the p-type ion implantation region 13. Therefore, the on-resistance of the junction barrier Schottky diode is reduced.

  In the semiconductor device of the present embodiment shown in FIG. 15, tantalum nitride 16 is formed between titanium 15 in a region other than on p-type ion implantation region 13 and aluminum 17. In addition, the aluminum concentration at the interface between the n-type epitaxial layer 12 and the titanium 15 other than the p-type ion implantation region 13 is equal to or lower than the n-type carrier concentration.

  As a result, the semiconductor device that reduces the on-resistance of the element while suppressing the reverse leakage current is realized as in the second embodiment.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. In the description of the embodiments, the description of the semiconductor device manufacturing method, the semiconductor device, etc., which is not directly necessary for the description of the present invention is omitted, but the required semiconductor device manufacturing method, Elements related to the semiconductor device and the like can be appropriately selected and used.

  In addition, all semiconductor device manufacturing methods and semiconductor devices that include the elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is sectional drawing of the semiconductor device of 3rd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment.

Explanation of symbols

11 n-type substrate 12 n-type epitaxial layer 13 p-type ion implantation region 14 SiO ₂
15, 15a, 15b Schottky electrode material (titanium)
15c Aluminum diffusion titanium region 16 Barrier metal (tantalum nitride)
17 Pad electrode material (aluminum)
24 photoresist

Claims (3)

a step of ion-implanting p-type impurities into a partial region of the surface of an n-type epitaxial silicon carbide semiconductor layer provided on the n-type silicon carbide semiconductor substrate to form a p-type impurity region;
Depositing a first metal layer that forms a Schottky barrier between the n-type epitaxial silicon carbide semiconductor layer and the n-type epitaxial silicon carbide semiconductor layer;
Depositing a second metal layer containing aluminum on the first metal layer;
And a heat treatment step after the step of depositing the second metal layer,
The aluminum contained in the second metal layer is selectively diffused into the p-type impurity region by the heat treatment ,
Selectively removing the first metal layer on the p-type impurity region after the step of depositing the first metal layer;
After the step of selectively removing the first metal layer and before the step of depositing the second metal layer, a first layer having the same composition as the first metal layer is formed on the first metal layer. the method of manufacturing a semiconductor device according to claim Rukoto that having a step of depositing a third metal layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the p-type impurity is aluminum. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal layer is formed of one metal selected from the group consisting of titanium, tungsten, molybdenum, nickel, or titanium silicide. .

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