CN105990134B - A method of making diode - Google Patents
A method of making diode Download PDFInfo
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- CN105990134B CN105990134B CN201510041382.7A CN201510041382A CN105990134B CN 105990134 B CN105990134 B CN 105990134B CN 201510041382 A CN201510041382 A CN 201510041382A CN 105990134 B CN105990134 B CN 105990134B
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Abstract
The embodiment of the invention discloses a kind of methods for making diode.In the above embodiment of the present invention, oxide layer is grown on epitaxial layer；Chemical wet etching is carried out to the oxide layer, at least etches away the oxide layer of the corresponding trench region of field limiting ring；Mask layer is grown, and chemical wet etching is carried out to the mask layer, forms the side wall of the oxide layer；Etching groove is carried out to the region of the adjacent oxidation interlayer, forms the corresponding groove of the field limiting ring；The side wall for removing the oxide layer carries out ion implanting to the corresponding groove of the field limiting ring；Dielectric layer, front metal layer are successively made in the epitaxial layer；Metal layer on back is made in substrate back.The embodiment of the present invention is by the way that in the side wall for forming oxide layer, excessively high light exposure causes ring region knot pattern to change during effectively preventing prior art production current regulator diode, and depletion region is uneven, the technical issues of device resistance to drops.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field more particularly to a kind of methods for making diode.
Background technique
Current regulator diode is semiconductor constant current device, it can export constant electric current in very wide voltage range, and have
There is very high motional impedance.Due to their constant current performance is good, price is lower, using simplicity, have been widely used at present
In LED component.Current regulator diode and LED have good matching, and can protect LED from due to overcurrent, overvoltage,
Periphery caused by the variation of cycle is destroyed.Therefore, it has broad application prospects.
Currently, current regulator diode improves pressure resistance, Ci Zhongfang generally by the way of field limiting ring and addition Metal field plate
Formula ring region depletion region is influenced very big by p-well injection (including p-well photoetching, p-well injection etc.).It hardly results in uniform depletion region
Field limiting ring.It is as follows to make current regulator diode main flow: as shown in Figure 1, forming groove in N-type epitaxy layer；Such as Fig. 2 institute
Show, completes p-well photoetching and development.In order to guarantee that device has enough pressure resistances, on ring region surface, trenched side-wall position, after development
The photoresist left has to guarantee that p-well has enough Injection Spaces to inside contracting.However, since this step is deep trouth photoetching, deep trouth
For the area Xian Kai, therefore while exposing, must add enough light exposures, but excessively high light exposure will will lead to ring region photomask surface glue
Pattern changes (glue sidewall profile is poor), this will directly affect p-well injection, eventually leads to the variation of ring region knot pattern, exhausts
Area is uneven, the resistance to drops of device.
Summary of the invention
The present invention is provided according to a kind of method for making diode, to solve the process of prior art production current regulator diode
In excessively high light exposure cause ring region knot pattern to change, the technical issues of depletion region is uneven, device resistance to drops.
A kind of method making diode provided in an embodiment of the present invention, comprising:
Oxide layer is grown on epitaxial layer；
Chemical wet etching is carried out to the oxide layer, at least etches away the oxide layer of the corresponding trench region of field limiting ring；
Mask layer is grown, and chemical wet etching is carried out to the mask layer, forms the side wall of the oxide layer；
Etching groove is carried out to the region of the adjacent oxidation interlayer, forms the corresponding groove of the field limiting ring；
The side wall for removing the oxide layer carries out ion implanting to the corresponding groove of the field limiting ring；
Dielectric layer, front metal layer are successively made in the epitaxial layer；
Metal layer on back is made in substrate back.
Preferably, carrying out chemical wet etching to the oxide layer, the oxidation of the corresponding trench region of field limiting ring is at least etched away
Layer, further includes:
Etch away the oxide layer of the corresponding trench region of active area；
Etching groove is carried out to the region of the adjacent oxidation interlayer, further includes:
Form the corresponding groove of the active area.
Preferably, carrying out chemical wet etching to the oxide layer, the oxidation of the corresponding trench region of field limiting ring is at least etched away
Layer, further includes:
Etch away the oxide layer of active area region；
Mask layer is grown, and chemical wet etching is carried out to the mask layer, further includes:
The mask layer for etching away the corresponding trench region of active area forms the mask layer of the active area；
Etching groove is carried out in the exposure mask interlayer of the adjacent active area, forms the corresponding groove of the active area.
Preferably, the mask layer is silicon nitride, remove the side wall of the oxide layer using wet process.
Preferably, covering the mask layer of the active area with photoresist before the side wall for removing the oxide layer.
Preferably, the epitaxial layer is N-type epitaxy layer, the ion is P-type ion；Or
The epitaxial layer is p-type epitaxial layer, and the ion is N-type ion.
In the above embodiment of the present invention, oxide layer is grown on epitaxial layer；Chemical wet etching is carried out to the oxide layer, until
The oxide layer of the corresponding trench region of eating away field limiting ring after a little while；Mask layer is grown, and chemical wet etching, shape are carried out to the mask layer
At the side wall of the oxide layer；Etching groove is carried out to the region of the adjacent oxidation interlayer, it is corresponding to form the field limiting ring
Groove；The side wall for removing the oxide layer carries out ion implanting to the corresponding groove of the field limiting ring；The epitaxial layer according to
Secondary production dielectric layer, front metal layer；Metal layer on back is made in substrate back.The embodiment of the present invention is by forming oxide layer
Side wall, excessively high light exposure causes ring region knot pattern to become during effectively preventing prior art production current regulator diode
Change, the technical issues of depletion region is uneven, device resistance to drops.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1-Fig. 2 is the production method flow chart of prior art diode；
Fig. 3 is a kind of production method flow chart of diode provided in an embodiment of the present invention；
Fig. 4-Figure 10 is the structural schematic diagram in a kind of manufacturing process of diode provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
As shown in figure 3, being a kind of production method of diode provided in an embodiment of the present invention, this method includes following step
It is rapid:
Step 301, oxide layer is grown on epitaxial layer；
Step 302, chemical wet etching is carried out to the oxide layer, at least etches away the oxidation of the corresponding trench region of field limiting ring
Layer；
Step 303, mask layer is grown, and chemical wet etching is carried out to the mask layer, forms the side wall of the oxide layer；Its
In, mask layer can be silicon nitride, silica.
Step 304, etching groove is carried out to the region of the adjacent oxidation interlayer, forms the corresponding ditch of the field limiting ring
Slot；
Step 305, the side wall for removing the oxide layer carries out ion implanting to the corresponding groove of the field limiting ring；
Step 306, dielectric layer, front metal layer are successively made in the epitaxial layer；Back metal is made in substrate back
Layer.
In the present embodiment, substrate is N-type substrate, then epitaxial layer is the N-type silicon chip being grown in N-type substrate, substrate P
Type substrate, then epitaxial layer is the P-type wafer being grown in P type substrate, is determined with specific reference to the design of device.If epitaxial layer is
N-type epitaxy layer, the then ionic type injected are p-type；If epitaxial layer is p-type epitaxial layer, the ionic type injected is N-type.
Diode in the embodiment of the present invention includes termination environment and active area, and wherein termination environment includes field limiting ring.
For a clearer understanding of the present invention, it is described in detail combined with specific embodiments below.
Embodiment one
Using epitaxial layer as N-type epitaxy layer, the ionic type of injection is to be introduced for p-type.
In above-mentioned steps 301, grown epitaxial layer, the structure that oxide layer is generated on epitaxial layer are as shown in Figure 4 on substrate.
In this step, oxide layer can be conventional silica.
Above-mentioned steps 302, are laid with photoresist in oxide layer, carry out lithography and etching to oxide layer, the structure of formation is such as
Shown in Fig. 5.
Above-mentioned steps 303, one layer of silicon nitride of growth deposit, the structure of formation are as shown in Figure 6 in oxide layer；To the nitrogen
SiClx layer carries out lithography and etching, and the structure for forming the side wall of oxide layer is as shown in Figure 7.
Above-mentioned steps 304 carry out etching groove to the region of the adjacent oxidation interlayer, it is corresponding to form the field limiting ring
Groove structure it is as shown in Figure 8.
Above-mentioned steps 305 cover the mask layer of the active area with photoresist, remove the side of the oxide layer using wet process
Wall, the structure of formation is as shown in figure 9, carry out ion implanting to the corresponding groove of the field limiting ring；Ion note is carried out in this step
Fashionable, the energetic ion of injection can be boron ion, and the technological parameter in specific implementation process can be according to specific diode structure
It is selected, the embodiment of the present invention provides a kind of common technological parameter: implantation dosage is usually 1E15-5E15/cm2, note
Enter energy may respectively be Implantation Energy should be between 200KEV-500KEV.Preferably, it is for the first time 450KEV, is for the second time
350KEV is for the third time 250KEV.Specific Implantation Energy is related with product design.Driving in temperature is about 1150 DEG C.
Above-mentioned steps 306 successively make dielectric layer, front metal layer, the structure of formation such as Figure 10 institute in the epitaxial layer
Show；Dielectric layer is silica and phosphorosilicate glass, and the temperature for forming dielectric layer is usually 880-950 DEG C, and thickness is about 1 μm；Just
Face metal is usually aluminium, silicon, copper alloy, with a thickness of 3-4um or so.Metal layer on back is made in substrate back, in this step
Back process include substrate thinning, the back side injection P ion, metal layer on back make three kinds of techniques, generally use mechanical lapping
Mode carry out substrate thinning；Substrate back injects P ion, and substrate and metal layer on back is made to form Ohmic contact, back metal
Layer is usually titanium, nickel, silver-colored three-layer metal film, can use vapor deposition or the production of the method for sputtering, wherein the thickness of first layer titanium
Usually 1000A, metallic film titanium and silicon substrate form silicide and guarantee that contact performance is good, and second layer nickel is adhesion layer,
Thickness is usually 2000A, and third layer is silver metal film, thickness about 1um, guarantee subsequent routing and etc. do not go wrong.
Embodiment two
Using epitaxial layer as N-type epitaxy layer, the ionic type of injection is to be introduced for p-type.
In above-mentioned steps 301, grown epitaxial layer, generates oxide layer on epitaxial layer on substrate.In this step, oxide layer
It can be conventional silica.
Above-mentioned steps 302, are laid with photoresist in oxide layer, carry out lithography and etching to oxide layer, and etched away
The oxide layer of the corresponding trench region of source region.
Above-mentioned steps 303, one layer of silicon nitride of growth deposit in oxide layer, carry out photoetching and quarter to the silicon nitride layer
Erosion, forms the side wall of oxide layer.
Above-mentioned steps 304 carry out etching groove to the region of the adjacent oxidation interlayer, it is corresponding to form the field limiting ring
Groove and the corresponding groove of active area.
Above-mentioned steps 305 remove the side wall of the oxide layer using wet process, and the structure of formation is as shown in figure 8, to the field
It limits the corresponding groove of ring and carries out ion implanting；When carrying out ion implanting in this step, the energetic ion of injection can be boron ion, tool
Technological parameter in body implementation process can be selected according to specific diode structure, and the embodiment of the present invention provides a kind of common
Technological parameter: implantation dosage is usually 1E15-5E15/cm2, and Implantation Energy, which may respectively be Implantation Energy, to be
Between 200KEV-500KEV.It preferably, is for the first time 450KEV, it is for the third time 250KEV that second, which is 350KEV,.Specifically
Implantation Energy is related with product design.Driving in temperature is about 1150 DEG C.
Above-mentioned steps 306 successively make dielectric layer, front metal layer in the epitaxial layer；Dielectric layer be silica and
Phosphorosilicate glass, the temperature for forming dielectric layer is usually 880-950 DEG C, and thickness is about 1 μm；Front metal is usually aluminium, silicon, copper conjunction
Gold, with a thickness of 3-4um or so.Substrate back make metal layer on back, back process in this step include substrate thinning,
P ion is injected at the back side, metal layer on back makes three kinds of techniques, and the mode for generalling use mechanical lapping carries out substrate thinning；Substrate
P ion is injected at the back side, and substrate and metal layer on back is made to form Ohmic contact, and metal layer on back is usually titanium, nickel, silver-colored three-layer metal
Film, can be using vapor deposition or the production of the method for sputtering, wherein the thickness of first layer titanium is usually 1000A, metallic film titanium and
Silicon substrate forms silicide and guarantees that contact performance is good, and second layer nickel is adhesion layer, and thickness is usually 2000A, and third layer is
Silver metal film, thickness about 1um, guarantee subsequent routing and etc. do not go wrong.
It can be seen from the above: in the above embodiment of the present invention, oxide layer is grown on epitaxial layer；To the oxygen
Change layer and carry out chemical wet etching, at least etches away the oxide layer of the corresponding trench region of field limiting ring；Mask layer is grown, and is covered to described
Film layer carries out chemical wet etching, forms the side wall of the oxide layer；Etching groove is carried out to the region of the adjacent oxidation interlayer,
Form the corresponding groove of the field limiting ring；The side wall for removing the oxide layer carries out ion to the corresponding groove of the field limiting ring
Injection；Dielectric layer, front metal layer are successively made in the epitaxial layer；Metal layer on back is made in substrate back.The present invention is real
Example is applied by effectively preventing excessively high exposure during prior art production current regulator diode in the side wall for forming oxide layer
The technical issues of amount causes ring region knot pattern to change, and depletion region is uneven, device resistance to drops.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (6)
1. a kind of method for making diode characterized by comprising
Oxide layer is grown on epitaxial layer；
Chemical wet etching is carried out to the oxide layer, at least etches away the oxide layer of the corresponding trench region of field limiting ring；
Mask layer is grown, and chemical wet etching is carried out to the mask layer, forms the side wall of the oxide layer；
Etching groove is carried out to the region of the adjacent oxidation interlayer, forms the corresponding groove of the field limiting ring；
The side wall for removing the oxide layer carries out ion implanting to the corresponding groove of the field limiting ring；
Dielectric layer, front metal layer are successively made in the epitaxial layer；
Metal layer on back is made in substrate back.
2. the method as described in claim 1, which is characterized in that carry out chemical wet etching to the oxide layer, at least etch away field
Limit the oxide layer of the corresponding trench region of ring, further includes:
Etch away the oxide layer of the corresponding trench region of active area；
Etching groove is carried out to the region of the adjacent oxidation interlayer, further includes:
Form the corresponding groove of the active area.
3. the method as described in claim 1, which is characterized in that carry out chemical wet etching to the oxide layer, at least etch away field
Limit the oxide layer of the corresponding trench region of ring, further includes:
Etch away the oxide layer of active area region；
Mask layer is grown, and chemical wet etching is carried out to the mask layer, further includes:
The mask layer for etching away the corresponding trench region of active area forms the mask layer of the active area；
Etching groove is carried out in the exposure mask interlayer of the adjacent active area, forms the corresponding groove of the active area.
4. the method as described in claim 1, which is characterized in that the mask layer is silicon nitride, removes the oxygen using wet process
Change the side wall of layer.
5. method as claimed in claim 4, which is characterized in that before the side wall for removing the oxide layer, cover with photoresist
The mask layer of active area.
6. method according to any one of claims 1 to 5, which is characterized in that the epitaxial layer be N-type epitaxy layer, it is described from
Son is P-type ion；Or
The epitaxial layer is p-type epitaxial layer, and the ion is N-type ion.
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| CN201510041382.7A CN105990134B (en) | 2015-01-27 | 2015-01-27 | A method of making diode |
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| CN201510041382.7A CN105990134B (en) | 2015-01-27 | 2015-01-27 | A method of making diode |
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| CN110783189A (en) * | 2019-09-23 | 2020-02-11 | 珠海格力电器股份有限公司 | Preparation method of chip groove and preparation method of chip |
| CN110556431B (en) * | 2019-09-29 | 2024-03-08 | 宁波铼微半导体有限公司 | Vertical conduction gallium nitride power diode and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100078754A1 (en) * | 2008-09-30 | 2010-04-01 | John Victor Veliadis | Guard ring structures and method of fabricating thereof |
| CN101740515B (en) * | 2008-11-14 | 2014-01-08 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN104103519A (en) * | 2013-04-11 | 2014-10-15 | 茂达电子股份有限公司 | Method for manufacturing semiconductor power device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USH204H (en) * | 1984-11-29 | 1987-02-03 | At&T Bell Laboratories | Method for implanting the sidewalls of isolation trenches |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100078754A1 (en) * | 2008-09-30 | 2010-04-01 | John Victor Veliadis | Guard ring structures and method of fabricating thereof |
| CN101740515B (en) * | 2008-11-14 | 2014-01-08 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN104103519A (en) * | 2013-04-11 | 2014-10-15 | 茂达电子股份有限公司 | Method for manufacturing semiconductor power device |
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Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 5 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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