CN111384154A - Radiation-resistant bipolar device - Google Patents

Radiation-resistant bipolar device Download PDF

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CN111384154A
CN111384154A CN202010241064.6A CN202010241064A CN111384154A CN 111384154 A CN111384154 A CN 111384154A CN 202010241064 A CN202010241064 A CN 202010241064A CN 111384154 A CN111384154 A CN 111384154A
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silicon dioxide
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radiation
field plate
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翟亚红
杨峰
李珍
李威
张国俊
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract

An anti-irradiation bipolar device relates to the electronic device technology. The semiconductor device comprises a semiconductor region, an insulating medium region and an electrode, wherein the insulating medium region and the electrode are arranged above the semiconductor region, the semiconductor region comprises a base region, an emitter region and a P + ohmic contact region which are arranged in a substrate, and a region between the emitter region and the P + ohmic contact region is a spacer region; an anti-irradiation reinforcing layer with the thickness of 20-80 nm is further arranged between the insulating medium region and the upper surface of the semiconductor region, and the material of the anti-irradiation reinforcing layer comprises silicon dioxide; a conductive field plate parallel to the ultrathin silicon dioxide layer is arranged between the upper surface of the irradiation-resistant reinforcing layer and the upper surface of the insulating medium region, the projection of the conductive field plate on the upper surface of the semiconductor region has an overlapping part with the emission region, the projection of the conductive field plate on the upper surface of the semiconductor region has an overlapping part with the spacer region, and the conductive field plate and the emission region are in conductive connection. The current gain of the bipolar transistor device is increased by 20-30% under the same radiation environment.

Description

Radiation-resistant bipolar device
Technical Field
The invention relates to an electronic device technology, belongs to the technical field of space environment effect, nuclear science and application, and particularly relates to a radiation hardening resistant bipolar transistor device.
Background
The spatially charged radiation particles mainly include heavy ions, electrons, protons, X-rays, and the like. These charged particles interact with the transistor device to produce ionizing radiation effects, single particle effects, displacement radiation effects, and the like. For using SiO2Transistor devices, which are insulating materials and passivation layers, generate a large number of electron-hole pairs in the oxide layer under the influence of different types of radiation particles, since the mobility of electrons is much higher than that of holes in the oxide. Under the action of an electric field, electrons drift to an electrode terminal at a high speed, and positive charges with low mobility are captured by the oxide traps to form positive oxide charges. In addition, the holes react with hydrogen-containing defects during the migration of the silicon dioxide layer, releasing hydrogen ions. Hydrogen ions will be transported to Si/SiO gradually2The interface reacts with Si-H bonds, and H + + Si-H → Si dangling bonds + H2 ×) cause interface state defects. The oxide trapped positive charge and the interface state change the recombination rate of carriers, and for the bipolar transistor, the oxide trapped positive charge and the interface state increase the recombination rate of a space charge area of a base region of the bipolar transistor, so that the base current is increased, and the current gain of the bipolar transistor is reduced.
Disclosure of Invention
The invention aims to provide a bipolar device with higher radiation resistance.
The invention solves the technical problem by adopting the technical scheme that the anti-radiation bipolar device comprises a semiconductor region, an insulating medium region and an electrode, wherein the insulating medium region and the electrode are arranged above the semiconductor region, the semiconductor region comprises a base region, an emitter region and a P + ohmic contact region which are arranged in a substrate, and the region between the emitter region and the P + ohmic contact region is a spacer region;
an anti-irradiation reinforcing layer with the thickness of 20-80 nm is further arranged between the insulating medium region and the upper surface of the semiconductor region, and the material of the anti-irradiation reinforcing layer comprises silicon dioxide;
a conductive field plate parallel to the ultrathin silicon dioxide layer is arranged between the upper surface of the irradiation-resistant reinforcing layer and the upper surface of the insulating medium region, the projection of the conductive field plate on the upper surface of the semiconductor region has an overlapping part with the emission region, the projection of the conductive field plate on the upper surface of the semiconductor region has an overlapping part with the spacer region, and the conductive field plate and the emission region are in conductive connection.
Further, the projection of the conductive field plate on the upper surface of the semiconductor region covers the boundary between the emitter region and the spacer region and the boundary between the P + ohmic contact region and the spacer region.
Furthermore, the anti-irradiation reinforcing layer comprises a first silicon dioxide layer, a positive charge inhibiting layer and a second silicon dioxide layer which are overlapped from bottom to top, the thickness of the first silicon dioxide layer is 2-20 nm, and the thickness of the positive charge inhibiting layer is 2-20 nm
Figure RE-GDA0002495883600000021
The thickness of the second silicon dioxide layer is 15-50 nm.
Further, the projection of the P + ohmic contact region on the upper surface of the semiconductor region is a semi-closed ring surrounding the projection area of the emitter region on the upper surface of the semiconductor region.
The current gain of the bipolar transistor device is increased by 20-30% under the same radiation environment.
Drawings
FIGS. 1(a) -1(k) show cross-sectional views of a mid-stage of a process for fabricating an ionizing radiation resistant bipolar device in accordance with the present invention.
Fig. 1(l) -1(n) show cross-sectional views of an improved, mid-stage, in-line, version of an ionizing radiation resistant bipolar device made in accordance with the present invention.
FIG. 1(o) is a schematic view of a radiation-hardening structure with a directly deposited silicon dioxide interlayer dielectric layer.
Fig. 2(a) shows a schematic diagram illustrating the radiation resistance of a radiation-resistant oxide layer according to the present invention for suppressing the effect of ionizing radiation of transistors, in particular the total dose of radiation.
Fig. 2(b) -2(d) show a process flow for fabricating a silicon dioxide thin film for suppressing the total dose radiation effect of a transistor according to the present invention.
Fig. 3 is another method of making a composite radiation-resistant silica layer.
Fig. 4 is a cross-sectional view and a layout of a radiation-resistant bipolar device with a P + ring structure added.
Fig. 5 is a simulated structural view of a radiation-hardened bipolar transistor device with the addition of a dense boron ring.
Detailed Description
Hereinafter, the present invention will be described with reference to the accompanying drawings. However, these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as to avoid confusion with the concepts of the present invention.
Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required. The numerical ranges indicated by the "to" symbols in the present invention are inclusive of the endpoints.
The following description explains the manufacturing method of the present invention, and the device structure of the present invention can be clearly understood through the manufacturing steps.
First, a thick sacrificial silicon dioxide layer is formed on a substrate by thermal oxidationThe layer (also can be called as an injection diffusion barrier layer) is used for photoetching the collector region, forming a collector region of a first conductive type on the substrate, then forming a base region of a second conductive type on the collector region, and then forming an emitter region of the first conductive type with higher concentration on the base region; then etching off the silicon dioxide sacrificial layer; growing a layer of thin silicon dioxide, which can be composite reinforced silicon dioxide or non-composite reinforced silicon dioxide; preparing a conductive field plate which can be polysilicon or metal on the thin silicon dioxide layer and is positioned above the emitter region-base region junction, wherein the conductive field plate is connected with the emitter electrode in potential; sputtering a thick silicon dioxide dielectric layer, respectively etching an emitter hole, a base electrode hole and a collector electrode hole, depositing metal, and etching to finish the patterning of the metal electrode to prepare a passivation layer. The "composite reinforcement" means that a composite layer structure is formed by a silicon dioxide layer and a positive charge inhibiting layer, for example, a positive charge inhibiting layer is grown on the upper surface of a first silicon dioxide layer having a thickness of 2 to 20nm, and then a second silicon dioxide layer having a thickness of 15 to 50nm is grown on the positive charge inhibiting layer, the positive charge inhibiting layer is made of Al2O3A thickness of
Figure RE-GDA0002495883600000031
The total dose of radiation produces a large number of electron-hole pairs in the silicon dioxide dielectric layer, since the mobility of electrons is much higher than that of holes in the oxide. Under the action of an electric field, electrons drift to an electrode terminal at a high speed, and positive charges with low mobility are captured by the oxide traps to form positive oxide charges. The invention reduces the positive oxide charge formed by radiation by preparing a thinner silicon dioxide layer or a radiation-resistant silicon dioxide layer; meanwhile, research shows that positive oxide charges in the silicon dioxide dielectric layer mainly cause increase of the recombination rate of the surface current of the base region and increase of the base current, so that the field plate and the emitter have the same potential by adding the conductive field plate on the base region junction of the emitter region, and the potential and the base region potential always have a potential difference of about 0.7V, so that the influence of positive charges captured by radiation on the surface current of the base region is reduced, and the radiation resistance of the device is improved.
The radiation-resistant silicon dioxide layer can be prepared by the following two methods: first, in very thin SiO2The single-layer Al-O bond on the surface can introduce acceptor states (Al-induced acceptor states) to capture electrons, so that negative fixed charges are generated at the interface, the Al-O bond tends to be used as an acceptor to accept the electrons, an electric field is generated after the Al-O bond on the surface of the silicon dioxide is linked with the electrons, the positive charges on the surface of the silicon dioxide are reduced under the action of the electric field, the surface state Dit of the silicon dioxide is reduced, and the effect of resisting ionizing radiation is achieved. The specific flow is shown in the implementation example.
The second method may employ SiO in a composite structure2Layer, i.e. first growing a thin layer of SiO on the surface of the silicon by thermal oxidation2And sputtering a layer of thin silicon dioxide or silicon nitride by adopting the processes of CVD, LPCVD, PECVD and the like, wherein the dielectric layer sputtered by the processes of CVD, LPCVD, PECVD and the like contains certain defects, and the defects are favorable for capturing positive charges caused by radiation and improving the radiation resistance. Usually, a plurality of broken silicon bonds exist at the interface of the Si substrate, and SiO is grown by thermal oxidation2Layer, which will repair these broken bonds, if sputtering is used directly, Si/SiO2The interface state of (2) is poor, and the device performance is influenced.
In addition, when the field plate is prepared, three different structures can be adopted, wherein the first structure is firstly etched to form an emitter hole, and after metal sputtering, a metal electrode is directly etched and stretches to a partial base region across the base region junction of the emitter region; in the second structure, metal is firstly deposited on a thin silicon dioxide layer, an independent field plate is etched, then an interlayer dielectric silicon dioxide layer is deposited, an emitter hole and a field plate hole are etched, and etched metal is deposited to realize the connection of the field plate and the emitter; the third method combines the improved structure 1 and the improved structure 2, which can reduce the process steps and increase the resistance of the emitting area; the conductive field plate is bridged on the surfaces of the emitter region and the base region, and the bridged range can be the surfaces of the emitter region and the low-concentration base region, or the surfaces of the emitter region, the low-concentration base region and the high-concentration base region; the field plate material is polycrystalline silicon or pure Al or doped Al or Ti/TiN or other metal conductive materials; the conductive field plate is connected to the emitter, or the conductive field plate is grounded or at a negative potential.
When a P + ohmic contact region is formed on the base region of the NPN tube, an annular layout can be adopted to form a concentrated boron ring on the surface of the base region, and the improvement of the radiation resistance of the NPN tube is facilitated. Similarly, when the base region of the PNP tube forms an n + ohmic contact region, an annular layout can be adopted to form a dense boron ring on the surface of the base region.
The following detailed description is made with reference to the accompanying drawings.
Fig. 1(a) -1(l) are cross-sectional views showing mid-stage stages in the flow of fabricating an ionizing radiation resistant bipolar NPN transistor of the present invention. As shown in fig. 1(a), a thick sacrificial layer 102 is thermally oxidized on an N-type substrate 101. A base implantation window is photoetched as shown in fig. 1(b), and base regions 103 are formed by ion implantation (or diffusion), as shown in fig. 1 (c); as shown in fig. 1(d), an emitter implantation window is patterned, and ion implantation (or diffusion) is performed to form an emitter region 104, as shown in fig. 1 (e); forming a base region P + ohmic contact region 106 by photolithography and ion implantation as shown in fig. 1 (f); the thick sacrificial oxide layer is removed, and a thin anti-radiation silicon dioxide layer 105 with a thickness of 20-80 nm is grown, as shown in FIG. 1(g), and the specific method is described in detail in FIG. 2.
As shown in fig. 1(h), a conductive field plate 107 is formed across the low resistance region and the emitter region of the base region, and the field plate 107 may be formed by polysilicon formed by a gate process of CMOS, or a metal deposited Al, TiN, Pt or other metal layer; the field plate 107 can also bridge the emitter junction and part of the base region surface as shown in fig. 1 (i); depositing a silicon dioxide dielectric layer 108 by PECVD or LPCVD, as shown in FIG. 1 (j); FIG. 1(k) illustrates the etching of the emitter, base, collector contact holes and the patterning of the electrodes of the metal electrodes; and finally, depositing a passivation layer and patterning the extraction point. The final structure of the device is shown in fig. 1(k), the radiation-resistant layer 105 can reduce the accumulation of holes, and the field plate 107 can accelerate the drifting and recombination of the holes, so that the purpose of improving the radiation resistance of the device is achieved. The field plate thickness is preferably 10nm to 1000 nm.
Fig. 1(l) -1(n) show cross-sectional views of an improved, mid-stage, in-line, version of an ionizing radiation resistant bipolar device made in accordance with the present invention.
Fig. 1(1) shows that, before preparing the field plate 107, the emitter hole 112 is etched, the metal field plate is sputtered and the connection between the field plate 107 and the emitter is completed, the interlayer dielectric silicon dioxide 108 is deposited, and patterning of the emitter, the base, the collector contact hole and the electrode metal is performed, and a hole etching process is added to the structure.
Fig. 1(m) shows that after an interlayer dielectric with a PECVD or LPCVD electrode thickness is adopted on the surface of a device prepared with anti-radiation silicon dioxide, the etching of an emitter hole is respectively etched by photoetching two patterns 121 and 122 with different sizes, and a metal electrode is deposited as shown in fig. 1(n), so that the preparation and connection of a field plate and an emitter electrode are completed at one time.
Fig. 1(o) shows that the radiation-resistant reinforcing structure including the field plate and the emitter electrode integrated is completed by the same process as that shown in fig. 1(m) after the silicon dioxide interlayer dielectric layer 108 is directly deposited without preparing the radiation-resistant silicon dioxide layer.
Fig. 2(a) shows the total dose radiation principle of the bipolar device, and as shown in the figure, the total dose radiation can generate a large number of electron-hole pairs in the silicon dioxide dielectric layer, because the mobility of electrons is much higher than that of holes in the oxide. Under the action of an electric field, electrons drift to an electrode terminal at a high speed, and positive charges with low mobility are captured by the oxide traps to form positive oxide charges. The positive oxide charge quantity is related to the thickness and the structure of the silicon dioxide, the thickness of the silicon dioxide layer is reduced, or the positive oxide charge caused by total dose radiation can be effectively reduced by adopting a silicon dioxide preparation method with radiation resistance reinforcement.
FIGS. 2(b) -2(d) are cross-sectional views of a middle-stage of the flow for fabricating an anti-radiation oxide layer for suppressing the effects of ionizing radiation, particularly the total dose of radiation, in accordance with the present invention;
as shown in the figure2(b), firstly cleaning the silicon wafer 101 by RCA, quickly rinsing in HF cleaning solution, washing by deionized water, spin-drying, and growing the ultrathin oxide layer 202 by a quick thermal oxidation method, wherein the material is SiO2(thickness 2-20 nm); next, as shown in FIG. 2(c), a positive charge inhibiting layer 203 of Al is grown on the ultra-thin oxide layer2O3Specifically, Al can be grown (1-10 cycles) by ALD2O3(thickness)
Figure RE-GDA0002495883600000061
) Or sputtering Al layer (thickness)
Figure RE-GDA0002495883600000062
) Naturally oxidizing;
next, as shown in FIG. 2(d), an oxide layer 204 of SiO is grown on the positive charge-suppressing layer 2032Specifically, a PECVD method is adopted to grow SiO2(thickness 15 to 50 nm). Then rapidly annealing at 900 ℃ for 30s in pure Ar atmosphere to enable Al to form an acceptor state. In pure H2And annealing at 400 ℃ for 1 hour in the atmosphere to form an H passivation layer. The resulting structure is an anti-radiation oxide layer structure 105.
FIG. 3 shows a composite structure of a radiation-resistant reinforcing silica layer, in which a thin SiO layer is first grown on the surface of the silicon by thermal oxidation2The layer 302 (with a thickness of 20-50 nm) is sputtered with a thin layer of silicon dioxide 303 (with a thickness of 50-500 nm) by processes such as CVD, LPCVD, PECVD and the like, because the silicon dioxide sputtered by the processes such as CVD, LPCVD, PECVD and the like contains certain defects, and the defects are favorable for capturing positive charges caused by radiation and improving radiation resistance. Usually, a plurality of broken silicon bonds exist at the interface of the Si substrate, and SiO is grown by thermal oxidation2Layer, which will repair these broken bonds, if sputtering is used directly, Si/SiO2The interface state of (2) is poor, and the device performance is influenced.
Fig. 4 shows a base region structure using a boron-rich ring, which shows a cross-sectional view and a layout, and can be combined with the device structures shown in fig. 1(l) -1 (o), so as to improve the total dose resistance of the device by improving the surface concentration of the base region of the bipolar transistor, reducing the influence of the positive oxide charges captured by the surface silicon dioxide layer on the surface recombination rate of the base region, and adding the boron-rich ring to the device simulation structure shown in fig. 5.

Claims (4)

1. The anti-radiation bipolar device comprises a semiconductor region, an insulating medium region and an electrode, wherein the insulating medium region and the electrode are arranged above the semiconductor region, the semiconductor region comprises a base region (103), an emitter region (104) and a P + ohmic contact region (106) which are arranged in a substrate (101), and the region between the emitter region (104) and the P + ohmic contact region (106) is a spacer region;
the method is characterized in that an anti-irradiation reinforcing layer with the thickness of 20-80 nm is arranged between the insulating medium region and the upper surface of the semiconductor region, and the material of the anti-irradiation reinforcing layer comprises silicon dioxide;
a conductive field plate (107) parallel to the ultrathin silicon dioxide layer (105) is arranged between the upper surface of the irradiation-resistant reinforcing layer and the upper surface of the insulating medium region, the projection of the conductive field plate 107 on the upper surface of the semiconductor region has an overlapping part with the emitter region (104), the projection of the conductive field plate (107) on the upper surface of the semiconductor region has an overlapping part with the spacer region, and the conductive field plate (107) is in conductive connection with the emitter region (104).
2. The radiation-resistant bipolar device of claim 1, wherein the projection of the conductive field plate (107) onto the upper surface of the semiconductor region covers the boundaries of the emitter region and the spacer region and the boundaries of the P + ohmic contact region (106) and the spacer region.
3. The radiation-resistant bipolar device according to claim 1 or 2, wherein the radiation-resistant reinforcing layer comprises a first silicon dioxide layer, a positive charge inhibition layer and a second silicon dioxide layer which are overlapped from bottom to top, the thickness of the first silicon dioxide layer is 2-20 nm, and the thickness of the positive charge inhibition layer is 2-20 nm
Figure FDA0002432589700000011
The thickness of the second silicon dioxide layer is 15-50 nm.
4. The radiation-resistant bipolar device of claim 3 wherein the projection of the P + ohmic contact region (106) on the upper surface of the semiconductor region is a semi-closed ring surrounding the projection of the emitter region (104) on the upper surface of the semiconductor region.
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CN110610983A (en) * 2019-09-06 2019-12-24 电子科技大学 Anti-radiation device and preparation method
CN112599529A (en) * 2020-12-10 2021-04-02 电子科技大学 Multilayer reinforced capacitor structure with hafnium-based ferroelectric and heavy ion irradiation resistance

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060157736A1 (en) * 2004-06-25 2006-07-20 Vonno Nicolaas W V Radiation hardened bipolar junction transistor
CN106653601A (en) * 2016-11-14 2017-05-10 北京时代民芯科技有限公司 Manufacture method for twin pole device resisting low dosage rate irradiation
CN108039320A (en) * 2017-11-13 2018-05-15 北京时代民芯科技有限公司 A kind of nanosecond Flouride-resistani acid phesphatase npn type bipolar transistor manufacture method
CN108417615A (en) * 2018-02-13 2018-08-17 重庆中科渝芯电子有限公司 A kind of high voltage substrate pnp bipolar junction transistor and its manufacturing method
CN110610983A (en) * 2019-09-06 2019-12-24 电子科技大学 Anti-radiation device and preparation method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621114B1 (en) * 2002-05-20 2003-09-16 Advanced Micro Devices, Inc. MOS transistors with high-k dielectric gate insulator for reducing remote scattering
CN101950757A (en) * 2010-07-13 2011-01-19 中国科学院上海微系统与信息技术研究所 High dielectric constant material grid structure based on SOI substrate and preparation method thereof
JP5638413B2 (en) * 2011-02-08 2014-12-10 東京エレクトロン株式会社 Method for forming mask pattern
CN104646985A (en) * 2013-11-25 2015-05-27 辽宁益盛达机电设备制造有限公司 Mechanism with discharge cylinder with rotary motor of backlight machine
EP3373329B1 (en) * 2014-02-28 2023-04-05 LFoundry S.r.l. Integrated circuit comprising a laterally diffused mos field effect transistor
CN104576398B (en) * 2014-12-12 2018-04-10 北京时代民芯科技有限公司 A kind of VDMOS device manufacture method with anti-radiation performance
CN205752146U (en) * 2016-07-04 2016-11-30 北京思众电子科技有限公司 The passivation film structure of semiconductor chip and circuit board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060157736A1 (en) * 2004-06-25 2006-07-20 Vonno Nicolaas W V Radiation hardened bipolar junction transistor
CN106653601A (en) * 2016-11-14 2017-05-10 北京时代民芯科技有限公司 Manufacture method for twin pole device resisting low dosage rate irradiation
CN108039320A (en) * 2017-11-13 2018-05-15 北京时代民芯科技有限公司 A kind of nanosecond Flouride-resistani acid phesphatase npn type bipolar transistor manufacture method
CN108417615A (en) * 2018-02-13 2018-08-17 重庆中科渝芯电子有限公司 A kind of high voltage substrate pnp bipolar junction transistor and its manufacturing method
CN110610983A (en) * 2019-09-06 2019-12-24 电子科技大学 Anti-radiation device and preparation method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
翟亚红等: "抗辐射双极n-p-n晶体管的研究", 《物理学报》 *

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