CN103178104A - Semiconductor device multistage field plate terminal structure and manufacturing method thereof - Google Patents
Semiconductor device multistage field plate terminal structure and manufacturing method thereof Download PDFInfo
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- CN103178104A CN103178104A CN2013100540202A CN201310054020A CN103178104A CN 103178104 A CN103178104 A CN 103178104A CN 2013100540202 A CN2013100540202 A CN 2013100540202A CN 201310054020 A CN201310054020 A CN 201310054020A CN 103178104 A CN103178104 A CN 103178104A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 60
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 60
- 230000007797 corrosion Effects 0.000 claims abstract description 46
- 238000005260 corrosion Methods 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 230000000903 blocking effect Effects 0.000 claims abstract description 6
- 238000011084 recovery Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims description 61
- 238000005229 chemical vapour deposition Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 23
- 239000007924 injection Substances 0.000 claims description 23
- 230000012010 growth Effects 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 8
- 239000000243 solution Substances 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 235000013842 nitrous oxide Nutrition 0.000 claims description 5
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 230000007773 growth pattern Effects 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 abstract 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 239000010409 thin film Substances 0.000 abstract 4
- 229910020286 SiOxNy Inorganic materials 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000005516 engineering process Methods 0.000 description 14
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- 230000005684 electric field Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910008062 Si-SiO2 Inorganic materials 0.000 description 1
- 229910006403 Si—SiO2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- -1 corrosion Substances 0.000 description 1
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Abstract
The invention relates to a semiconductor device multistage field plate terminal structure and a manufacturing method thereof. The multistage field plate terminal structure is in a step structure, is used in IGBT (insulated gate bipolar transistor) chips and fast recovery diodes (FRDs) and comprises a grid oxidation film and a filed oxidation film layer on the surface of a substrate area, polysilicon grids deposited on the grid oxidation film and the field oxidation film layer, an isolating oxidation film deposited on the field oxidation film layer, and an SiO2 thin film deposited on the isolating oxidation film, and an SiOxNy layer is arranged between the isolating oxidation film and the SiO2 thin film and is a corrosion barrier layer. The structural terminal is structured in five steps, is small in area and insensitive to interface charge, and breaks blocking of a patent of four-step filed plate structure abroad; the SiOxNy thin film layers are added in the middle of the multistage field plate oxidation film layer and below the SiO2 thin film to serve as the corrosion barrier layers, so that requirements on process accuracy are lowered and operations are simple; SiOxNy has good compactness and capability of blocking external foreign ions from invading, so that stability and reliability of a device are improved.
Description
Technical field
The invention belongs to field of semiconductor devices, be specifically related to a kind of terminal structure, relate in particular to the multistage field plate terminal structure of a kind of semiconductor device and manufacture method thereof.
Background technology
The IGBT(igbt) have advantages of simultaneously unipolarity device and bipolar devices, drive circuit is simple, control circuit power consumption and cost are low, on-state voltage drop is low, the device own loss is little, be in monopoly position in high-current device in tens kilo hertzs of high pressure, promote the arrival in power electronic technology high frequency epoch.
In the IGBT process for making, diffusion is to carry out after the photo etched mask windowing, the p-n junction intermediate approximation is in planar junction, and at edge, at the near interface of Si-SiO2, because the positively charged electronics that can attract in oxide layer causes N-type district, Si surface surface concentration to raise in the Si set of surfaces, and then causing depletion layer to narrow down than inside in the surface, p-n junction bends, and is high in the electric field ratio body, easily puncture, make the device actual breakdown voltage only have the 10%-30% of ideal situation; And planar technique makes defective and the ion that the surface produces stain the critical breakdown electric field that has reduced surf zone.Therefore must take certain terminal technology effects on surface electric field to be optimized, to reach the purpose that improves surface breakdown voltage.
The terminal structure of having developed has shaping surface technology, electric field limit collar (FLR), field plate techniques, knot surface expansion etc., and in fact these structures play the effect with the outside broadening of main knot depletion region, finally improve puncture voltage.Wherein field plate structure is because it can adopt common process to realize, the terminal area is little, not the advantage such as very sensitive to interface charge, it is a kind of normal adopted structure, wherein the multistage field plate terminal structure of company of Infineon level Four step is very ripe, the marketization and was not met the multistage field plate terminal structure of Pyatyi step for many years on market.
Summary of the invention
For the deficiencies in the prior art, the purpose of this invention is to provide the multistage field plate terminal structure of a kind of semiconductor device, another purpose is to provide the manufacture method of the multistage field plate terminal structure of semiconductor device, this structure terminal is five steps, the terminal area is little, insensitive to interface charge, blockade that can the breaks through foreign four multistage field plate structure patents of step; Middle and isolated oxide film and SiO at field oxide film
2SiO is set between film
xN
yLayer,, can be used as corrosion barrier layer on technology controlling and process, reduce the requirement to craft precision, simple to operate, secondly due to SiO
xN
yHave good compactness, the ability of stronger prevention foreign matter ion intrusion is arranged, can improve stability and the reliability of device.
The objective of the invention is to adopt following technical proposals to realize:
The multistage field plate terminal structure of a kind of semiconductor device, described multistage field plate terminal structure is hierarchic structure, be used for IGBT and fast recovery diode FRD semiconductor power device, its improvements are, described multistage field plate terminal structure comprise the substrate zone surface grid oxidation film 1 and field oxide film layer 2, be deposited on polysilicon gate 3 on grid oxidation film 1 and field oxide film layer 2, be deposited on the isolated oxide film 4 on field oxide film layer 2 and be deposited on SiO on isolated oxide film 4
2 Film 5; Oxidation film layer 2 centre and isolated oxide film 4 and SiO on the scene
2Between film 5, SiO is set
xN
y(wherein x, y determine according to actual tests) layer, described SiO
xN
yLayer is corrosion barrier layer.
Preferably, described grid oxidation film 1 and field oxide film layer 2 all are grown on substrate 6, and described substrate 6 is the N-substrate.
Preferably, described field oxide film layer 2 forms two steps by Twi-lithography, corrosion, the field oxide film layer 2 that photoetching for the first time and corrosion adopt the thermal oxidation mode to generate, and its thickness is 0.5-0.8um; The field oxide film layer 2 that photoetching for the second time and corrosion adopt the deposit mode to form, its thickness is 0.7-1.0um; Between the field oxide film layer that two kinds of different growth patterns generate, SiO is set
xN
yLayer.
Preferably, described grid oxidation film 1 is grown by the thermal oxidation mode, and its thickness is 0.09-0.12um.
Preferably, described SiO
2Film 5 adopts the chemical vapor deposition mode to generate, and thickness is 4.0-5um.
Preferably, described SiO
xN
yAll for stoping the foreign matter ion to invade multistage field plate terminal structure, thickness is 0.12um to layer.
The present invention is based on the manufacture method of the multistage field plate terminal structure of a kind of semiconductor device that another purpose provides, it is characterized in that, described manufacture method comprises the steps:
A, clean substrate 6, at active area and terminal junction, P type guard ring (being called for short P Ring ring) is set, and P type guard ring is carried out photoetching, injection;
B, adopt the thermal oxidation mode to generate field oxide film layer 2 on substrate 6, and field oxide film layer 2 is carried out photoetching for the first time, corrosion;
C, generate successively SiO after photoetching for the first time, corrosion field oxide film layer 2
xN
yLayer, field oxide 2;
D, field oxide film layer 2 is carried out photoetching for the second time, corrosion;
E, generate grid oxidation film 1 and it is carried out etching on substrate 6;
F, generate polysilicon gate 3 on grid oxidation film 1 and field oxide film layer 2, and polysilicon gate 3 is carried out etching;
G, P trap and N trap inject on substrate 6;
H, generate isolated oxide film 4 and thereon using plasma strengthen chemical vapour deposition (CVD) (PECVD) method, at pressure 4.5-5.5Pa, under 100 ° of C-300 ° of C conditions of temperature in proportion 5:7:12 pass into silane, laughing gas, ammonia (SiH
4: N2O:NH3=5:7:12) generate SiO
xN
yLayer;
I, at SiO
xN
yGenerate SiO on layer
2Film 5 also carries out etching to it.
Preferably, in described steps A, the oxide layer of growth 0.2um after substrate cleans; as implant blocking layer, and at active area and terminal junction, P type guard ring is set, to B Implanted ion after the photoetching of P type guard ring; injection rate is 1e13-1e14, then to the cleaning of removing photoresist of the P type guard ring after photoetching.
Preferably, in described step B, the thickness that adopts the thermal oxidation mode to generate field oxide film layer 2 is 0.5-0.8um and carries out photoetching for the first time, corrosion.
Preferably, in described step C, strengthen chemical vapour deposition technique and generate successively SiO at photoetching for the first time, corrosion field oxide film layer 2 rear using plasma
xN
yLayer, field oxide film layer 2, described SiO
xN
yThe thickness of layer is 0.12um, and field oxide film layer 2 thickness are 0.7-1.0um.
Preferably, in described step D, the field oxide film layer 2 that adopts the chemical vapor deposition mode to generate to step C carries out photoetching for the second time, and adopts buffered hydrogen fluoride (BHF) solution to carry out wet etching.
Preferably, in described step e, described grid oxidation film 1 is grown by the thermal oxidation mode, and growth temperature is not higher than 1050 ° of C, and its thickness is 0.09-0.12um.
Preferably, in described step F, polysilicon gate 3 is carried out photoetching and carries out plasma etching.
Preferably, in described step G, P trap and the photoetching on substrate 6 of N trap, injection, P trap B Implanted ion, injection rate is 1e13-1e14; NSD injects arsenic ion, and injection rate is 3e15-5e15.
Preferably, in described step H, the thickness of the isolated oxide film 4 of generation is 1.0-1.2um, and using plasma strengthens chemical vapour deposition technique generation SiO on isolated oxide film 4
xN
yLayer, described SiO
xN
yThe thickness of layer is 0.12um.
Preferably, in described step I, the SiO that adopts CVD (Chemical Vapor Deposition) method to generate
2The thickness of film 5 is 4.0-5um, adopts and adopt buffered hydrogen fluoride (BHF) solution to carry out wet etching after photoetching.
Compared with the prior art, the beneficial effect that reaches of the present invention is:
1, the multistage field plate terminal structure of semiconductor device provided by the invention and manufacture method thereof, based on existing technique, practical;
2, the multistage field plate terminal structure of semiconductor device provided by the invention and manufacture method thereof, can break through the blockade of the four multistage field plates of step on market;
3, the terminal area of the multistage field plate terminal structure of semiconductor device provided by the invention is little, and is insensitive to interface charge;
4, the multistage field plate terminal structure of semiconductor device provided by the invention, the middle and SiO at field oxide
2Add skim SiO under film
xN
yThe layer, on technology controlling and process as corrosion barrier layer, due to SiO
xN
yHave good compactness, the ability that has stronger prevention foreign matter ion to invade can reduce the requirement to craft precision, and is simple to operate, improves stability and the reliability of device;
5, the multistage field plate terminal structure of semiconductor device provided by the invention is applicable to igbt chip and fast recovery diode FRD terminal structure.
Description of drawings
Fig. 1 is the shape appearance figure after embodiment 1 field oxide film layer photoetching for the first time provided by the invention, corrosion;
Fig. 2 is that embodiment 1 provided by the invention generates a SiO
xN
yShape appearance figure after the photoetching for the second time of layer back court oxidation film layer, corrosion;
Fig. 3 is the shape appearance figure after embodiment 1 polysilicon gate growth provided by the invention, etching and P trap, N trap inject;
Fig. 4 is that embodiment 1 provided by the invention generates isolated oxide film and the 2nd SiO
xN
yShape appearance figure after layer;
Fig. 5 is that embodiment 1 provided by the invention generates SiO
2Shape appearance figure after film;
Fig. 6 is the shape appearance figure of the multistage field plate terminal structure of embodiment 1 provided by the invention.
Fig. 7 is the shape appearance figure after embodiment 2 field oxide film layer photoetching for the first time provided by the invention, corrosion;
Fig. 8 is the shape appearance figure after embodiment 2 field oxide film layer photoetching for the second time provided by the invention, corrosion;
Fig. 9 is embodiment 2 gate oxidation films growths provided by the invention, etching, the shape appearance figure after the injection of polysilicon gate growth, etching and P trap, N trap;
Figure 10 is that embodiment 2 provided by the invention generates isolated oxide film and SiO
xN
yShape appearance figure after layer;
Figure 11 is that embodiment 2 provided by the invention generates SiO
2Shape appearance figure after film;
Figure 12 is the shape appearance figure of the multistage field plate terminal structure of embodiment 2 provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
The invention provides the multistage field plate terminal structure of a kind of semiconductor device, multistage field plate terminal structure is hierarchic structure, be used for the semiconductor device such as IGBT and fast recovery diode FRD, its shape appearance figure as shown in Figure 6, comprise the substrate zone surface grid oxidation film 1 and field oxide film layer 2, be deposited on polysilicon gate 3 on grid oxidation film 1 and field oxide film layer 2, be deposited on the isolated oxide film 4 on field oxide film layer 2 and be deposited on SiO on isolated oxide film 4
2 Film 5; Middle and isolated oxide film 4 and SiO at field oxide
2Between film 5, SiO is set
xN
yLayer, SiO
xN
yLayer is corrosion barrier layer.
IGBT(igbt in semiconductor device) have advantages of simultaneously unipolarity device and bipolar devices, drive circuit is simple, and control circuit power consumption and cost are low, and on-state voltage drop is low, the device own loss is little, is the developing direction of following high-voltage great-current.
Igbt chip is divided into by function: active area, termination environment and gate regions three parts.Active area claims again cellular region, is the functional area of chip; The electric current relevant parameter of major effect chip, as conducting voltage, the threshold voltage parameter; The termination environment is positioned at the fringe region of chip, the withstand voltage parameter of major effect chip; Gate regions is the grid control area of chip, affects the switching characteristic of device.
The igbt chip manufacturing technology mainly comprises: photoetching, diffusion/injection, corrosion, film four module.The igbt chip manufacturing technology is namely transferred to technology on semiconductor wafer by corresponding manufacturing technology with the figure on mask.The IGBT manufacturing technology namely adopts corresponding technology to complete the igbt chip active area, the technology of termination environment and gate regions.
The present invention also provides a kind of manufacture method of the igbt chip five multistage field plate terminal structures of step, specifically comprises the steps:
A, clean substrate 6, at active area and terminal junction, P type guard ring (being called for short P Ring ring) is set, and P type guard ring is carried out photoetching, injection;
The oxide layer of growth 0.2um after substrate cleans as implant blocking layer, and arranges P type guard ring at active area and terminal junction, and to B Implanted ion after the photoetching of P type guard ring, injection rate is 1e13-1e14, then to the cleaning of removing photoresist of the P type guard ring after photoetching.
B, adopt the thermal oxidation mode to generate field oxide film layer 2 on substrate 6, and field oxide film layer 2 is carried out photoetching for the first time, corrosion;
The thickness that adopts the thermal oxidation mode to generate field oxide film layer 2 is 0.5-0.8um and carries out photoetching for the first time, corrosion, add after the photoetching for the first time of PRing ring back court oxidation film layer, corrosion shape appearance figure as shown in Figure 1.
C, generate successively SiO after photoetching for the first time, corrosion field oxide film layer 2
xN
yLayer, the field oxide film layer;
Using plasma strengthens chemical vapour deposition (CVD) generation SiO on the field oxide film layer 2 after photoetching for the first time, corrosion
xN
yLayer, field oxide film layer, described SiO
xN
yThe thickness of layer is 0.12um, and described field oxide film thickness layer by layer is 0.7-1.0um.
D, field oxide film layer 2 is carried out photoetching for the second time, corrosion;
The field oxide film layer 2 that adopts the chemical vapor deposition mode to generate to step C carries out photoetching for the second time, and adopts buffered hydrogen fluoride (BHF) solution to carry out wet etching.The field oxide film layer is generating a SiO on photoetching back court oxidation film layer for the first time
xN
yShape appearance figure after layer as shown in Figure 2.
E, generate grid oxidation film 1 and it is carried out etching on substrate 6;
F, generate polysilicon gate 3 on grid oxidation film 1 and field oxide film layer 2, and polysilicon gate 3 is carried out etching;
G, P trap and N trap inject on substrate 6;
P trap and the photoetching on substrate 6 of N trap, injection, P trap B Implanted ion, injection rate is 1e13-1e14; NSD injects arsenic ion, and injection rate is 3e15-5e15.Gate oxidation films growth, etching add a SiO
xN
yShape appearance figure after polysilicon gate growth after layer, etching and P trap, N trap inject as shown in Figure 3.
H, generation isolated oxide film 4 also generate SiO thereon
xN
yLayer;
The thickness of the isolated oxide film 4 that generates is 1.0-1.2um, and using plasma strengthens chemical vapour deposition (CVD) generation SiO on isolated oxide film 4
xN
yLayer, SiO
xN
yThe thickness of layer is 0.12um, adds a SiO
xN
yGenerate isolated oxide film and the 2nd SiO after layer
xN
yShape appearance figure after layer as shown in Figure 4.
I, at the 2nd SiO
xN
yGenerate SiO on layer
2Film 5 also carries out etching to it:
The SiO that adopts chemical vapor deposition to generate
2The thickness of film 5 is 4.0-5um, adopts buffered hydrogen fluoride (BHF) solution to carry out wet etching after photoetching, adds a SiO
xN
yGenerate SiO after layer
2Shape appearance figure after film as shown in Figure 5.
In order to ensure the integrality that semiconductor device is made, also carry out hole etching, metal etch and passivation etching and the back side of semiconductor device and make, form complete IGBT device.
A ', clean substrate 6, at active area and terminal junction, P type guard ring (being called for short P Ring ring) is set, and P type guard ring is carried out photoetching, injection;
The oxide layer of growth 0.2um after substrate cleans as implant blocking layer, and arranges P type guard ring at active area and terminal junction, and to B Implanted ion after the photoetching of P type guard ring, injection rate is 1e13-1e14, then to the cleaning of removing photoresist of the P type guard ring after photoetching.
B ', adopt the thermal oxidation mode to grow on substrate 6 to generate field oxide film layer 2 and field oxide film layer 2 is carried out photoetching for the first time, corrosion;
The thickness that adopts the thermal oxidation mode to generate field oxide film layer 2 is 1.0-1.5um and carries out photoetching for the first time, corrosion, and the shape appearance figure after the photoetching for the first time of field oxide film layer, corrosion as shown in Figure 7.
C ', field oxide film layer 2 is carried out photoetching for the second time, corrosion;
The field oxide film layer 2 that step B ' is generated carries out photoetching for the second time, and adopts buffered hydrogen fluoride (BHF) solution to carry out wet etching, and the thickness after corrosion is 0.5-0.8um, and the shape appearance figure after the photoetching for the second time of field oxide film layer, corrosion as shown in Figure 8.
D ', generate grid oxidation film 1 and it is carried out etching on substrate 6;
E ', generate polysilicon gate 3 on grid oxidation film 1 and field oxide film layer 2, and polysilicon gate 3 is carried out etching;
F ', P trap and N trap inject on substrate 6;
P trap and the photoetching on substrate 6 of N trap, injection, P trap B Implanted ion, injection rate is 1e13-1e14; The N trap injects arsenic ion, and injection rate is 3e15-5e15.Gate oxidation films growth, etching, the shape appearance figure after the injection of polysilicon gate growth, etching and P trap, N trap as shown in Figure 9.
G ', generate isolated oxide film 4 and thereon using plasma strengthen chemical vapour deposition (CVD) (PECVD) method and exist, at pressure 4.5-5.5Pa, under 100 ° of C-300 ° of C conditions of temperature in proportion 5:7:12 pass into silane, laughing gas, ammonia (SiH
4: N2O:NH3=5:7:12) generate SiO
xN
yLayer; Generate isolated oxide film and SiO
xN
yShape appearance figure after layer as shown in figure 10.
H ', at SiO
xN
yGenerate SiO on layer
2Film 5 also carries out etching to it.
The SiO that adopts chemical vapor deposition to generate
2The thickness of film 5 is 4.0-5um, adopts and adopt buffered hydrogen fluoride (BHF) solution to carry out wet etching after photoetching.Generate SiO
2Shape appearance figure after film as shown in figure 11.
In order to ensure the integrality that semiconductor device is made, carry out equally hole etching, metal etch, passivation etching and the back side of semiconductor device and make, form complete IGBT device.
The present invention is based on existing technique platform a multistage field plate terminal structure with five step igbt chips is provided, this structure terminal area is little, and is insensitive to interface charge, the blockade of the breaks through foreign four multistage field plate structure patents of step; Field oxide centre and the thick SiO of multistage field plate
2Add skim SiO under structure
xN
yLayer can be used as corrosion barrier layer on technology controlling and process, reduce the requirement to craft precision, and manufacture method is simple, secondly due to SiO
xN
yHave good compactness, the ability of stronger prevention foreign matter ion intrusion is arranged, can improve stability and the reliability of device.
Should be noted that at last: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although with reference to above-described embodiment, the present invention is had been described in detail, those of ordinary skill in the field are to be understood that: still can modify or be equal to replacement the specific embodiment of the present invention, and do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of claim scope of the present invention.
Claims (16)
1. multistage field plate terminal structure of semiconductor device, described multistage field plate terminal structure is hierarchic structure, be used for IGBT and fast recovery diode FRD semiconductor power device, it is characterized in that, described multistage field plate terminal structure comprise the substrate zone surface grid oxidation film (1) and field oxide film layer (2), be deposited on polysilicon gate (3) on grid oxidation film (1) and field oxide film layer (2), be deposited on the isolated oxide film (4) on field oxide film layer (2) and be deposited on SiO on isolated oxide film (4)
2Film (5); Middle and isolated oxide film (4) and SiO at field oxide film
2Film arranges SiO between (5)
xN
yLayer, described SiO
xN
yLayer is corrosion barrier layer.
2. the multistage field plate terminal structure of semiconductor device as claimed in claim 1, is characterized in that, described grid oxidation film (1) and field oxide film layer (2) all are grown on substrate (6), and described substrate (6) is the N-substrate.
3. the multistage field plate terminal structure of semiconductor device as claimed in claim 1, it is characterized in that, described field oxide film layer (2) forms two steps by Twi-lithography, corrosion, the field oxide film layer (2) that photoetching for the first time and corrosion adopt the thermal oxidation mode to generate, and its thickness is 0.5-0.8um; The field oxide film layer (2) that photoetching for the second time and corrosion adopt the deposit mode to form, its thickness is 0.7-1.0um; The field oxide film layer arranges SiO between the field oxide film layer that two kinds of different growth patterns generate
xN
yLayer.
4. the multistage field plate terminal structure of semiconductor device as claimed in claim 1, is characterized in that, described grid oxidation film (1) is grown by the thermal oxidation mode, and its thickness is 0.09-0.12um.
5. the multistage field plate terminal structure of semiconductor device as claimed in claim 1, is characterized in that described SiO
2Film (5) adopts the chemical vapor deposition mode to generate, and thickness is 4.0-5um.
6. the multistage field plate terminal structure of semiconductor device as described in any one in claim 1 and 3, is characterized in that described SiO
xN
yLayer is used for stoping the foreign matter ion to invade multistage field plate terminal structure all as corrosion barrier layer, and thickness is 0.12um.
7. the manufacture method of the multistage field plate terminal structure of semiconductor device, is characterized in that, described manufacture method comprises the steps:
A, clean substrate (6), at active area and terminal junction, P type guard ring is set, and P type guard ring is carried out photoetching, injection;
B, generate field oxide film layer (2) in the upper thermal oxidation mode that adopts of substrate (6), and field oxide film layer (2) is carried out photoetching for the first time, corrosion;
C, generate successively SiO after photoetching for the first time, corrosion field oxide film layer (2)
xN
yLayer, field oxide film layer (2);
D, field oxide film layer (2) is carried out photoetching for the second time, corrosion;
E, generate grid oxidation film (1) and it is carried out etching substrate (6) is upper;
F, generate polysilicon gate (3) grid oxidation film (1) and field oxide film layer (2) are upper, and polysilicon gate (3) is carried out etching;
G, P trap and N trap inject on substrate (6);
H, generate isolated oxide film (4) and thereon using plasma strengthen chemical vapour deposition technique, at pressure 4.5-5.5Pa, under 100 ° of C-300 ° of C conditions of temperature in proportion 5:7:12 pass into silane, laughing gas and ammonia and generate SiO
xN
yLayer;
I, at SiO
xN
yGenerate SiO on layer
2Film (5) also carries out etching to it.
8. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7; it is characterized in that; in described steps A; the oxide layer of growth 0.2um after substrate cleans; as implant blocking layer, and at active area and terminal junction, P type guard ring is set, to B Implanted ion after the photoetching of P type guard ring; injection rate is 1e13-1e14, then to the cleaning of removing photoresist of the P type guard ring after photoetching.
9. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7, is characterized in that, in described step B, the thickness that adopts the thermal oxidation mode to generate field oxide film layer (2) is 0.5-0.8um and carries out photoetching for the first time, corrosion.
10. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7, is characterized in that, in described step C, the upper using plasma of the field oxide film layer (2) after photoetching for the first time, corrosion strengthens chemical vapour deposition technique and generates SiO
xN
yLayer and field oxide film layer (2), described SiO
xN
yThe thickness of layer is 0.12um, and described field oxide film layer thickness is 0.7-1.0um.
11. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7, it is characterized in that, in described step D, the field oxide film layer (2) that adopts the chemical vapor deposition mode to generate to step C carries out photoetching for the second time, and adopts buffered hydrogen fluoride solution to carry out wet etching.
12. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7, it is characterized in that, in described step e, described grid oxidation film (1) is grown by the thermal oxidation mode, growth temperature is not higher than 1050 ° of C, and its thickness is 0.09-0.12um.
13. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7 is characterized in that, in described step F, polysilicon gate (3) is carried out photoetching and carries out plasma etching.
14. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7 is characterized in that, in described step G, and the photoetching on substrate (6) of P trap and N trap, injection, P trap B Implanted ion, injection rate is 1e13-1e14; The N trap injects arsenic ion, and injection rate is 3e15-5e15.
15. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7, it is characterized in that, in described step H, the thickness of the isolated oxide film of generation (4) is 1.0-1.2um, and strengthens chemical vapour deposition technique generation SiO at the upper using plasma of isolated oxide film (4)
xN
yLayer, described SiO
xN
yThe thickness of layer is 0.12um.
16. the manufacture method of the multistage field plate terminal structure of semiconductor device as claimed in claim 7 is characterized in that, in described step I, and the SiO that adopts chemical vapor deposition to generate
2The thickness of film (5) is 4.0-5um, after photoetching and adopt buffered hydrogen fluoride solution to carry out wet etching.
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