CN202633315U - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
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- CN202633315U CN202633315U CN 201220151783 CN201220151783U CN202633315U CN 202633315 U CN202633315 U CN 202633315U CN 201220151783 CN201220151783 CN 201220151783 CN 201220151783 U CN201220151783 U CN 201220151783U CN 202633315 U CN202633315 U CN 202633315U
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- 230000001413 cellular effect Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 230000007797 corrosion Effects 0.000 claims abstract description 13
- 238000005260 corrosion Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000011218 binary composite Substances 0.000 claims description 6
- 239000011219 quaternary composite Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The utility model provides an IGBT (insulated gate bipolar transistor), comprising a cellular region, a terminal region and a scribing groove. The cellular region comprises a polysilicon gate electrode, an emitter electrode, an N+ emitter region and a P+ emitter region in connection with the emitter electrode, an N well region, a P well region, an N- substrate, a transparent collector region and a collector electrode. A silicon oxynitride layer in a multistage field plate possesses a function of a corrosion barrier layer and has low processing precision requirements; and the silicon oxynitride layer has good compactness; the stability and reliability of the transistor can be raised. The emitter electrode employs a chamfer type and is lateral to a corrosion oxide layer after chamfer, which can reduce ohmic contact resistance and meanwhile increase a metal contact region to uniform heat dissipation and better device high temperature characteristics. The cellular employs a Spacer structure and is injected to P and N type regions by utilizing a set of lithography edition, which can avoid overlay error, ensure consistency of cellular channels and improve dynamic characteristics; meanwhile a lithography plate can be saved, processing steps can be minimized and costs can be saved.
Description
Technical field
The utility model belongs to the power device field, is specifically related to a kind of igbt.
Background technology
Insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) is formed in parallel by the unit born of the same parents; The advantage that has unipolarity device and bipolar devices simultaneously; Drive circuit is simple, and control circuit power consumption and cost are low, and on-state voltage drop is low; The device own loss is little, is the developing direction of following high-voltage great-current.
Like Fig. 1, insulated gate bipolar transistor IGBT comprises cellular region, termination environment and scribe line.Fig. 2 is the profile of insulated gate bipolar transistor IGBT in the prior art.Cellular region diffuses to form the P well region through the ion injection on the N-substrate, the N well region, and emitter links to each other with N emitter region, P+ emitter region; The shape of emitter and material influence ohmic contact resistance size and heat-sinking capability, and the unreasonable hot properties that can influence device is set, and solution commonly used is to seek suitable metal material; Perhaps improve the doping content of semiconductor region, as injecting the N+ emitter region that diffuses to form high concentration through ion usually now, the current lead-through ability of device can also be improved in the N+ emitter region; In order to suppress the generation of insulated gate bipolar transistor IGBT breech lock; The P+ emitter region of the high concentration of also can reinjecting, to reduce the pressure drop between P trap and the N+ emitter region, cellular region N-substrate injects through the back side and forms the very thin transparent collector district BackP+ of one deck; Play electricity and lead modulating action; Make the IGBT saturation voltage be positive temperature coefficient, be more suitable for parallel connection, what the transparent collector district linked to each other is collector electrode.
The termination environment is looped around around the cellular, improves the critical breakdown electric field of cellular region surf zone.In the process for making of cellular, diffusion is behind the photo etched mask windowing, to carry out, and the p-n junction intermediate approximation is in planar junction; And bend at the edge p-n junction; Be similar to cylinder or sphere, because there is curvature in the position of p-n junction corner, the electric field that makes the surface is than high in the body; When critical breakdown electric field one timing, be the position that puncture takes place the most easily; And defective and ion that planar technique produces the surface stain the critical breakdown electric field that has reduced surf zone.Like this, just must design certain terminal structure surface field is optimized, to reach the purpose that improves surface breakdown voltage.
Terminal structure commonly used has field plate (FP), field limiting ring (FLR), knot terminal to extend (JTE), horizontal varying doping (VLD), resistive field plate (like oxygen-doped polysilicon (SIPOS)) etc.In fact these extended structures play the effect with the outside broadening of main knot depletion region, finally improve puncture voltage thereby reduce its internal electric intensity.
Multistage field plate also has the little advantage of terminal area except having the ability that improves puncture voltage.Oxidated layer thickness in the multistage field plate structure plays a major role to withstand voltage, and wherein the thickest oxide layer is not easy control in the etching process process, can influence device withstand voltage if THICKNESS CONTROL is improper.
Scribe line can be put some resolution charts, so that some parameters in the chip production course of processing are collected, and test.
The utility model content
In order to overcome the deficiency of above-mentioned prior art; The utility model provides a kind of insulated gate bipolar transistor, and the silicon oxynitride layer in the multistage field plate has the effect of corrosion barrier layer, and is low to the etching process required precision; Silicon oxynitride layer compactness is good; The ability that has stronger prevention foreign matter ion to invade improves the stability and the reliability of igbt, and the multistage field plate that contains silicon oxynitride layer can be saved device area.
To achieve these goals, the utility model adopts following technical scheme:
A kind of igbt, said transistor comprise cellular region, termination environment and the scribe line that single cellular is formed in parallel; Said cellular region comprises polygate electrodes, metal emitting, the N+ emitter region that is connected with said emitter and P+ emitter region, N well region, P well region, N-substrate, transparent collector district and collector electrode; Said termination environment comprises multistage field plate, N-substrate, transparent collector district and collector electrode; Said transparent collector district is positioned at the centre of said N-substrate and collector electrode, and said multistage field plate is positioned at the top of N-substrate.
Said metal emitting is a grooving formula structure, and at the grooving rear side to the corrosion oxidation layer.The grooving formula be at the window place that isolating oxide layer ILD (Isolate Oxide) opens downward etching to form a degree of depth be 0.2～0.5um, the length of side of going to the bottom is 4.8um, go up bottom side length is the prismatoid groove of 5um; And at the grooving rear side to the corrosion oxidation layer, fill metal at groove again and form metal emitting, can increase the contact area of metal and N+ and P+ like this; Reduce contact resistance; Simultaneously also can increase area of dissipation, make the heat radiation of device more even, hot properties is better.
Said N+ emitter region and said P+ emitter region lay respectively in the N well region and P well region in the said N-substrate.
Said multistage field plate comprises metal emitting, polygate electrodes and oxide layer; Said oxide layer is a hierarchic structure.
Said oxide layer comprises that thickness is that gate oxide, the thickness of 0.1～0.2um is the field oxide of 1～2um; Thickness be 2～4um by field oxide and the supreme binary composite bed that constitutes of stack successively below the isolating oxide layer and thickness be 5～10um by field oxide, isolating oxide layer, silicon oxynitride oxide layer and the supreme quaternary composite bed that superposes and constitute successively below the silicon dioxide oxide layer.
The field oxide thickness of said binary composite bed is 1～2um, and the isolation oxidation layer thickness is 1～2um; The field oxide thickness of said quaternary composite bed is 1～2um, and the isolation oxidation layer thickness is 1～2um, and the silicon oxynitride thickness of oxide layer is 0.1～0.6um, and the silicon dioxide thickness of oxide layer is 3～6um.
Said cellular adopts the Spacer structure; Said Spacer structure is meant that said P well region and N well region form deposit layer oxide film on entire chip afterwards; Wet etching oxide-film then; Because wet etching has anisotropy, oxide-film is different in the corrosion rate at edge and smooth place, causes edge can stay the masking layer of oxide layer.
Said N+ emitter region and P+ emitter region form as injecting masking layer with the Spacer structure.
Compared with prior art, beneficial effect of the present invention is: the reliability of this device is high, and stability is strong, and cost is low; Silicon oxynitride layer in the multistage field plate has the effect of corrosion barrier layer, and is low to the etching process required precision; And silicon oxynitride layer compactness is good, and the ability that has stronger prevention foreign matter ion to invade improves transistorized stability and reliability; The multistage field plate that contains silicon oxynitride layer can be saved device area; Emitter adopts the grooving formula, and can when reducing ohmic contact resistance, increase metal contact area at the grooving rear side to the corrosion oxidation layer, makes heat radiation more even, and the hot properties of device is better.
Description of drawings
Fig. 1 is the structure chart of insulated gate bipolar transistor IGBT in the prior art;
Fig. 2 is the profile of insulated gate bipolar transistor IGBT in the prior art;
Fig. 3 is the profile of the utility model embodiment;
Fig. 4 is the electrode sketch map without sideetching;
Fig. 5 is the electrode sketch map through sideetching.
Embodiment
Below in conjunction with accompanying drawing the embodiment of the utility model is done further supplementary notes.
As shown in Figure 3, a kind of insulated gate bipolar transistor, said transistor comprise cellular region, termination environment and the scribe line that single cellular is formed in parallel; Said cellular region comprises polygate electrodes G (Gate), metal emitting E (Emitter), the N+ emitter region that is connected with said emitter E (Emitter) and P+ emitter region, N well region, P well region, N-substrate, transparent collector district BackP+ and collector electrode C (Collector); Said termination environment comprises multistage field plate, N-substrate, transparent collector district BackP+ and collector electrode C (Collector); Said transparent collector district BackP+ is positioned at the centre of said N-substrate and collector electrode C (Collector), and said multistage field plate is positioned at the top of N-substrate.
Cellular region is formed in parallel by a lot of cellulars, shares the electric current of this chip jointly, and each cellular has essentially identical current potential on the surface.
Said metal emitting E (Emitter) is a grooving formula structure, and at the grooving rear side to the corrosion oxidation layer.Very grooving formula of said emission structure.The grooving formula be at the window place that isolating oxide layer ILD (Isolate Oxide) opens downward etching to form a degree of depth be 0.2～0.5um, the length of side of going to the bottom is 4.8um, go up bottom side length is the prismatoid groove of 5um; And at the grooving rear side to the corrosion oxidation layer, fill metal at groove again and form metal emitting, can increase the contact area of metal and N+ and P+ like this; Reduce contact resistance; Simultaneously also can increase area of dissipation, make the heat radiation of device more even, hot properties is better.
Said N+ emitter region and said P+ emitter region lay respectively in the N well region and P well region in the said N-substrate.
Said multistage field plate comprises metal emitting, polygate electrodes G (Gate) and oxide layer; Said oxide layer is a hierarchic structure.
Said oxide layer comprises that thickness is the gate oxide GOX (Gate Oxide) of 0.1～0.2um, the field oxide FOX (Field Oxide) that thickness is 1～2um; Thickness is the quaternary composite bed by field oxide FOX (Field Oxide), isolating oxide layer ILD (Isolate Oxide), silicon oxynitride oxide layer and supreme stack formation successively below the silicon dioxide oxide layer that binary composite bed and the thickness by field oxide FOX (Field Oxide) and supreme stack formation successively below the isolating oxide layer ILD (Isolate Oxide) of 2～4um is 5～10um.
The field oxide FOX of said binary composite bed (Field Oxide) thickness is 1～2um, and isolating oxide layer ILD (IsolateOxide) thickness is 1～2um; The field oxide FOX of said quaternary composite bed (Field Oxide) thickness is 1～2um, and isolating oxide layer ILD (Isolate Oxide) thickness is 1～2um, and the silicon oxynitride thickness of oxide layer is 0.1～0.6um, and the silicon dioxide thickness of oxide layer is 3～6um.
Said cellular adopts the Spacer structure; Said Spacer structure is meant that said P well region and N well region form deposit layer oxide film on entire chip afterwards; Wet etching oxide-film then; Because wet etching has anisotropy, oxide-film is different in the corrosion rate at edge and smooth place, causes edge can stay the masking layer of oxide layer.Said cellular adopts the Spacer structure, utilizes a cover reticle to inject P and N type district, can avoid the alignment error, guarantees the consistency of cellular raceway groove, improves dynamic characteristic; Can economize one simultaneously photolithography plate, reduce processing step, practice thrift cost.
Said N+ emitter region and P+ emitter region form as injecting masking layer with the Spacer structure.Said P well region and N well region are same injection windows, annotate boron element Be formation P well region earlier and annotate P elements P formation N well region again.
The application's metal emitting adopts the grooving formula; And make electrode fully contact the N+ emitter region and the P+ emitter region of high concentration to the corrosion oxidation layer at the grooving rear side; Can when reducing ohmic contact resistance, increase metal contact area, make heat radiation more even, the hot properties of device is better; The slot type electrode of sideetching is not seen Fig. 4, and the slot type electrode of sideetching is seen Fig. 5.In order to suppress the generation of insulated gate bipolar transistor IGBT breech lock; The P+ district of the high concentration of also can reinjecting; Cellular region N-substrate injects through the back side and forms the very thin transparent collector district BackP+ of one deck, plays electricity and leads modulating action, makes the insulated gate bipolar transistor IGBT saturation voltage be positive temperature coefficient; Be more suitable for parallel connection, that transparent collector district BackP+ links to each other is collector electrode C (Collector).
Claims (9)
1. igbt, said transistor comprises cellular region, termination environment and scribe line; It is characterized in that: said cellular region comprises polygate electrodes, metal emitting, the N+ emitter region that is connected with said emitter and P+ emitter region, N well region, P well region, N-substrate, transparent collector district and collector electrode; Said termination environment comprises multistage field plate, N-substrate, transparent collector district and collector electrode; Said transparent collector district is positioned at the centre of said N-substrate and collector electrode, and said multistage field plate is positioned at the top of N-substrate.
2. a kind of igbt according to claim 1 is characterized in that: very grooving formula of said emission structure, and at the grooving rear side to the corrosion oxidation layer.
3. a kind of igbt according to claim 1 is characterized in that: said N+ emitter region and said P+ emitter region lay respectively in the N well region and P well region in the said N-substrate.
4. a kind of igbt according to claim 1 is characterized in that: said multistage field plate comprises metal emitting, polygate electrodes and oxide layer.
5. a kind of igbt according to claim 4 is characterized in that: said oxide layer is a hierarchic structure.
6. according to claim 4 or 5 described a kind of insulated gate bipolar transistors, it is characterized in that: said oxide layer comprises that thickness is that gate oxide, the thickness of 0.1～0.2um is the field oxide of 1～2um; Thickness be 2～4um by field oxide and the supreme binary composite bed that constitutes of stack successively below the isolating oxide layer and thickness be 5～10um by field oxide, isolating oxide layer, silicon oxynitride oxide layer and the supreme quaternary composite bed that superposes and constitute successively below the silicon dioxide oxide layer.
7. a kind of igbt according to claim 6 is characterized in that: the field oxide thickness of said binary composite bed is 1～2um, and the isolation oxidation layer thickness is 1～2um; The field oxide thickness of said quaternary composite bed is 1～2um, and the isolation oxidation layer thickness is 1～2um, and the silicon oxynitride thickness of oxide layer is 0.1～0.6um, and the silicon dioxide thickness of oxide layer is 3～6um.
8. a kind of igbt according to claim 1 is characterized in that: said cellular adopts the Spacer structure.
9. a kind of igbt according to claim 1 is characterized in that: said N+ emitter region and P+ emitter region form as injecting masking layer with the Spacer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220151783 CN202633315U (en) | 2012-04-11 | 2012-04-11 | Insulated gate bipolar transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220151783 CN202633315U (en) | 2012-04-11 | 2012-04-11 | Insulated gate bipolar transistor |
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| CN202633315U true CN202633315U (en) | 2012-12-26 |
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| CN 201220151783 Expired - Lifetime CN202633315U (en) | 2012-04-11 | 2012-04-11 | Insulated gate bipolar transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178104A (en) * | 2013-02-20 | 2013-06-26 | 国网智能电网研究院 | Semiconductor device multistage field plate terminal structure and manufacturing method thereof |
| CN103378140A (en) * | 2012-04-11 | 2013-10-30 | 中国电力科学研究院 | Insulated gate bipolar transistor |
-
2012
- 2012-04-11 CN CN 201220151783 patent/CN202633315U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378140A (en) * | 2012-04-11 | 2013-10-30 | 中国电力科学研究院 | Insulated gate bipolar transistor |
| CN103378140B (en) * | 2012-04-11 | 2015-11-04 | 中国电力科学研究院 | A kind of igbt |
| CN103178104A (en) * | 2013-02-20 | 2013-06-26 | 国网智能电网研究院 | Semiconductor device multistage field plate terminal structure and manufacturing method thereof |
| CN103178104B (en) * | 2013-02-20 | 2015-08-19 | 国网智能电网研究院 | A kind of semiconductor device multistage field plate terminal structure and manufacture method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: CHINA ELECTRIC POWER RESEARCH INSTITUTE Effective date: 20140327 Owner name: CHINA ELECTRIC POWER RESEARCH INSTITUTE Effective date: 20140327 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100192 HAIDIAN, BEIJING TO: 100031 XICHENG, BEIJING |
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| TR01 | Transfer of patent right |
Effective date of registration: 20140327 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: China Electric Power Research Institute Address before: 100192 Beijing city Haidian District Qinghe small Camp Road No. 15 Patentee before: China Electric Power Research Institute |
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| CX01 | Expiry of patent term |
Granted publication date: 20121226 |
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| CX01 | Expiry of patent term |