CN213026140U

CN213026140U - Trench MOSFET structure

Info

Publication number: CN213026140U
Application number: CN202022101136.5U
Authority: CN
Inventors: 潘光燃; 胡瞳腾
Original assignee: Shenzhen Semi One Technology Co ltd
Current assignee: Shenzhen Semi One Technology Co ltd
Priority date: 2020-09-22
Filing date: 2020-09-22
Publication date: 2021-04-20
Anticipated expiration: 2030-09-22

Abstract

The utility model discloses a trench MOSFET structure, including substrate and epitaxial layer, the epitaxial layer sets up on the substrate, be provided with slot, gate oxide and polycrystalline silicon on the epitaxial layer, gate oxide sets up the surface of slot, polycrystalline silicon sets up gate oxide's surface just the slot is filled to polycrystalline silicon, the top layer of epitaxial layer is provided with first doping region and second doping region, the second doping region sets up the surface of slot, the spacing distance of first doping region and gate oxide equals the width in second doping region, the doping concentration in second doping region is less than the doping concentration in first doping region. The utility model provides a slot MOSFET's structure has advantages such as less unit area on-resistance, cost are lower.

Description

Trench MOSFET structure

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a trench MOSFET structure.

Background

The MOSFET chip is a discrete device, belongs to the category of semiconductor power devices, and belongs to the field of semiconductor chips with integrated circuits, the most key index parameters of the MOSFET include breakdown voltage (particularly drain-source breakdown voltage), on-resistance and threshold voltage (also called as starting voltage in spoken language), and under the general condition, the larger the breakdown voltage is, the better the on-resistance is, the smaller the on-resistance is. In order to realize the nominal breakdown voltage, an epitaxial layer with specific resistivity and specific thickness is adopted in the internal structure of the MOSFET chip to bear the pressure, and the higher the breakdown voltage which is required to be realized is, the larger the resistivity or (and) thickness of the epitaxial layer is, the larger the on-resistance of the chip per unit area is, so that the on-resistance and the breakdown voltage per unit area are a pair of parameters which are contradictory to each other; the most important work of a chip research and development engineer is to reduce the on-resistance of the MOSFET chip to the maximum extent, and in order to reduce the on-resistance of the MOSFET chip, the most direct method is to increase the area of the chip, but the method also increases the cost of the chip most directly, so that it is the responsibility of the chip research and development engineer to improve the on-resistance per unit area to the maximum extent.

The prior art has the following disadvantages: as shown in fig. 2, the trench MOSFET structure includes a body region and an epitaxial layer forming a PN junction (referred to as body region junction), a polysilicon gate, a gate oxide layer and an epitaxial layer forming an M-O-S capacitor, wherein when a drain terminal is subjected to a high potential, the PN junction and the M-O-S capacitor are both in a reverse bias state, and an electric field is relatively concentrated at a junction position (region marked by a circle in fig. 2) of the PN junction and the M-O-S capacitor, so that the MOSFET is prone to breakdown at the junction position; in order to realize the target breakdown voltage, an epitaxial layer with higher resistivity or (and) thickness needs to be adopted, so that the on-resistance of the chip per unit area is not small due to the influence of the factor, the target on-resistance can be realized only by the larger chip area, and the chip cost is higher.

SUMMERY OF THE UTILITY MODEL

The utility model provides a trench MOSFET structure aims at solving the big problem of chip unit area's on-resistance.

According to the embodiment of the application, a trench MOSFET structure is provided, including substrate and epitaxial layer, the epitaxial layer sets up on the substrate, be provided with slot, gate oxide and polycrystalline silicon on the epitaxial layer, the gate oxide sets up the surface of slot, the polycrystalline silicon sets up the surface of gate oxide just the slot is filled to the polycrystalline silicon, the top layer of epitaxial layer is provided with first doping region and second doping region, the second doping region sets up the surface of slot, the interval distance of first doping region and gate oxide equals the width in second doping region, the doping concentration in second doping region is less than the doping concentration in first doping region.

Preferably, a third doped region is arranged on the surface layer of the epitaxial layer, the depth of the third doped region is smaller than that of the first doped region, and the depth of the third doped region is smaller than that of the second doped region.

Preferably, the lower surface layer of the substrate is a drain of the MOSFET, the polysilicon is a gate of the MOSFET, the third doped region is a source region of the MOSFET, and the first doped region and the second doped region constitute a body region of the MOSFET.

Preferably, the substrate is an N-type substrate, the epitaxial layer is an N-type epitaxial layer, the first doped region is a first P-type doped region, the second doped region is a second P-type doped region, and the third doped region is an N-type doped region.

Preferably, the substrate is a P-type substrate, the epitaxial layer is a P-type epitaxial layer, the first doped region is a first N-type doped region, the second doped region is a second N-type doped region, and the third doped region is a P-type doped region.

Preferably, the depth of the trench is less than the thickness of the epitaxial layer.

Preferably, the depth of the first doped region and the depth of the second doped region are smaller than the depth of the trench.

Preferably, the width of the second doped region is 0.2-0.5 microns.

Preferably, the depth of the third doped region is 0.15-0.4 microns.

The technical scheme provided by the embodiment of the application can have the following beneficial effects: the application designs a trench MOSFET structure, a body region is composed of a first doped region and a second doped region, the doping concentration of the second doped region is lower than that of the first doped region, wherein the second doped region with lower doping concentration is close to a gate oxide layer, and as the doping concentration of the second doped region is lower than that of the first doped region, the breakdown voltage of a PN junction is higher as the doping concentration of the PN junction is lower, and the breakdown voltage of the PN junction formed by the second doped region and an epitaxial layer is higher than that of the PN junction formed by the first doped region and the epitaxial layer, the electric field concentration effect of the junction position of an M-O-S capacitor and the body region junction formed by a polysilicon gate oxide layer-epitaxial layer can be weakened (namely, the region marked by a circle in figure 4, and the electric field of the region can be weakened), so that the breakdown voltage of the trench MOSFET structure is improved. That is, compare prior art, adopt the utility model discloses can obtain the breakdown voltage higher than prior art, or obtain littleer unit area on-resistance under the condition that realizes the same breakdown voltage.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of a prior art trench MOSFET structure;

FIG. 2 is another schematic diagram of a prior art trench MOSFET structure;

fig. 3 is a schematic diagram of a trench MOSFET structure of the present invention;

fig. 4 is another schematic diagram of the trench MOSFET structure of the present invention.

Description of reference numerals:

10. a trench MOSFET structure; 1. a substrate; 2. an epitaxial layer; 3. a trench; 4. a gate oxide layer; 5. polycrystalline silicon; 6. a first doped region; 7. a second doped region; 8. a third doped region.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 3 and 4, the utility model discloses a trench MOSFET structure 10, including substrate 1 and epitaxial layer 2, epitaxial layer 2 sets up on substrate 1, be provided with slot 3, gate oxide 4 and polycrystalline silicon 5 on epitaxial layer 2, gate oxide 4 sets up the surface of slot 3, polycrystalline silicon 5 sets up the surface of gate oxide 4 just polycrystalline silicon 5 fills slot 3, the top layer of epitaxial layer 2 is provided with first doped region 6 and second doped region 7, second doped region 7 sets up the surface of slot 3, the spacing distance of first doped region 6 and gate oxide 4 equals the width of second doped region 7, the doping concentration of second doped region 7 is less than the doping concentration of first doped region 6.

The utility model provides a trench MOSFET structure, the body region is composed of a first doped region 6 and a second doped region 7, the doping concentration of the second doped region 7 is lower than that of the first doped region 6, wherein the second doping region 7 with lower doping concentration is close to the gate oxide layer 4, because the doping concentration of the second doping region 7 is smaller than that of the first doping region 6, the smaller the doping concentration of the PN junction is, the higher the breakdown voltage is, the PN junction formed by the second doped region 7 and the epitaxial layer 2 has a higher breakdown voltage than the PN junction formed by the first doped region 6 and the epitaxial layer 2, therefore, the electric field concentration effect at the junction of the M-O-S capacitor formed by the polysilicon gate, the gate oxide layer and the epitaxial layer and the body region can be weakened (i.e., the region marked by the circle in fig. 4, the electric field in this region can be weakened by the scheme), and the breakdown voltage of the trench MOSFET structure 10 can be improved. That is, compare prior art, adopt the utility model discloses can obtain the breakdown voltage higher than prior art, or obtain littleer unit area on-resistance under the condition that realizes the same breakdown voltage.

The surface layer of the epitaxial layer 2 is provided with a third doped region 8, the depth of the third doped region 8 is smaller than that of the first doped region 6, and the depth of the third doped region 8 is smaller than that of the second doped region 7.

In this embodiment, the lower surface layer of the substrate 1 is a drain of the MOSFET, the polysilicon 5 is a gate of the MOSFET, the third doped region 8 is a source region of the MOSFET, the first doped region 6 and the second doped region 7 form a body region of the MOSFET, and the drain, the gate, the source region and the body region are names of conventional structures in the prior art and are not described herein again.

The depth of the trenches 3 is less than the thickness of the epitaxial layer 2. Optionally, the depth of the trench 3 is 1.3 microns, and the thickness of the epitaxial layer is 3 microns. The depth of the first doping region 6 and the depth of the second doping region 7 are smaller than the depth of the groove 3. Preferably, the width of the second doped region 7 is 0.2-0.5 micrometer. Preferably, the depth of the third doped region 8 is 0.15-0.4 microns.

In this embodiment, the substrate 1 is an N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, the first doped region 6 is a first P-type doped region, the second doped region 7 is a second P-type doped region, and the third doped region 8 is an N-type doped region.

Optionally, in some other embodiments, the substrate 1 is a P-type substrate, the epitaxial layer 2 is a P-type epitaxial layer, the first doped region 6 is a first N-type doped region, the second doped region 7 is a second N-type doped region, and the third doped region 8 is a P-type doped region.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A trench MOSFET structure characterized by: including substrate and epitaxial layer, the epitaxial layer sets up on the substrate, be provided with slot, gate oxide and polycrystalline silicon on the epitaxial layer, the gate oxide sets up the surface of slot, the polycrystalline silicon sets up the surface of gate oxide just the slot is filled to the polycrystalline silicon, the top layer of epitaxial layer is provided with first doping region and second doping region, the second doping region sets up the surface of slot, the interval distance of first doping region and gate oxide equals the width in second doping region, the doping concentration in second doping region is less than the doping concentration in first doping region.

2. The trench MOSFET structure of claim 1, wherein: the surface layer of the epitaxial layer is provided with a third doped region, the depth of the third doped region is smaller than that of the first doped region, and the depth of the third doped region is smaller than that of the second doped region.

3. The trench MOSFET structure of claim 2, wherein: the lower surface layer of the substrate is a drain of the MOSFET, the polycrystalline silicon is a gate of the MOSFET, the third doped region is a source region of the MOSFET, and the first doped region and the second doped region form a body region of the MOSFET.

4. The trench MOSFET structure of claim 3, wherein: the substrate is an N-type substrate, the epitaxial layer is an N-type epitaxial layer, the first doped region is a first P-type doped region, the second doped region is a second P-type doped region, and the third doped region is an N-type doped region.

5. The trench MOSFET structure of claim 3, wherein: the substrate is a P-type substrate, the epitaxial layer is a P-type epitaxial layer, the first doped region is a first N-type doped region, the second doped region is a second N-type doped region, and the third doped region is a P-type doped region.

6. The trench MOSFET structure of claim 3, wherein: the depth of the trench is less than the thickness of the epitaxial layer.

7. The trench MOSFET structure of claim 6, wherein: the depth of the first doping area and the depth of the second doping area are smaller than the depth of the groove.

8. The trench MOSFET structure of claim 7, wherein: the width of the second doped region is 0.2-0.5 microns.

9. The trench MOSFET structure of claim 8, wherein: the depth of the third doped region is 0.15-0.4 microns.