CN113284805A - Manufacturing method of MOS (Metal oxide semiconductor) tube - Google Patents

Manufacturing method of MOS (Metal oxide semiconductor) tube Download PDF

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Publication number
CN113284805A
CN113284805A CN202110525828.9A CN202110525828A CN113284805A CN 113284805 A CN113284805 A CN 113284805A CN 202110525828 A CN202110525828 A CN 202110525828A CN 113284805 A CN113284805 A CN 113284805A
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China
Prior art keywords
doped region
layer
oxide layer
depth
forming
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CN202110525828.9A
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徐晓辉
杨伟勋
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Shenzhen Jeelyton Electronics Co ltd
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Shenzhen Jeelyton Electronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a manufacturing method of an MOS (metal oxide semiconductor) tube, which comprises the following steps of S1: forming an epitaxial layer on the surface of a substrate; step S2: forming a groove, a gate oxide layer and a polycrystalline silicon layer on the surface of the epitaxial layer in sequence; step S3: depositing a polycrystalline silicon layer, removing the polycrystalline silicon layer outside the trench, and forming a first doped region and a second doped region on the sequential surface of the epitaxial layer, wherein the second doped region is arranged on the outer surface of the trench, the spacing distance between the first doped region and the gate oxide layer is equal to the width of the second doped region, and the doping concentration of the second doped region is less than that of the first doped region; step S4: and forming a third doped region on the surface layer of the first doped region, wherein the depth of the third doped region is less than that of the first doped region, and the depth of the third doped region is less than that of the second doped region. The manufacturing method of the MOS tube provided by the invention has the advantages of smaller on-resistance per unit area, lower cost and the like.

Description

Manufacturing method of MOS (Metal oxide semiconductor) tube
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an MOS (metal oxide semiconductor) tube.
Background
The MOS tube chip is a discrete device, belongs to the category of semiconductor power devices, and belongs to the field of semiconductor chips with integrated circuits, the most key index parameters of the MOS tube comprise breakdown voltage (particularly drain-source breakdown voltage), on-resistance and threshold voltage (also called as starting voltage in spoken language), and under the general condition, the larger the breakdown voltage is, the better the on-resistance is, the smaller the on-resistance is, the better the breakdown voltage is. In order to realize the nominal breakdown voltage, the internal structure of the MOS chip is pressurized by adopting an epitaxial layer with specific resistivity and specific thickness, and the higher the breakdown voltage is, the larger the resistivity or (and) thickness of the epitaxial layer is, the larger the on-resistance of the chip per unit area is, so that the on-resistance and the breakdown voltage per unit area are a pair of contradictory parameters; the most important work of chip research and development engineers is to reduce the on-resistance of the MOS chip to the maximum extent, and the most direct method is to increase the area of the chip in order to reduce the on-resistance of the MOS chip, but this method also increases the cost of the chip most directly, so that it is the responsibility of the chip research and development engineers to improve the on-resistance per unit area to the maximum extent.
The prior art has the following disadvantages: referring to fig. 1, a PN junction (referred to as a body junction) is formed by the body region and the epitaxial layer, an M-O-S capacitor is formed by the polysilicon gate, the gate oxide layer and the epitaxial layer, and when the drain terminal bears a high potential, the PN junction and the M-O-S capacitor are in a reverse bias state, and at the junction position of the PN junction and the M-O-S capacitor, an electric field is concentrated, and the MOS transistor is easily broken down at the junction position; in order to realize the target breakdown voltage, an epitaxial layer with higher resistivity or (and) thickness needs to be adopted, so that the on-resistance of the chip per unit area is not small due to the influence of the factor, the target on-resistance can be realized only by the larger chip area, and the chip cost is higher.
Disclosure of Invention
The invention provides a manufacturing method of an MOS (metal oxide semiconductor) tube, aiming at solving the problem of large on-resistance of a chip per unit area.
According to the embodiment of the application, a manufacturing method of a MOS tube is provided, which comprises the following steps:
step S1: forming an epitaxial layer on the surface of a substrate;
step S2: forming a groove, a gate oxide layer and a polycrystalline silicon layer on the surface of the epitaxial layer in sequence;
step S3: depositing a polycrystalline silicon layer, removing the polycrystalline silicon layer outside the trench, and forming a first doped region and a second doped region on the sequential surface of the epitaxial layer, wherein the second doped region is arranged on the outer surface of the trench, the spacing distance between the first doped region and the gate oxide layer is equal to the width of the second doped region, and the doping concentration of the second doped region is less than that of the first doped region;
step S4: and forming a third doped region on the surface layer of the first doped region, wherein the depth of the third doped region is less than that of the first doped region, and the depth of the third doped region is less than that of the second doped region.
Preferably, the step S2 includes the steps of:
step S21: forming a mask on the surface of the epitaxial layer, wherein the mask comprises a first oxide layer, a second oxide layer and first silicon nitride, the first oxide layer is formed on the surface of the epitaxial layer, the first silicon nitride is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the first silicon nitride;
step S22: and forming a groove in the epitaxial layer, removing the second oxide layer, and growing a gate oxide layer on the surface of the groove.
Preferably, the lower surface layer of the substrate is a drain of an MOS transistor, the polysilicon layer is a gate of the MOS transistor, the third doped region is a source region of the MOS transistor, and the first doped region and the second doped region form a body region of the MOS transistor.
Preferably, the depth of the trench is less than the thickness of the epitaxial layer.
Preferably, the depth of the first doped region and the depth of the second doped region are smaller than the depth of the trench.
Preferably, the width of the second doped region is 0.2-0.5 microns.
Preferably, the depth of the third doped region is 0.15-0.4 microns.
Preferably, the substrate is bulk silicon or silicon-on-insulator SOI.
The technical scheme provided by the embodiment of the application can have the following beneficial effects: the application designs a manufacturing method of an MOS tube, the doping concentration of a second doping region is lower than that of a first doping region of the MOS tube obtained by the manufacturing method, wherein the second doping region with lower doping concentration is close to a gate oxide layer, and as the doping concentration of the second doping region is smaller than that of the first doping region, the breakdown voltage of a PN junction is higher as the doping concentration of the second doping region is smaller than that of the first doping region, and the breakdown voltage of the PN junction formed by the second doping region and an epitaxial layer is higher than that of the PN junction formed by the first doping region and the epitaxial layer, the electric field concentration effect of the junction position of an M-O-S capacitor and a body junction formed by a polysilicon gate oxide layer-epitaxial layer can be weakened, and the breakdown voltage of the manufacturing method of the MOS tube is improved. That is, compared with the prior art, the invention can obtain higher breakdown voltage than the prior art, or obtain smaller on-resistance per unit area under the condition of realizing the same breakdown voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art MOS transistor structure;
FIG. 2 is a schematic flow chart of a method for manufacturing a MOS transistor according to the present invention;
fig. 3 is a schematic flow chart of step S2 in the method for manufacturing a MOS transistor according to the present invention;
fig. 4 is a schematic structural diagram of a MOS transistor manufactured by the method for manufacturing a MOS transistor according to the present invention.
Description of reference numerals:
10. a manufacturing method of the MOS tube; 1. a substrate; 2. an epitaxial layer; 3. a trench; 4. a gate oxide layer; 5. a polysilicon layer; 6. a first doped region; 7. a second doped region; 8. a third doped region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 2 in combination with fig. 4, the present invention discloses a method 10 for manufacturing a MOS transistor, which includes the following steps:
step S1: forming an epitaxial layer 2 on the surface of a substrate 1;
step S2: forming a groove 3, a gate oxide layer 4 and a polycrystalline silicon layer 5 on the surface of the epitaxial layer 2 in sequence;
step S3: depositing a polycrystalline silicon layer 5, removing the polycrystalline silicon layer 5 outside the trench 3, forming a first doped region 6 and a second doped region 7 on the sequential surface of the epitaxial layer 2, wherein the second doped region 7 is arranged on the outer surface of the trench 3, the spacing distance between the first doped region 6 and the gate oxide layer 4 is equal to the width of the second doped region 7, and the doping concentration of the second doped region 7 is less than that of the first doped region 6;
step S4: and forming a third doped region 8 on the surface layer of the first doped region 6, wherein the depth of the third doped region 8 is less than that of the first doped region 6, and the depth of the third doped region 8 is less than that of the second doped region 7.
Referring to fig. 3 in conjunction with fig. 4, the step S2 includes the following steps:
step S21: forming a mask on the surface of the epitaxial layer 2, wherein the mask comprises a first oxide layer, a second oxide layer and first silicon nitride, the first oxide layer is formed on the surface of the epitaxial layer 2, the first silicon nitride is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the first silicon nitride;
step S22: a trench 3 is formed in the epitaxial layer 2, the second oxide layer is removed, and a gate oxide layer 4 is grown on the surface of the trench 3.
Referring to fig. 4, it can be understood that the lower surface layer of the substrate 1 is a drain of an MOS transistor, the polysilicon layer 5 is a gate of the MOS transistor, the third doped region 8 is a source region of the MOS transistor, and the first doped region 6 and the second doped region 7 form a body region of the MOS transistor.
It will be appreciated that the depth of the trenches 3 is less than the thickness of the epitaxial layer 2.
It is understood that the depth of the first doped region 6 and the depth of the second doped region 7 are smaller than the depth of the trench 3.
It will be appreciated that the width of the second doped region 7 is 0.2-0.5 microns.
It will be appreciated that the third doped region 8 has a depth of 0.15-0.4 microns.
It will be appreciated that the substrate 1 is bulk silicon or silicon-on-insulator SOI.
The technical scheme provided by the embodiment of the application can have the following beneficial effects: the application designs a manufacturing method of an MOS tube, the doping concentration of a second doping region is lower than that of a first doping region of the MOS tube obtained by the manufacturing method, wherein the second doping region with lower doping concentration is close to a gate oxide layer, and as the doping concentration of the second doping region is smaller than that of the first doping region, the breakdown voltage of a PN junction is higher as the doping concentration of the second doping region is smaller than that of the first doping region, and the breakdown voltage of the PN junction formed by the second doping region and an epitaxial layer is higher than that of the PN junction formed by the first doping region and the epitaxial layer, the electric field concentration effect of the junction position of an M-O-S capacitor and a body junction formed by a polysilicon gate oxide layer-epitaxial layer can be weakened, and the breakdown voltage of the manufacturing method of the MOS tube is improved. That is, compared with the prior art, the invention can obtain higher breakdown voltage than the prior art, or obtain smaller on-resistance per unit area under the condition of realizing the same breakdown voltage.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A manufacturing method of a MOS tube is characterized in that: the method comprises the following steps:
step S1: forming an epitaxial layer on the surface of a substrate;
step S2: forming a groove, a gate oxide layer and a polycrystalline silicon layer on the surface of the epitaxial layer in sequence;
step S3: depositing a polycrystalline silicon layer, removing the polycrystalline silicon layer outside the trench, and forming a first doped region and a second doped region on the sequential surface of the epitaxial layer, wherein the second doped region is arranged on the outer surface of the trench, the spacing distance between the first doped region and the gate oxide layer is equal to the width of the second doped region, and the doping concentration of the second doped region is less than that of the first doped region;
step S4: and forming a third doped region on the surface layer of the first doped region, wherein the depth of the third doped region is less than that of the first doped region, and the depth of the third doped region is less than that of the second doped region.
2. The method of claim 1, further comprising the steps of: the step S2 includes the steps of:
step S21: forming a mask on the surface of the epitaxial layer, wherein the mask comprises a first oxide layer, a second oxide layer and first silicon nitride, the first oxide layer is formed on the surface of the epitaxial layer, the first silicon nitride is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the first silicon nitride;
step S22: and forming a groove in the epitaxial layer, removing the second oxide layer, and growing a gate oxide layer on the surface of the groove.
3. The method of claim 1, further comprising the steps of: the lower surface layer of the substrate is a drain of the MOS tube, the polycrystalline silicon layer is a gate of the MOS tube, the third doped region is a source region of the MOS tube, and the first doped region and the second doped region form a body region of the MOS tube.
4. The method of claim 3, wherein: the depth of the trench is less than the thickness of the epitaxial layer.
5. The method of claim 4, wherein: the depth of the first doping area and the depth of the second doping area are smaller than the depth of the groove.
6. The method of claim 1, wherein: the width of the second doped region is 0.2-0.5 microns.
7. The method of claim 1, wherein: the depth of the third doped region is 0.15-0.4 microns.
8. The method of claim 1, wherein: the substrate is bulk silicon or silicon-on-insulator SOI.
CN202110525828.9A 2021-05-14 2021-05-14 Manufacturing method of MOS (Metal oxide semiconductor) tube Pending CN113284805A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221731A1 (en) * 2014-02-04 2015-08-06 Maxpower Semiconductor, Inc. Vertical power mosfet having planar channel and its method of fabrication
CN112103185A (en) * 2020-09-22 2020-12-18 深圳市芯电元科技有限公司 Manufacturing method and structure of trench MOSFET
CN213026140U (en) * 2020-09-22 2021-04-20 深圳市芯电元科技有限公司 Trench MOSFET structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221731A1 (en) * 2014-02-04 2015-08-06 Maxpower Semiconductor, Inc. Vertical power mosfet having planar channel and its method of fabrication
CN112103185A (en) * 2020-09-22 2020-12-18 深圳市芯电元科技有限公司 Manufacturing method and structure of trench MOSFET
CN213026140U (en) * 2020-09-22 2021-04-20 深圳市芯电元科技有限公司 Trench MOSFET structure

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