CN103972174B - SiGe bodies area longitudinal direction 1T-DRAM devices and its manufacturing method - Google Patents
SiGe bodies area longitudinal direction 1T-DRAM devices and its manufacturing method Download PDFInfo
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- CN103972174B CN103972174B CN201310035130.4A CN201310035130A CN103972174B CN 103972174 B CN103972174 B CN 103972174B CN 201310035130 A CN201310035130 A CN 201310035130A CN 103972174 B CN103972174 B CN 103972174B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The present invention provides a kind of longitudinal nano-pillar 1T-DRAM devices and array based on SiGe energy band engineerings, use longitudinal nano-pillar transistor, the use of the lamination being epitaxially formed is respectively channel region and drain region, big space is provided to the design in channel region and drain region, this provides many embodiments for the promotion of 1T-DRAM performances；Simultaneously, the structure of vertical transistor is conducive to the integrated of SiGe channel regions, using epitaxy Si Ge as channel region, utilizes the difference of SiGe and Si valence band, the potential well in hole has been manufactured in channel region, 1 state of reading of 1T-DRAM can be effectively improved and has read the current difference between 0 state.
Description
Technical field
The present invention relates to semiconductor devices and its method field of manufacturing more particularly to a kind of indulging based on SiGe energy band engineerings
To high integration transistor arrangement and its manufacturing method.
Background technology
With the continuous diminution of semiconductor device characteristic size, traditional 1T/1C embedded DRAMs unit size
It is reducing, the area of capacitance becomes more and more difficult with scaled (scaling down), and preparation process is also more next
It is more complicated, with logical device technique compatibility worse and worse.Therefore, with the good capless DRAM of logical device compatibility
(Capacitorless DRAM) will have good development prospect in the high-performance embedded fields DRAM of VLSI.Wherein using floating
1T-DRAM (the One Transistor Dynamic Random Access of bulk effect (floating body effect)
Memory) the main realization method for being 1T-DRAM.
1T-DRAM is generally a SOI floating body (floating body) transistor, charges when to its body area, and the areas Ji Ti are empty
One writing is completed in the accumulation in cave, is at this moment caused body effect since body area hole accumulates, is led to the threshold voltage drop of transistor
It is low.It discharges when to its body area, i.e., the hole accumulated by its body area of the positive assistant general of body drain PN junction bleeds off to complete to write " 0 ", at this moment serves as a contrast
Bottom effect disappears, and threshold voltage recovering is normal, and firing current increases.And read operation is source when reading the transistor open state
Leakage current, since " 1 " is different with the threshold voltage of " 0 " state, the two source-drain current is also different, indicates to read when large
Be " 1 ", and it is smaller when indicate read be " 0 ".
Currently, the mechanism to charge to body area is broadly divided into：Using saturation region ionization by collision excitation parasitism BJT effects come
Hole is accumulated in body area and hole is accumulated using the areas GIDL effect Shi Ti.In comparison, the 1T- of impact ionization is utilized
DRAM, due to becoming research hotspot with higher speed and good reliability.
Realize that the structure of IT-DRAM is generally based on the planar structure of SOI at present, and the 1T-DRAM of SOI planar structures is deposited
Main problem be：Body potential is limited by body area and the hole potential barrier of source and leakage.Since conventional silicon semiconductor forbidden band is wide
Spend limited, the variation of body potential is restricted, and the variation of threshold voltage is smaller, this makes the signal code read smaller.This
The substrate of outer SOI and the bulk silicon technological being widely used at present are incompatible, and there are problems that not easy heat radiation.
Invention content
The present invention, which is directed to embedded DRAM field in existing VLSI technologies, has the capless 1T- of good development prospect
DRAM cell structure proposes a kind of longitudinal nano-pillar 1T-DRAM devices and array of the high integration based on SiGe energy band engineerings
And its manufacturing method.The present invention optimizes 1T-DRAM, realizes floater effect using longitudinal nano-pillar transistor, and use
Epitaxy Si Ge bodies area easy of integration, therefore while reducing unit area, raising integrated level, signal margin can be increased.
According to an aspect of the present invention, the present invention provides a kind of method, semi-conductor device manufacturing method, wherein including walking as follows
Suddenly：
Step 1, source region of the N+ doped layers as transistor is formed on substrate；
Step 2, it is epitaxially formed SiGe layer over the substrate；
Step 3, using first layer mask plate, the SiGe layer is etched, forms raceway groove of the SiGe nano-pillars as transistor
Region；
Step 4, Si cap layers are deposited；
Step 5, the first interlayer dielectric layer is deposited；
Step 6, using second layer mask plate, first interlayer dielectric layer is performed etching；
Step 7, high-K gate dielectric material layer and metal gate material layer are sequentially depositing；
Step 8, using CMP process, part first interlayer dielectric layer, the high-K gate dielectric material layer and institute are removed
Metal gate material layer is stated, until exposing the upper surface of the Si cap layers, the remaining metal gate material layer is formed as
Metal gates namely wordline；
Step 9, selective epitaxial is carried out in the upper surface of the exposed Si cap layers, forms Si epitaxial layers；
Step 10, the Si epitaxial layers described to part carry out thermal oxidation；
Step 11, the second interlayer dielectric layer is deposited；
Step 12, using CMP process, part second interlayer dielectric layer is removed, until exposing the Si epitaxial layers
Upper surface；
Step 13, the first metal wiring layer is deposited, is patterned using third layer mask plate, to form bit line.
According to another aspect of the present invention, the present invention provides a kind of semiconductor devices comprising：
Semiconductor substrate；N+ doped layers on the semiconductor substrate are the source region of transistor；Positioned at institute
The SiGe nano-pillars on N+ doped layers are stated, are the channel region of transistor；Si extensions on the SiGe nano-pillars
Layer is the drain region of transistor；High-K gate dielectric material layer and wordline enclose the SiGe nano-pillars, are the ring of transistor
Shape grid；Bit line on the Si epitaxial layers.
In the present invention, in the SiGe nano-pillars atom percentage content of Ge between 20%~30%；The N+
The impurity of doped layer is arsenic, doping concentration 1*1020cm-3；The wordline connects a line 1T-DRAM units, between adjacent cells
The wordline be isolated by first interlayer dielectric layer；One row 1T-DRAM units of the bit line connection；It is being formed by unit
In, the diameter of the Si epitaxial layers is less than the diameter of the SiGe nano-pillars.
Description of the drawings
The method, semi-conductor device manufacturing method flow and its structural schematic diagram of 0 present invention of Fig. 1-2
Specific implementation mode
Hereinafter, describing the present invention by specific embodiment shown in the accompanying drawings.However, it should be understood that these descriptions are
Illustratively, it is not intended to limit the scope of the present invention.In addition, in the following description, it is omitted to known features and technology
Description, so as not to unnecessarily obscure the concept of the present invention.
First, the present invention provides a kind of method, semi-conductor device manufacturing method, and manufacturing process is referring to attached drawing 1-20.
First, it is a domain of the 1T-DRAM device architectures and array in the embodiment of the present invention referring to attached drawing 1, including
Three layers.It is a 1T-DRAM unit in Fig. 1 dashed rectangles.Horizontal dotted line Aa indicates, along bit line extending direction, to indulge dotted line Bb and indicate edge
Wordline extending direction, Fig. 5~Figure 19 are the cross-sectional view in the directions Aa, and Figure 20 is the cross-sectional view in the directions Bb.In addition, Fig. 2 is this
The figure of the 1T-DRAM device architectures of inventive embodiments and the first layer mask of array is the mask of nano-pillar figure；Figure
3 be the embodiment of the present invention 1T-DRAM device architectures and array second layer mask figure, be wordline mask；Fig. 4
Be the embodiment of the present invention 1T-DRAM device architectures and array third layer mask figure, be bit line mask.
First, referring to attached drawing 5, substrate 1 is provided.Substrate 1 in the present embodiment is semiconductor substrate, such as monocrystalline silicon lining
Bottom has P- doping types.Optionally, substrate 1 is the semi-conducting materials such as germanium silicon, gallium nitride.
Then, referring to attached drawing 6, impurity injection is carried out on substrate 1, forms N+ doped layers 2.Wherein, doping type is arsenic,
Doping concentration is 1*1020cm-3, peak dopant is distributed between 5nm~30nm.Optionally, annealing process is carried out after the implantation.
Source region of the N+ doped layers 2 as transistor, therefore, all 1T-DRAM sources are in an equipotential in Fig. 1 arrays.
Then, referring to attached drawing 7, it is epitaxially formed SiGe layer 3.Wherein, in SiGe layer 3 atom percentage content of Ge 20%
Between~30%.In addition, being delayed outside, doped in situ (in-situ doping), such as boron doping, concentration can be carried out at the same time
For 1*1015cm-3.The thickness of SiGe layer 3 is preferably 10~50nm.
Then, nano-pillar figure photoetching is carried out using first layer mask plate referring to attached drawing 8, SiGe layer 3 is etched, to shape
At SiGe nano-pillars 31.SiGe nano-pillars 31 are used as the channel region of transistor body area namely transistor.The step specifically includes：
The coating of photoresist is exposed with first layer mask plate, carries out anisotropic etching to the SiGe layer 3 exposed later, directly
To N+ doped layers 2.The height of SiGe nano-pillars 31 is equal with the thickness of SiGe layer 3, and diameter is preferably 10~40nm.Together
When, the height of SiGe nano-pillars 31 also determines the channel length of vertical transistor.
Then, referring to attached drawing 9, comprehensive deposition Si cap layers 4.Depositing operation includes CVD, and thickness 5nm, Si cap layers 4 are complete
All standing and enclose SiGe nano-pillars 31.Si cap layers 4 have 1*1015cm-3Arsenic doping, can be used for improve interface spy
Property.
Then, referring to attached drawing 10, the first interlayer dielectric layer 5 is deposited.The material of first interlayer dielectric layer 5 is optionally dioxy
SiClx covers SiGe nano-pillars 31 and Si cap layers 4 comprehensively.After depositing the first interlayer dielectric layer 5, it usually needs carry out
CMP process, to obtain the surface of the first flat interlayer dielectric layer 5.
Then, referring to attached drawing 11, photoresist is coated, is exposed using second layer mask plate, form patterning photoresist
Layer 6.Later, to pattern photoresist layer 6 as mask is carried out to the first interlayer dielectric layer 5 anisotropy quarter referring to attached drawing 12
Erosion, until exposing the Si cap layers 4 of 5 lower section of the first interlayer dielectric layer.After the completion of etching, patterning photoresist layer 6 is removed.
Then, referring to attached drawing 13, high-K gate dielectric material layer 7 and metal gate material layer 8 are sequentially depositing.Wherein, work is deposited
Skill includes CVD, ALD etc..The material choosing of high-K gate dielectric material layer 7 includes HfSiOx、HfSiON、HfAlOx、HfTaOx、
HfLaOx、HfAlSiOxAnd HfLaSiOxAt least one including hafnium base high K dielectric material, the material of metal gate material layer 8
For metal, alloy or metallic compound, such as TiN, TaN, W etc..Wherein, the EOT of high-K gate dielectric material layer 7 is 1~2nm.
Then, be terminal with Si cap layers 4 using CMP process referring to attached drawing 14, remove segments first layer between dielectric layer 5,
High-K gate dielectric material layer 7 and metal gate material layer 8, expose the upper surface of Si cap layers 4.Remaining metal gate material layer 8
Be formed as metal gates namely wordline 9.
Then, referring to attached drawing 15, selective epitaxial is carried out in the upper surface of exposed Si cap layers 4, forms Si epitaxial layers 10.
Si epitaxial layers 10 are used as the drain region of transistor, and height is 10~50nm.During extension, doped in situ may be used
(in-situ doping), such as arsenic doped, it is 1*10 to form doping concentration20cm-3Si epitaxial layers 10.In this way, just being formed
Stratiform doped structure from bottom to top：1*10 before this15cm-3Boron doped SiGe layer 3, then transitions to 1*1015cm-3Arsenic
The Si cap layers 4 of doping, are finally transitioned into the 1*10 of top layer gradually20cm^-3The Si epitaxial layers 10 of arsenic doping.Such structure
The structure for advantageously forming drain-gate not overlap-extension PCR (drain to gate underlap) is conducive to the guarantor for improving 1T-DRAM
Hold the time.
Then, referring to attached drawing 16, thermal oxide is carried out to Si epitaxial layers 10, forms the silicon oxide layer for surrounding Si epitaxial layers 10
11.Since thermal oxidation technology can consume part Si epitaxial layers 10, after this step, the size of Si epitaxial layers 10 will contract
Small, in this way, the diameter of Si epitaxial layers 10 is less than the diameter of SiGe nano-pillars 31, this also avoids the Si extensions as drain region
Layer 10 and wordline 9 (namely metal gates) short circuit.
Then, referring to attached drawing 17, the second interlayer dielectric layer 12 is formed.Second interlayer dielectric layer 12 is silica, therefore, with
Silicon oxide layer 11 is combined into an entire silicon oxide layer, and uses reference numeral 12.
Then, dielectric layer 12 between portion of second layer is removed using CMP process referring to attached drawing 18, until exposing Si extensions
The upper surface of layer 10.
Then, attached drawing 19 and 20, the first metal wiring layer of comprehensive deposition, is patterned using third layer mask plate,
To form bit line 13.The material of bit line 13 is, for example, aluminium.Before forming bit line 13, on Si epitaxial layers 10 formed drain electrode connect
It touches, such as metal silicide so that bit line 13 is electrically connected with the Si epitaxial layers 10 as drain region.
So far, according to one embodiment of present invention, the method that the present invention is described in detail.Next, according to the present invention
Other side, a kind of semiconductor devices is provided.
Referring to attached drawing 19 and 20, semiconductor devices of the invention includes 1T-DRAM cell arrays, wherein each unit is specific
Including：Semiconductor substrate 1；N+ doped layers 3 on semiconductor substrate 1 are the source region of transistor；It is adulterated positioned at N+
SiGe nano-pillars 31 on layer 3 are the channel region of transistor；Si epitaxial layers 10 on SiGe nano-pillars 31 are
The drain region of transistor；High-K gate dielectric material layer 7 and wordline 9, enclose SiGe nano-pillars 31, are the ring-shaped gate of transistor
Pole；Bit line 13 on Si epitaxial layers.Cell array in the present invention is equally distributed nano-pillar, and wordline 9 is by connecting
Metal gates composition together, since the metal gates in the present invention constitute wordline 9, the 1T-DRAM that can connect a line is mono-
Member.In addition, the bit line 13 in the present invention is etched to define by the first metal wiring layer, and connection transistor drain region, bit line
13 can connect the 1T-DRAM units of a row.
According to proposed by the present invention, channel region and drain region can also be formed by the combination of other a variety of material epitaxy, with
Achieve the purpose that promote DRAM performances.SiGe is employed herein as channel region, Si is to utilize sige material as drain region
Valence band and Si material valence band differences form the potential barrier in hole.Equally, designer can also use Si materials as channel region, wide
The SiC of forbidden band is as extension drain region.
So far, the method and device of the present invention is described in detail.In the present invention, source connector silicon substrate is utilized
Longitudinal nano-pillar transistor realize floater effect, the making of transistor is based on body silicon substrate, is avoided using expensive SOI
Substrate, while array area is reduced, it can realize high integration；Longitudinal nano-pillar transistor is used, using being epitaxially formed
Lamination be respectively channel region and drain region, big space is provided to the design in channel region and drain region, this is for 1T-DRAM performances
Promotion many embodiments are provided；Meanwhile the structure of vertical transistor is conducive to the integrated of SiGe channel regions, using extension
SiGe is as channel region, using the difference of SiGe and Si valence band, has manufactured the potential well in hole in channel region, can effectively improve 1T-
Current difference between 0 state of 1 state of reading and reading of DRAM.
The present invention is described above by reference to the embodiment of the present invention.But these embodiments are used for the purpose of saying
Bright purpose, and be not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.
The scope of the present invention is not departed from, those skilled in the art can make a variety of substitutions and modifications, these substitutions and modifications should all be fallen
Within the scope of the present invention.
Claims (8)
1. a kind of method, semi-conductor device manufacturing method, for manufacturing 1T-DRAM cell arrays, wherein include the following steps：
Step 1, source region of the N+ doped layers as transistor is formed on a semiconductor substrate；
Step 2, it is epitaxially formed SiGe layer on the semiconductor substrate；
Step 3, using first layer mask plate, the SiGe layer is etched, forms channel region of the SiGe nano-pillars as transistor；
Step 4, Si cap layers are deposited；
Step 5, the first interlayer dielectric layer is deposited；
Step 6, using second layer mask plate, first interlayer dielectric layer is performed etching；
Step 7, high-K gate dielectric material layer and metal gate material layer are sequentially depositing；
Step 8, using CMP process, part first interlayer dielectric layer, the high-K gate dielectric material layer and the gold are removed
Belong to gate material layers, until exposing the upper surface of the Si cap layers, the remaining metal gate material layer is formed as metal
Grid namely wordline；
Step 9, selective epitaxial is carried out in the upper surface of the exposed Si cap layers, forms Si epitaxial layers；
Step 10, the Si epitaxial layers described to part carry out thermal oxidation；
Step 11, the second interlayer dielectric layer is deposited；
Step 12, using CMP process, part second interlayer dielectric layer is removed, until exposing the upper of the Si epitaxial layers
Surface；
Step 13, the first metal wiring layer is deposited, is patterned using third layer mask plate, to form bit line.
2. a kind of semiconductor devices of the manufacture of the conductor device manufacturing method described in claim 1, including 1T-DRAM unit battle arrays
Row, wherein each unit includes：
Semiconductor substrate；
N+ doped layers on the semiconductor substrate are the source region of transistor；
SiGe nano-pillars on the N+ doped layers are the channel region of transistor；
Si epitaxial layers on the SiGe nano-pillars are the drain region of transistor；
High-K gate dielectric material layer and wordline enclose the SiGe nano-pillars, are the annular grid of transistor；
Bit line on the Si epitaxial layers.
3. device according to claim 2, which is characterized in that the height of the SiGe nano-pillars is 10~50nm, diameter
For 10~40nm.
4. device according to claim 2, which is characterized in that the atom percentage content of Ge exists in the SiGe nano-pillars
Between 20%~30%.
5. device according to claim 2, which is characterized in that the impurity of the N+ doped layers is arsenic, doping concentration 1*
1020cm-3。
6. device according to claim 2, which is characterized in that each unit further includes the first interlayer dielectric layer, and described the
One interlayer dielectric layer is isolated by the wordline between adjacent cells.
7. device according to claim 2, which is characterized in that the wordline connects a line 1T-DRAM units, the bit line
One row 1T-DRAM units of connection.
8. device according to claim 2, which is characterized in that the diameter of the Si epitaxial layers is less than the SiGe nano-pillars
Diameter.
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| CN106960683B (en) * | 2017-03-31 | 2020-05-05 | 深圳市华星光电技术有限公司 | Dynamic random access memory applied to liquid crystal display and access method thereof |
| US11031402B1 (en) | 2019-12-05 | 2021-06-08 | International Business Machines Corporation | Capacitorless dram cell |
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| CN102437126A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | Single-transistor DRAM (dynamic random access memory) unit based on source heterojunction and preparation method thereof |
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| US8064239B2 (en) * | 2008-11-12 | 2011-11-22 | The Board Of Trustees Of The Leland Stanford Junior University | Memory circuit with quantum well-type carrier storage |
| US8441053B2 (en) * | 2010-10-15 | 2013-05-14 | Powerchip Technology Corporation | Vertical capacitor-less DRAM cell, DRAM array and operation of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437126A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | Single-transistor DRAM (dynamic random access memory) unit based on source heterojunction and preparation method thereof |
Non-Patent Citations (2)
| Title |
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| A New Capacitorless 1T DRAM Cell: Surrounding;Hoon Jeong;《IEEE TRANSACTIONS ON NANOTECHNOLOGY》;20070531;第6卷(第3期);第352-355页 * |
| Investigation of Capacitorless Double-Gate;M. Günhan Ertosun;《IEEE TRANSACTIONS ON ELECTRON DEVICES》;20100331;第57卷(第3期);第608-612页 * |
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