CN106960683B - Dynamic random access memory applied to liquid crystal display and access method thereof - Google Patents
Dynamic random access memory applied to liquid crystal display and access method thereof Download PDFInfo
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Abstract
The invention discloses a dynamic random access memory applied to a liquid crystal display and an access method thereof. The dynamic random access memory is a thin film transistor with hysteresis effect, and the method comprises the following steps: fixing the voltage between the source electrode and the drain electrode of the thin film transistor as a first voltage; applying a voltage to be stored to the grid to enable the dynamic random access memory to be in a corresponding storage state; applying a third voltage to the gate to read a drain current flowing through the drain; and reading the storage state of the dynamic random access memory according to the drain current. Through the mode, the dynamic random access memory can realize the access function without additionally increasing a capacitor, so that the display effect of the liquid crystal display is ensured; in addition, the invention uses the prior thin film transistor to realize the dynamic random access memory, does not need additional manufacture procedure and occupies additional area, thereby reducing the production complexity of the liquid crystal display.
Description
Technical Field
The invention relates to the field of liquid crystal display, in particular to a dynamic random access memory applied to a liquid crystal display and an access method thereof.
Background
The conventional dynamic random access memory needs to use 1T1C, i.e., one transistor and one capacitor. When the conventional dram is applied to the lcd, the requirements for the RC delay and the aperture ratio are higher and higher due to the higher resolution of the lcd, and the additional capacitance introduced into the dram causes the RC delay to increase and the aperture ratio to decrease, thereby reducing the display effect of the lcd. In addition, the conventional dram requires additional processes and occupies a large area, thereby increasing the production complexity of the lcd.
Disclosure of Invention
The invention mainly solves the technical problem of providing a dynamic random access memory applied to a liquid crystal display and an access method thereof, which can realize the function of dynamic access without additionally increasing a capacitor, thereby ensuring the display effect of the liquid crystal display.
In order to solve the technical problems, the invention adopts a technical scheme that: an access method of a dynamic random access memory applied to a liquid crystal display is provided, the dynamic random access memory is a thin film transistor with hysteresis effect, the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, the method comprises the following steps: fixing the voltage between the source electrode and the drain electrode of the thin film transistor as a first voltage; applying a voltage to be stored to the gate to place the dynamic random access memory in a corresponding storage state, wherein the storage state comprises a first state and a second state; applying a third voltage to the gate to read a drain current flowing through the drain; and reading the storage state of the dynamic random access memory according to the drain current, wherein the drain current comprises a first current and a second current, and the first current is smaller than the second current.
In order to solve the technical problem, the invention adopts another technical scheme that: a dynamic random access memory applied to a liquid crystal display is provided, the dynamic random access memory is a thin film transistor with hysteresis effect, the thin film transistor comprises a grid electrode, a source electrode and a drain electrode; the source electrode and the drain electrode are fixed to form a first voltage; when the voltage to be stored of the second positive voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a first state; when the voltage to be stored with the second negative voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a second state; when the storage state of the dynamic random access memory is a first state or a second state, applying a third voltage to the grid electrode and reading the drain current flowing through the drain electrode; when the drain current is the first current, the read dynamic random access memory is defined to be in a first state; when the drain current is the second current, defining the read dynamic random access memory as a second state; wherein the first current is less than the second current.
The invention has the beneficial effects that: the dynamic random access memory applied to the liquid crystal display and the access method thereof adopt the thin film transistor with the hysteresis effect, wherein, when the voltage to be stored of a second positive voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a first state; when the voltage to be stored with the second negative voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a second state; when the storage state of the dynamic random access memory is a first state or a second state, applying a third voltage to the grid electrode and reading the drain current flowing through the drain electrode; when the drain current is the first current, the read dynamic random access memory is defined to be in a first state; when the drain current is the second current, the read dynamic random access memory is defined as the second state. Through the mode, the dynamic random access memory applied to the liquid crystal display does not need to be additionally provided with a capacitor, so that the display effect of the liquid crystal display is ensured; in addition, the invention uses the prior thin film transistor to realize the dynamic random access memory, does not need additional manufacture procedure and occupies additional area, thereby reducing the production complexity of the liquid crystal display.
Drawings
FIG. 1 is a schematic diagram of a DRAM applied in a liquid crystal display according to an embodiment of the present invention;
FIG. 2 is a graph illustrating hysteresis effects of the DRAM of FIG. 1;
FIG. 3 is a schematic diagram of a DRAM applied in an LCD according to an embodiment of the present invention;
FIG. 4 is a flow chart of an access method of a DRAM applied in a liquid crystal display according to an embodiment of the present invention;
FIG. 5 is an access timing diagram of endurance test of DRAM according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating endurance of a DRAM according to an embodiment of the present invention.
Detailed Description
Where certain terms are used throughout the description and claims to refer to particular components, those skilled in the art will appreciate that manufacturers may refer to the same components by different names. In the present specification and claims, the difference in name is not used as a means for distinguishing between components, but a difference in function of a component is used as a reference for distinguishing between components. The present invention will be described in detail below with reference to the accompanying drawings and examples.
FIG. 1 is a schematic diagram of a DRAM applied in a liquid crystal display according to an embodiment of the present invention. As shown in fig. 1, the dynamic random access memory 10 is a thin film transistor 11 with hysteresis effect, and the thin film transistor 11 includes a gate 111, a source 112 and a drain 113.
Wherein, the source electrode 112 and the drain electrode 113 are fixed to a first voltage.
When the voltage to be stored of the second positive voltage is applied to the gate 111, the storage state of the dynamic random access memory 10 is the first state; when the standby voltage of the second negative voltage is applied to the gate 111, the memory state of the dynamic random access memory 10 is the second state. Preferably, in the present embodiment, the first state is "1" in the binary number, and the second state is "0" in the binary number.
When the storage state of the dynamic random access memory 10 is the first state or the second state, a third voltage is applied to the gate 111, and the drain current flowing through the drain 113 is read.
When the drain current is the first current, the read dram 10 is defined as the first state; when the drain current is the second current, defining the read dynamic random access memory 10 as the second state; wherein the first current is less than the second current.
Preferably, in this embodiment, the first voltage is 10V, the second positive voltage is +25V, the second negative voltage is-25V, and the third voltage is-3V.
In other words, in the present embodiment, when the dram 10 performs the access operation: the voltage between the source and drain is 10V; when a second positive voltage of +25V is applied to the gate 111, which corresponds to writing "1" in the binary number into the dynamic random access memory 10, and a third voltage of-3V is applied to the gate 111 again, the drain current flowing through the drain 113 is read to be a relatively small first current, which corresponds to reading "1" in the binary number stored in the dynamic random access memory 10; when a second negative voltage of-25V is applied to the gate 111, which corresponds to writing "0" in the binary number into the dynamic random access memory 10, and a third voltage of-3V is applied to the gate 111 again, the drain current flowing through the drain 113 is read as a relatively large second current, which corresponds to reading "0" in the binary number stored in the dynamic random access memory 10.
Those skilled in the art will appreciate that the first current is required to be much less than the second current in order to better distinguish the binary numbers "1" and "0" stored in the dynamic random access memory 10. Preferably, in the embodiment, the first current is smaller than the second current by 1 to 2 orders of magnitude.
In addition, as will be understood by those skilled in the art, conventional dram devices have a capacitive structure, which may leak current, and thus require constant refreshing during use. The dynamic random access memory of the invention has no capacitor, so that the dynamic random access memory does not need to be refreshed and is more convenient to use.
Referring to fig. 2, fig. 2 is a graph illustrating the hysteresis effect of the dram shown in fig. 1. As shown in fig. 2, the horizontal axis represents the Gate Voltage (Gate Voltage) applied to the Gate electrode, and the vertical axis represents the Drain Current (Drain Current) flowing through the Drain electrode. When the curves of the gate voltage and the drain current obtained by the Forward scanning and the reverse scanning do not coincide, a hysteresis window is formed between the two curves, so that the hysteresis window realizes the memory effect and realizes the access function of the dynamic random access memory.
The principle of the hysteresis effect of the dynamic random access memory is as follows: when the gate of the thin film transistor is operated at a negative voltage, holes accumulate near the source (source) end, causing the voltage to drift to a negative bias, and when the gate of the thin film transistor is operated at a positive voltage, electrons recombine with the holes near the source end, thereby returning to the original electrical curve and thus reaching the memory window.
In an embodiment, regarding the selection of the third voltage, the third voltage is preferably a gate voltage corresponding to a point where a difference between the drain currents (i.e., a difference between the first current and the second current) is maximum in a curve formed by the forward scan and the reverse scan, i.e., -3V.
In addition, in the practical use process, the hysteresis window in the characteristic graph of the hysteresis effect becomes more obvious as the temperature becomes higher, that is, the difference value between the second current and the first current becomes larger as the temperature of the thin film transistor becomes higher. Preferably, in the present embodiment, the temperature of the thin film transistor is up to 450 kelvin.
In this embodiment, the thin film transistor is specifically an amorphous silicon thin film transistor or a metal oxide thin film transistor with a hysteresis effect.
Fig. 3 is a schematic structural diagram of a dynamic random access memory according to an embodiment of the present invention, and as shown in fig. 3, when a thin film transistor in the dynamic random access memory is an amorphous silicon thin film transistor, the amorphous silicon thin film transistor includes: a substrate 21, a gate 22 disposed on the substrate 21, a gate insulating layer 23 disposed on the substrate 21 and the gate 22, an active layer 24 disposed on the gate insulating layer 23, and a source 25 and a drain 26 disposed on the active layer 24; the active layer 24 includes an undoped amorphous silicon layer 241, and a first doped amorphous silicon layer 242 and a second doped amorphous silicon layer 243 spaced apart from the undoped amorphous silicon layer 241, and the source 25 and the drain 26 are in contact with the first doped amorphous silicon layer 242 and the second doped amorphous silicon layer 243, respectively. Preferably, the gate electrode 22, the source electrode 25 and the drain electrode 26 are of a single-layer aluminum structure, a single-layer molybdenum structure or a three-layer structure in which two layers of molybdenum sandwich one layer of aluminum. Preferably, the first and second impurity-doped amorphous silicon layers 242 and 243 are N-type impurity-doped amorphous silicon layers.
In other words, the forming process of the amorphous silicon thin film transistor is as follows: under the back channel etching structure, Ti/Al/Ti is deposited as the gate material, further a gate insulation layer is deposited, an active layer is deposited, and then Ti/Al/Ti is also deposited as the source and drain, defining the shape and etching of the source and drain.
In addition, when the thin film transistor is a metal oxide thin film transistor, the metal oxide thin film transistor includes: the semiconductor device includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the substrate and the gate electrode, an oxide semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer at an interval. Preferably, the gate, the source and the drain are in a single-layer aluminum structure, a single-layer molybdenum structure or a three-layer structure in which two layers of molybdenum sandwich one layer of aluminum. Preferably, the material of the oxide semiconductor layer is Indium Gallium Zinc Oxide (IGZO).
In other words, when the thin film transistor is a metal oxide thin film transistor, the active layer 24 shown in fig. 3 may be replaced with an oxide semiconductor layer.
Fig. 4 is a flowchart of an access method of a dynamic random access memory according to an embodiment of the present invention, the method being based on the thin film transistor shown in fig. 1. As shown in fig. 4, the method includes the steps of:
step S101: and fixing the voltage between the source electrode and the drain electrode of the thin film transistor to be a first voltage.
In step S101, the thin film transistor is an amorphous silicon thin film transistor or a metal oxide thin film transistor with a hysteresis effect. In the present embodiment, the first voltage is preferably 10V.
Step S102: a voltage to be stored is applied to the gate to place the dynamic random access memory in a corresponding storage state.
In step S102, the step of applying a voltage to be stored to the gate to place the dynamic random access memory in a corresponding storage state includes: applying the voltage to be stored of a second positive voltage to the gate to place the dynamic random access memory in a first state; or applying the voltage to be stored of a second negative voltage to the gate to place the dynamic random access memory in a second state.
That is, when the voltage to be stored is a second positive voltage, the dram is in the first state, and when the voltage to be stored is a second negative voltage, the dram is in the second state.
In this embodiment, the second positive voltage is preferably +25V and the second negative voltage is preferably-25V. In the present embodiment, the first state is "1" in the binary number, and the second state is "0" in the binary number.
Step S103: a third voltage is applied to the gate to read a drain current flowing through the drain.
In step S102, the third voltage is a gate voltage corresponding to a point where the difference between the drain currents is maximum in a curve formed by the forward scan and the reverse scan in the hysteresis effect. In this embodiment, the third voltage is preferably-3V.
Step S104: and reading the storage state of the dynamic random access memory according to the drain current.
In step S104, when the drain current is the first current, that is, when the gate voltage changes from the second positive voltage to the third voltage, the read storage state of the dynamic random access memory is the first state; when the drain current is the second current, that is, the gate voltage changes from the second negative voltage to the third voltage, the read storage state of the dynamic random access memory is the second state.
Wherein the first current is less than the second current. Preferably, the first current is 1 to 2 orders of magnitude less than the second current to better distinguish binary numbers "1" and "0" stored in the dynamic random access memory.
Referring to fig. 5 and fig. 6 together, fig. 5 is an access timing chart of the endurance test of the dynamic random access memory according to the embodiment of the invention, and fig. 6 is a schematic diagram of the endurance test of the dynamic random access memory according to the embodiment of the invention. As shown in fig. 5, the dynamic random access memory is subjected to successive write and read operations, specifically, a gate voltage of-25V is given as a write second state operation, followed by a gate voltage of-3V as a read operation, a gate voltage of +25V is given as a write first state operation, followed by a gate voltage of-3V as a read operation, … …, and the operations are cycled. As shown in fig. 6, when the number of operations (Operation number) reaches 700 times, the first current corresponding to reading the first state and the second current corresponding to reading the second state of the dynamic random access memory are both kept constant and have a difference of 1 to 2 orders (1 to 2 orders), and a hysteresis window still exists, which indicates that the dynamic random access memory is durable.
In addition, the dynamic random access Memory is a thin film transistor, in the field of liquid crystal display, the dynamic random access Memory can simultaneously have the functions of displaying pixels and memorizing, can be effectively applied to a Memory-in-Pixel display, and reduces the circuit complexity.
The invention has the beneficial effects that: the dynamic random access memory applied to the liquid crystal display and the access method thereof adopt the thin film transistor with the hysteresis effect, wherein, when the voltage to be stored of a second positive voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a first state; when the voltage to be stored with the second negative voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a second state; when the storage state of the dynamic random access memory is a first state or a second state, applying a third voltage to the grid electrode and reading the drain current flowing through the drain electrode; when the drain current is the first current, the read dynamic random access memory is defined to be in a first state; when the drain current is the second current, the read dynamic random access memory is defined as the second state. Through the mode, the dynamic random access memory does not need to be additionally provided with a capacitor, so that the display effect of the liquid crystal display is ensured; in addition, the invention uses the prior thin film transistor to realize the dynamic random access memory, does not need additional manufacture procedure and occupies additional area, thereby reducing the production complexity of the liquid crystal display.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An access method of DRAM applied in LCD is characterized in that the DRAM is a thin film transistor with hysteresis effect, the thin film transistor includes a grid, a source and a drain, the method includes:
fixing a voltage between the source electrode and the drain electrode of the thin film transistor as a first voltage;
applying a voltage to be stored of a second positive voltage or a second negative voltage to the gate to enable the dynamic random access memory to be in a corresponding storage state, wherein the storage state comprises a first state and a second state;
applying a third voltage to the gate to read a drain current flowing through the drain, wherein the third voltage is a gate voltage corresponding to a point in a curve formed by forward scanning and reverse scanning where a difference between the drain currents is maximum; when the forward scanning is performed, namely the voltage between the source electrode and the drain electrode is a first voltage, a voltage signal from a second negative voltage to a second positive voltage is applied to the grid electrode; when the reverse scanning is performed, namely the voltage between the source electrode and the drain electrode is a first voltage, applying a voltage signal from a second positive voltage to a second negative voltage to the grid electrode;
reading the storage state of the dynamic random access memory according to the drain current, wherein the drain current comprises a first current and a second current, and the first current is smaller than the second current.
2. The method of claim 1, wherein applying a voltage to be stored to the gate to place the dynamic random access memory in a corresponding storage state comprises:
applying the voltage to be stored of the second positive voltage to the gate to place the dynamic random access memory in the first state; or
Applying the voltage to the gate of the second negative voltage to place the dynamic random access memory in the second state.
3. The method of claim 2, wherein reading the memory state of the dynamic random access memory according to the drain current comprises:
when the drain current is a first current, reading the storage state of the dynamic random access memory to be the first state; and when the drain current is a second current, reading the storage state of the dynamic random access memory to be the second state.
4. The method of claim 1, wherein the first state is a "1" in a binary number and the second state is a "0" in a binary number.
5. The method of claim 1, wherein the first current is 1 to 2 orders of magnitude less than the second current.
6. The method according to claim 1, wherein a difference between the second current and the first current becomes larger as a temperature of the thin film transistor increases.
7. The method of claim 1, wherein the thin film transistor is an amorphous silicon thin film transistor or a metal oxide thin film transistor.
8. A dynamic random access memory applied to a liquid crystal display is characterized in that the dynamic random access memory is a thin film transistor with a hysteresis effect, and the thin film transistor comprises a grid electrode, a source electrode and a drain electrode;
wherein a first voltage is fixed between the source and the drain;
when a voltage to be stored of a second positive voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a first state; when a second negative voltage to-be-stored voltage is applied to the grid electrode, the storage state of the dynamic random access memory is a second state;
when the storage state of the dynamic random access memory is the first state or the second state, applying a third voltage to the gate to read a drain current flowing through the drain, wherein the third voltage is a gate voltage corresponding to a point where a difference between the drain currents is maximum in a curve formed by forward scanning and reverse scanning; when the forward scanning is performed, namely the voltage between the source electrode and the drain electrode is a first voltage, a voltage signal from a second negative voltage to a second positive voltage is applied to the grid electrode; when the reverse scanning is performed, namely the voltage between the source electrode and the drain electrode is a first voltage, applying a voltage signal from a second positive voltage to a second negative voltage to the grid electrode;
when the drain current is a first current, defining the read dynamic random access memory to be in the first state; when the drain current is a second current, defining the read dynamic random access memory to be in the second state;
wherein the first current is less than the second current.
9. The dynamic random access memory of claim 8, wherein the first state is a "1" in a binary number and the second state is a "0" in a binary number.
10. The dram of claim 8, wherein the thin film transistor is an amorphous silicon thin film transistor or a metal oxide thin film transistor.
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| CN103972174A (en) * | 2013-01-29 | 2014-08-06 | 中国科学院微电子研究所 | SiGe body region longitudinal 1T-DRAM device and manufacturing method thereof |
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| US7589995B2 (en) * | 2006-09-07 | 2009-09-15 | Micron Technology, Inc. | One-transistor memory cell with bias gate |
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| CN102668062A (en) * | 2009-10-21 | 2012-09-12 | 株式会社半导体能源研究所 | Semiconductor device |
| CN103972174A (en) * | 2013-01-29 | 2014-08-06 | 中国科学院微电子研究所 | SiGe body region longitudinal 1T-DRAM device and manufacturing method thereof |
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