CN100527442C - Double-fin type channel double-grid multifunction field effect transistor and producing method thereof - Google Patents
Double-fin type channel double-grid multifunction field effect transistor and producing method thereof Download PDFInfo
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- CN100527442C CN100527442C CNB2007101059638A CN200710105963A CN100527442C CN 100527442 C CN100527442 C CN 100527442C CN B2007101059638 A CNB2007101059638 A CN B2007101059638A CN 200710105963 A CN200710105963 A CN 200710105963A CN 100527442 C CN100527442 C CN 100527442C
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Abstract
This invention provides a double-fin channel double-grid multifunction field effect transistor and its preparation method, in which, the field effect transistor has a silicon substrate, the channel is two same fins with rectangular sections to form a double-fin channel, the outside of each is oxygen grid and front grid, the inside of which is tunnel through oxidation layer, a SiN4 trap layer, a block oxidation layer and a back grid to form a double-grid structure, two ends of the double-fin channel is connected with a common n+source and n+drain, the front and back grids are aligned covering little part of the n+source and n+drain, a thick SiO2 insulation layer is set just under the channel and the silicon substrate connected with the n+source and the n+drain to form a structure with the double-fin channel on the insulation layer.
Description
Technical field
(technical field of MetalOxide Semiconductor Field Effect Transistor-MOSFET) is specifically related to a kind of double-fin type channel double-grid multifunction field effect transistor and preparation method thereof to the invention belongs to mos field effect transistor in the very lagre scale integrated circuit (VLSIC) (ULSI).
Background technology
Along with the extensive use and the high speed development of very lagre scale integrated circuit (VLSIC), based on MOSFET, (System OnChip-SOC) technology more and more causes people's great interest to System on Chip/SoC.System on Chip/SoC is exactly that whole system is integrated on one or the few several integrated circuit (IC) chip of trying one's best, each chip by original simple function, become now can be integrated two or more function.The SOC technology can overcome the variety of issue (as the reliability of the time-delay between the chip, printed circuit board (PCB)) of the integrated appearance of plate level of multicore sheet, is improving systematic function, reduces power consumption, is being easy to have outstanding advantage aspect the assembling.
The device cell of the integrated multiple difference in functionality of development need while of SOC technology or module are on same chip, for example a kind of SOC technology that is suitable for performance application may need integrated: based on the high performance MOSFET logical device of SOI substrate and based on flash memory (the Flash Memory of body silicon substrate MOSFET structure, can be called for short flash memory) and DRAM (dynamic RAM), respectively as Fig. 1 (a) and (b) with (c).But, because the difference of these three kinds of device architectures is bigger, realize that on same chip these devices need increase more preparation technology, will cause rate of finished products variation, cost to increase.Simultaneously, chip area does not have advantage with respect to the chip area sum on each individual chips.Therefore, do not increase integration density, increased the cost of unit chip area though existing SOC technology has improved systematic function.
At this point, based on MOSFET, from device architecture and preparation method thereof, people have proposed to be suitable for the notion of the multifunction device (multi-functional device) that SOC uses, adopt the device of new structure, on same device, realize multiple function.As document 1 (C.Oh, S.Kim, N.Kim, et al., " A Novel Multi-FunctionalSilicon-On-ONO (SOONO) MOSFETs for SoC applications:Electrical Characterization forHigh Performance Transistor and Embeded Memory Applications ", in Proc.of VLSI Dig.Tech., p.16,2006) shown in, based on MOSFET, proposed to realize the multi-function field effect transistor of logical device, flash memory, three kinds of device functions of DRAM, as shown in Figure 2.Because this multi-function field effect transistor can possess logical device and two kinds of device functions of flash memory simultaneously or with no capacity MOS FET structure realization DRAM device function, therefore one times integration density nearly can be improved, the cost of unit chip area can be significantly reduced.This multifunction device has wide prospect in the SOC technology is used.
A kind of SOONO structure MOSFET multifunction device shown in the document 1 is equivalent to a kind of planar double-gated devices.Can possess following three kinds of functions.(1) function of high performance MOSFET logical device constitutes device by source, leakage, raceway groove, grid oxygen and preceding grid (FG), operating voltage 1.0V～1.2V (volt), and it is 0V that back of the body grid (BG) are used as underlayer electrode.(2) function of flash memory constitutes device by source, leakage, raceway groove, back of the body grid and back of the body grid ONO stack architectures (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer), and it is 0V that preceding grid are used as underlayer electrode; Source 0V leaks 3V, and back of the body grid 6V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of DRAM constitutes device by source, leakage, raceway groove, grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 "; Preceding grid 1V, leakage adds back bias voltage, the hole is swept leakage, storage " 0 "; When reading, leak 0.2V.This capless DRAM, than the DRAM of conventional 1T1C (field-effect transistor adds an electric capacity), simple in structure, scaled down ability is strong, compatible fully with MOSFET technology.
But, this SOONO structure MOSFET multifunction device shown in the document 1, based on planar double-gated devices, there are the following problems: (1) (is respectively 1.4nm because the back of the body grid ONO stack architecture that device architecture and preparation technology cause is too thick, 42nm, 1.4nm, gross thickness reaches about 45nm), make threshold window young (2.5V), back gate voltage during program/erase higher (reaching 6V/-4V), the program/erase time is grown (reaching 0.5ms/0.5ms), application of thin tunnel oxide (1.4nm) makes the retention performance variation, too thick silicon nitride trap layer makes the distribution influence again of iunjected charge arrive the reliability of device simultaneously; (2) preparation method of conventional relatively MOSFET need to increase by two domains: a Stripe version (removing the SiGe sacrifice layer), one be the deep trench isolation domain, be used for isolating different back of the body grid; (3) back of the body grid cover raceway groove and source, leakage fully, and the band-to-band-tunneling hot hole when wiping can be injected into the overlay area of back of the body grid and leakage, have influence on the DC characteristic and the reliability of device.(4) as the SiGe layer of sacrifice layer with as the silicon layer of raceway groove, all be epitaxially grown, the technology cost is higher.
Summary of the invention
At the problem of the SOONO structure multifunctional MOSFET of above-mentioned document 1, for the multifunction device characteristic that realizes optimizing, improve integration density, the present invention proposes innovation from the device architecture aspect, proposed a kind of double-fin type channel double-grid multifunction field effect transistor.
A kind of double-fin type channel double-grid multifunction field effect transistor, this field-effect-transistor-based be in the body silicon substrate, and raceway groove is that two identical cross sections (along the section of the vertical direction of raceway groove) are to form double-fin channel by rectangular fin type Fin; The outside of each fin channel is grid oxygen and preceding grid (polysilicon or metal material), and the inboard is tunnel oxide, the silicon nitride trap layer as charge storage layer, barrier oxide layer and back of the body grid (polysilicon or metal material), forms double-gate structure; The two ends of double-fin channel connect common n+ source and n+ leaks, preceding grid and the autoregistration of back of the body grid, very little to the covering of n+ source and n+ leakage; Under the double-fin channel and the silicon dioxide insulating layer of a bed thickness is arranged between the body silicon substrate, and the n+ source is leaked with n+ and is all linked to each other with the body silicon substrate, the formation double-fin channel be the structure of body on insulating barrier (Body-On-Insulator, BOI).
The cross section of described double-fin channel is that width W is that 30nm～60nm, height H are the rectangle (W is less than H) of 50nm～100nm.
Under the described double-fin channel and the thickness of the silicon dioxide insulating layer between the body silicon substrate be 150nm～250nm.
The thickness of described grid oxygen is 1nm～2nm.
The thickness of described tunnel oxide is that the thickness of 2nm～4nm, silicon nitride trap layer is that the thickness of 4nm～5nm, barrier oxide layer is 4nm～6nm, and the gross thickness of promptly carrying on the back grid ONO stack architecture is 10～16nm.
The junction depth of described source and leakage can be greater than the height of double-fin channel, to reduce the parasitic series resistance of source, leakage.
Another object of the present invention is to, a kind of method for preparing double-fin type channel double-grid multifunction field effect transistor is provided, may further comprise the steps:
1) on the body silicon substrate, thermal oxidation first silicon dioxide layer, deposit first silicon nitride layer, second silicon dioxide layer, second silicon nitride layer and the 3rd silicon dioxide layer four-layer structure again;
2) memory version photoetching, etching the 3rd silicon dioxide layer and second silicon nitride layer;
3) active area version photoetching, etching second silicon dioxide layer, first silicon nitride layer and first silicon dioxide layer; The silicon of etching place;
4) deposit silicon dioxide, etching form side wall; The silicon of etching place once more; Isotropic etching silicon makes that the silicon under the raceway groove is all carved empty; Remove side wall; Wet etching second silicon nitride layer;
5) deposit silicon dioxide; With second silicon nitride layer as stopping layer, the chemico-mechanical polishing planarization;
6) remove second silicon nitride layer, etching second silicon dioxide layer, first silicon nitride layer and first silicon dioxide layer; Etch silicon forms double-fin channel;
7) thermal oxidation tunnel oxide, deposit silicon nitride trap layer, deposition preventing oxide layer form back of the body grid ONO stack architecture, and deposit or sputter back of the body grid material form back of the body grid;
8) silicon dioxide of corrosion place exposes the lateral wall of double-fin channel; Grid material before the gate oxidation, deposit or sputter, grid before forming;
9) grid version photoetching, grid and the autoregistration of back of the body grid before making; Impurity injects, and forms n+ source and leakage; The annealing activator impurity.
In the described step 3), the silicon 50nm～100nm of etching place, the size autoregistration of etching has defined the height H of double-fin channel.
In the described step 4), wet etching silicon nitride 30nm～60nm has defined to the size autoregistration of lateral encroaching the width W of double-fin channel.
Wherein, some key structure parameters of the double-fin type channel double-grid multifunction field effect transistor of BOI structure of the present invention are as the long L of thickness, grid of the silicon dioxide insulating layer of the wide W of double-fin channel and high H, BOI structure
G, back of the body grid ONO stack architecture material, raceway groove and the source of each layer thickness, gate oxide thickness, back of the body grid and preceding the grid doping content and the distribution of leaking, can make adjustment according to the design needs.Preparation method of the present invention, adopt the technology of conventional MOSFET preparation, as oxidation, deposit, etching and corrosion etc., by new technology integrated (Process Integration), can autoregistration on the body silicon substrate realize the double-fin type channel double-grid multifunction field effect transistor of BOI structure (body is on insulating barrier).This preparation method and existing conventional MOSFET technology are compatible fully, do not need expensive technologies such as extension, when realizing the multifunction device characteristic of optimizing, can reduce the prepared cost.
Double-fin type channel double-grid multifunction field effect transistor of the present invention has following three kinds of functions equally.(1) function of high performance MOSFET logical device constitutes device by source, leakage, double-fin channel, outer grid oxygen and the preceding grid of surveying of double-fin channel, operating voltage 1.0V～1.2V, and back of the body grid are 0V.(2) function of flash memory, back of the body grid and back of the body grid ONO stack architectures (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer) by source, leakage, double-fin channel, double-fin channel inboard constitute device, preceding grid are 0V: source 0V, leak 3V, back of the body grid 4V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of capless DRAM constitutes device by source, leakage, double-fin channel, grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 ": preceding grid 1V, leak and add back bias voltage, the hole is swept leakage, storage " 0 ": when reading, leak 0.2V.
Multi-functional MOSFET with respect to document 1 based on planar double-gated structure, the technique effect of the double-fin type channel double-grid multifunction field effect transistor that the present invention proposes is: (1) double-fin channel, can increase as the ON state drive current of logical device with as the electric current that reads of flush memory device, optimize DC characteristic; (2) each layer thickness of back of the body grid ONO stack architecture can be according to the definition of design needs; (tunnel oxide of 2nm～4nm) is to improve the retention performance of storage data to adopt suitable thickness; Adopt suitable thickness (silicon nitride trap layer of 4nm～5nm), suppress stored charge in the distribution again of silicon nitride layer, improve reliability; (3) gross thickness of back of the body grid ONO stack architecture is not subjected to process technology limit, can reach 10nm～16nm (and about 45nm of thickness of the ONO stack architecture in the document 1), and the back of the body grid voltage when making program/erase reduces, improves simultaneously program/erase speed; (4) back of the body grid and preceding grid autoregistration all are by the definition of grid version, and be very little for the covering of source and leakage, can improve the DC characteristic and the reliability of multifunction device; (5) preparation method of conventional relatively MOSFET, only needing increases by a block storage version, does not also need epitaxial growth technology, can reduce the technology cost; (6) based on the body of the body silicon substrate structure of (BOI) on insulating barrier, can adopt bigger source and drain junction dark, to reduce the parasitic series resistance that leak in the source, the BOI structure also can reduce the grid parasitic capacitance simultaneously; (7) double-fin channel is a stereochemical structure simultaneously, effective channel width that can device under the condition of same domain improves at least one times, promptly in other words, under the condition of effective channel width, can thereby can improve integration density so that chip area reduces closely 50%.
Therefore, double-fin type channel double-grid multifunction field effect transistor proposed by the invention in high reliability and highdensity high-performance SOC application, has clear superiority and application prospects.
Description of drawings
Fig. 1 is for needing the generalized section of three kinds of integrated devices in the high-performance SOC application, wherein Fig. 1 (a) is the high performance MOSFET logical device based on the SOI substrate, wherein Fig. 1 (b) is flash (the Flash Memory based on body silicon substrate MOSFET structure, can be called for short flash memory), wherein Fig. 1 (c) is the DRAM (dynamic RAM) of 1T1C (field-effect transistor adds an electric capacity).
Among Fig. 1 (a)-(c), identical label is represented identical parts:
The oxygen buried layer of back side silicon 102-SOI substrate of 101-SOI substrate
103-polysilicon gate, 104-grid oxygen
105-raceway groove (SOI top layer silicon), 106-n+ source, 107-n+ leaks
The raceway groove of 108-body silicon substrate, 109-flash memory
110-barrier oxide layer, 111-silicon nitride trap layer, 112-tunnel oxide
The electric capacity of 113-raceway groove (body silicon substrate), 114-DRAM
Fig. 2 is the domain and the structural representation of the SOONO structure multifunctional field-effect transistor of document 1: wherein, Fig. 2 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is Stripe version (removing the SiGe sacrifice layer), M3 is the grid version, and M4 is the domain of deep trench isolation; Fig. 2 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device; Fig. 2 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device.
Fig. 2 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide of the place that 201-body silicon substrate (p-doping), 202-STI isolates
203-back of the body grid (n+ silicon), 204-barrier oxide layer, 205-silicon nitride trap layer, 206-tunnel oxide
207-polysilicon gate, 208-grid oxygen
209-raceway groove, 210-n+ source 211-n+ leaks
Fig. 3 is the domain and the structural representation of double-fin type channel double-grid multifunction field effect transistor provided by the present invention: wherein, Fig. 3 (a) is the domain schematic diagram of this device, and M1 is the memory version, and M2 is the active area version, M3 is the grid version, and dark part is a double-fin channel; Fig. 3 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device, can see that raceway groove is the structure of two fin types, the outer survey of double-fin channel is grid oxygen and preceding grid, inboard for carrying on the back grid ONO stack architecture and back of the body grid, and the silicon dioxide insulating layer of a bed thickness is arranged under the while double-fin channel; Fig. 3 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device, can see that the position of raceway groove is the BOI structure, and the source links to each other with the body silicon substrate still with leakage.
Fig. 3 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide of the place that 301-body silicon substrate (p-doping), 302-STI isolates
Under 303-double-fin channel and the silicon dioxide insulating layer between the body silicon substrate
304-double-fin channel
305-preceding grid 306-grid oxygen
307-back of the body grid, 308-tunnel oxide, 309-silicon nitride trap layer, 310-barrier oxide layer
The hard mask 312-n+ source 313-n+ of 311-silicon dioxide leaks
Fig. 4 (a)-(j) be one embodiment of the invention based on body preparation method's of the double-fin type channel double-grid multifunction field effect transistor of (BOI structure) on insulating barrier of body silicon substrate the technological process and the schematic diagram of each step institute counter structure thereof.
Among Fig. 4 (a)-(j), identical label is represented identical parts:
401-body silicon substrate (p-doping) 402-do ground floor SiO of hard mask
2
403-make the ground floor Si of hard mask
3N
4Layer 404-make the second layer SiO of hard mask
2Layer
406-make the second layer Si of hard mask
3N
4Layer 406-make the 3rd layer of SiO of hard mask
2Layer
Silicon under the height H 408-raceway groove of 407-double-fin channel is carved empty part
The silicon dioxide of the place that the width W 410-STI of 409-double-fin channel isolates
Under 411-double-fin channel and the silicon dioxide insulating layer between the body silicon substrate
412-double-fin channel
413-tunnel oxide, 414-silicon nitride trap layer, 415-barrier oxide layer 416-back of the body grid
417-grid oxygen 418-preceding grid
419-n+ source, 420-n+ leaks
Embodiment
Describe double-fin type channel double-grid multifunction field effect transistor provided by the present invention and preparation method thereof in detail below in conjunction with accompanying drawing, but be not construed as limiting the invention.
Shown in Fig. 3 (a)-(c), be the double-fin type channel double-grid multifunction field effect transistor of present embodiment.This device is based on the body silicon substrate.Be depicted as the domain of this device as Fig. 3 (a), M1 memory version, M2 active area version, M3 grid version, dark position is a double-fin channel.As Fig. 3 (b) with (c) be respectively the vertical direction along raceway groove (A1A2 direction) of this device and along the cross-section structure of channel direction (B1B2 direction).From the cross-section structure along the vertical direction of raceway groove, this field-effect-transistor-based is in body silicon substrate 301, and raceway groove is that two identical cross sections are rectangular fin type Fin, and its width W is that 40nm, height H are 80nm, forms double-fin channel 304; The outside of each fin channel is the grid oxygen 306 of 1.5nm and the preceding grid 305 of polysilicon, and the inboard is tunnel oxide 308, the silicon nitride trap layer 309 as 4nm, the barrier oxide layer 310 of 5nm and the back of the body grid 307 of polysilicon of 3nm, forms double-gate structure; The two ends of double-fin channel 304 connect common n+ source 312 and n+ leaks 313; Preceding grid 305 and 307 autoregistrations of back of the body grid, and very little to the covering of n+ source 312 and n+ leakage 313; Under the double-fin channel 304 and the silicon dioxide insulating layer 303 of a bed thickness 200nm arranged between the body silicon substrate, and the n+ source 312 of junction depth 100nm all links to each other with body silicon substrate 301 with n+ leakage 313, form double-fin channel 304 and be the structure of body on insulating barrier (Body-On-Insulator, BOI).
Double-fin type channel double-grid multifunction field effect transistor of the present invention has following three kinds of functions equally.(1) function of high performance MOSFET logical device constitutes device by source, leakage, double-fin channel, outer grid oxygen and the preceding grid of surveying of double-fin channel, operating voltage 1.2V, and back of the body grid are 0V.(2) function of flash memory, by the back of the body grid and back of the body grid ONO stack architectures (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer) the formation device of source, leakage, double-fin channel, double-fin channel inboard, preceding grid are 0V; Source 0V leaks 3V, and back of the body grid 4V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of capless DRAM constitutes device by source, leakage, double-fin channel, grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 "; Preceding grid 1V, leakage adds back bias voltage, the hole is swept leakage, storage " 0 "; When reading, leak 0.2V.
Double-fin type channel double-grid multifunction field effect transistor proposed by the invention in high reliability and highdensity high-performance SOC application, has clear superiority and application prospects.
The present invention prepares the method for double-fin type channel double-grid multifunction field effect transistor, comprises the steps:
Step 1: on the body silicon substrate, thermal oxidation silicon dioxide (SiO
2) 5nm～10nm, the silicon nitride (Si of the following four-layer structure of deposit: 10nm～20nm again
3N
4), the SiO of 20～40nm
2, the Si of 80nm～150nm
3N
4And the SiO of 50nm～100nm
2
The photoetching of step 2:M1 memory version, etching SiO
2And Si
3N
4
The photoetching of step 3:M2 active area version, etching SiO
2/ Si
3N
4/ SiO
2Silicon 50nm～the 100nm of etching place, the size autoregistration of etching has defined the height H of double-fin channel.
Step 4: deposit SiO
2, etching forms side wall; The silicon of etching place once more; Isotropic etching silicon makes that the silicon under the raceway groove is all carved empty; Remove side wall; Wet etching Si
3N
430nm～60nm (wet etching is isotropic) has defined to the size autoregistration of lateral encroaching the width W of double-fin channel.
Step 5: deposit SiO
2600nm～800nm; Chemico-mechanical polishing (CMP) planarization.
Step 6: remove Si
3N
4, etching SiO
2, Si
3N
4And SiO
2Etch silicon forms double-fin channel again.
Step 7: the silicon nitride trap layer 4nm～5nm of thermal oxidation tunnel oxide 2nm～4nm, deposit charge storage layer, high-temperature deposition barrier oxide layer 4nm～6nm form back of the body grid ONO stack architecture.Deposit polysilicon (and mix, activate) or splash-proofing sputtering metal are as back of the body grid material, and cmp planarizationization forms back of the body grid.
Step 8: corrode the silicon dioxide of place, expose the lateral wall of double-fin channel; Gate oxidation 1nm～2nm; Deposit polysilicon (and mix, activate) or splash-proofing sputtering metal are as preceding grid material, and cmp planarizationization forms preceding grid.
The photoetching of step 9:M3 grid version, etch polysilicon or metal form self aligned preceding grid and back of the body grid; Arsenic injects, and forms n+ source and leakage; Remove Si
3N
4The annealing activator impurity.
Be illustrated in figure 4 as the preparation method of a kind of double-fin type channel double-grid multifunction field effect transistor proposed by the invention.Each device architecture shown in Fig. 4 (a)-(j) is corresponding with each step among this preparation method.
Below in conjunction with each accompanying drawing this preparation method is elaborated:
Step 1: on the body silicon substrate, thermal oxidation silicon dioxide (SiO
2) 5nm, the silicon nitride (Si of the following four-layer structure of deposit: 15nm again
3N
4), the SiO of 30nm
2, the Si of 150nm
3N
4SiO with 80nm
2Shown in Fig. 4 (a) (along the A1A2 direction).
The photoetching of step 2:M1 memory version, etching SiO
2And Si
3N
4, shown in Fig. 4 (b) (along the B1B2 direction).
The photoetching of step 3:M2 active area version, etching SiO
2/ Si
3N
4/ SiO
2The silicon 80nm of etching place, the size autoregistration of etching has defined the height H of double-fin channel, shown in Fig. 4 (c) (along the A1A2 direction).Fig. 4 (d) is the cross-sectional view of B1B2 direction.
Step 4: deposit SiO
2, etching forms side wall: the silicon of etching place once more; Isotropic etching silicon makes that the silicon under the raceway groove is all carved empty; Remove side wall: wet etching Si
3N
440nm has defined to the size autoregistration of lateral encroaching the width W of double-fin channel, shown in Fig. 4 (e).
Step 5: deposit SiO
2800nm; With Si
3N
4As stopping layer, chemico-mechanical polishing (CMP) planarization is shown in Fig. 4 (f) (along the B1B2 direction).
Step 6: remove Si
3N
4, etching SiO
2, Si
3N
4And SiO
2Etch silicon forms double-fin channel, shown in Fig. 4 (g) again.
Step 7: the silicon nitride trap layer 4nm of thermal oxidation tunnel oxide 3nm, deposit charge storage layer, high-temperature deposition barrier oxide layer 5nm form back of the body grid ONO stack architecture.Deposit polysilicon (and mix, activate) is as back of the body grid material, and cmp planarizationization forms back of the body grid.Shown in Fig. 4 (h).
Step 8: corrode the silicon dioxide of place, expose the lateral wall of double-fin channel; Gate oxidation 1.5nm; Deposit polysilicon (and mix, activate) or splash-proofing sputtering metal are as preceding grid material, and cmp planarizationization forms preceding grid.Shown in Fig. 4 (i).
The photoetching of step 9:M3 grid version, etch polysilicon forms self aligned preceding grid and back of the body grid; Arsenic injects, and forms n+ source and leakage; Remove Si
3N
4The annealing activator impurity.Shown in Fig. 4 (j) (B1B2 direction).
Step 10: further carry out conventional subsequent technique, deposit hypoxemia layer, the etching fairlead, depositing metal, photoetching, etching form metal wire, alloy, passivation.
Obtain the body that can be used to test double-fin type channel double-grid multifunction field effect transistor at last, the high 80nm of wide 40nm of the cross-section structure of double-fin channel in insulating barrier (BOI structure).
More than by specific embodiment double-fin type channel double-grid multifunction field effect transistor provided by the present invention and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to device architecture of the present invention; Its preparation method also is not limited to disclosed content among the embodiment.
Claims (3)
1, a kind of method for preparing double-fin type channel double-grid multifunction field effect transistor is characterized in that, may further comprise the steps:
1) on the body silicon substrate, thermal oxidation first silicon dioxide layer, deposit first silicon nitride layer, second silicon dioxide layer, second silicon nitride layer and the 3rd silicon dioxide layer four-layer structure again;
2) memory version photoetching, etching the 3rd silicon dioxide layer and second silicon nitride layer;
3) active area version photoetching, etching second silicon dioxide layer, first silicon nitride layer and first silicon dioxide layer; The silicon of etching place;
4) deposit silicon dioxide, etching form side wall; The silicon of etching place once more; Isotropic etching silicon makes that the silicon under the raceway groove is all carved empty; Remove side wall; Wet etching second silicon nitride layer;
5) deposit silicon dioxide; With second silicon nitride layer as stopping layer, the chemico-mechanical polishing planarization;
6) remove second silicon nitride layer, etching second silicon dioxide layer, first silicon nitride layer and first silicon dioxide layer; Etch silicon forms double-fin channel;
7) thermal oxidation tunnel oxide, deposit silicon nitride trap layer, deposition preventing oxide layer form back of the body grid ONO stack architecture, and deposit or sputter back of the body grid material form back of the body grid;
8) silicon dioxide of corrosion place exposes the lateral wall of double-fin channel; Grid material before the gate oxidation, deposit or sputter, grid before forming;
9) grid version photoetching, grid and the autoregistration of back of the body grid before making; Impurity injects, and forms n+ source and leakage; The annealing activator impurity.
2, preparation method as claimed in claim 1 is characterized in that, in the described step 3), and the silicon 50nm～100nm of etching place.
3, preparation method as claimed in claim 1 or 2 is characterized in that, in the described step 4), and wet etching silicon nitride 30nm～60nm.
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| CN100527442C true CN100527442C (en) | 2009-08-12 |
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