CN106158974A - A kind of fin formula field effect transistor of Ω type top gate structure and preparation method thereof - Google Patents
A kind of fin formula field effect transistor of Ω type top gate structure and preparation method thereof Download PDFInfo
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- CN106158974A CN106158974A CN201610756154.2A CN201610756154A CN106158974A CN 106158974 A CN106158974 A CN 106158974A CN 201610756154 A CN201610756154 A CN 201610756154A CN 106158974 A CN106158974 A CN 106158974A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 24
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 238000009616 inductively coupled plasma Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 2
- 238000000671 immersion lithography Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000003786 synthesis reaction Methods 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 description 8
- 238000002513 implantation Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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Abstract
The present invention provides fin formula field effect transistor of a kind of Ω type top gate structure and preparation method thereof, belongs to super large-scale integration manufacturing technology field.Rectangle top-gated is changed into Ω type top-gated by the present invention, owing to the grid-control ability of Ω type grid structure is close to enclosing structure, therefore the grid-control ability at Ω type top-gated FinFET upper for Fin 1/3 is necessarily greater than rectangular top gate FinFET, and this makes the Ω type top-gated FinFET Leakage Current can be less compared with traditional F inFET；And the channels cross-section at the Fin upper 1/3 of Ω type top-gated FinFET amasss and does not have reduction.The present invention, compared with traditional fin FET, can obtain higher ON state current.And the present invention is with traditional integrated circuit manufacturing technology compatibility mutually, technique is simple, cost price is little.
Description
Technical field
The invention belongs to super large-scale integration manufacturing technology field, relate to a kind of Ω type top gate structure fin field effect
Transistor and preparation method thereof.
Background technology
After semiconductor device enters 22nm technology generation, fin formula field effect transistor (FinFET) is short with its outstanding suppression
Ditch effect capability, high density of integration, the advantage such as compatible with traditional cmos process, become the main flow of semiconductor device.Preferably
The Fin structure of FinFET should be rectangle or the square of standard, yet with reliability hidden danger and the technique of sharp corner
The restriction of condition, the Fin of actual FinFET will not be preferable shape.If Intel is at 22nm technology node, have employed one
Up-small and down-big class triangle Fin, and when issuing the FinFET of 14nm technology node of future generation, it is used as the Fin knot of raceway groove
Structure uses the approximate rectangular shape of the round and smooth process of a kind of wedge angle.For triangle Fin, owing to top Fin is relatively thin, its tool
Having less equivalent Fin thickness, grid-control ability is relatively strong, thus has less leakage current, but it lacks top-gated and channels cross-section
Long-pending little, drive electric current the least；Rectangle Fin is then contrary, and equivalence Fin thickness is relatively large, and grid-control ability is weak compared with triangle Fin, lets out
Leakage current is big, but owing to rectangle Fin exists top-gated, and top-gated can contribute significant component of driving electric current, and square for device
The channels cross-section of shape Fin is long-pending the biggest, therefore drives electric current can be far above triangle Fin.
Therefore, on the basis of the FinFET of Intel 14nm, need badly and Fin pattern is optimized research, to obtain low letting out
Keep driving the inconspicuous degeneration of electric current while dew electric current.
Summary of the invention
For problem above, the invention provides the preparation side of the fin formula field effect transistor of a kind of Ω type top gate structure
Method, to improve existing known technology.Traditional rectangular FinFET drives the 2/3 of electric current all to concentrate at upper the 1/3 of Fin, if
The rectangle top-gated at originally upper 1/3 can be changed into Ω type top-gated, owing to the grid-control ability of Ω type grid structure is close to enclosing structure, because of
Grid-control ability at this Ω type top-gated FinFET upper for Fin 1/3 is necessarily greater than rectangular top gate FinFET (the grid-control energy of three grid
Power), this makes the Ω type top-gated FinFET Leakage Current can be less compared with traditional F inFET.On the other hand, Ω type top-gated FinFET
Channels cross-section at Fin upper 1/3 is long-pending reduction, therefore, can't bring the serious degradation of ON state current.
It is an object of the present invention to provide the preparation method of the fin formula field effect transistor of a kind of Ω type top gate structure.
The preparation method of the fin formula field effect transistor of the Ω type top gate structure of the present invention, comprises the following steps:
A., semi-conductive substrate is provided；
B. forming the mask pattern of channel region, mask live width is for defining the live width at Ω type Fin top；
B1. one layer of dielectric material of deposit is as mask layer 1；
B2. by the line thickness at photoetching technique definition Ω type Fin top；
B3. utilize photoresist for sheltering, anisotropic etching mask layer 1, formed rectangle Fin mask, rectangle Fin mask
Line
Width is the line thickness at Ω type Fin top；
B4. remove photoresist；
C. source region, drain region, preliminary Fin channel region and device isolation are formed；
C1. one layer of dielectric material of deposit is covered by mask layer 2 as mask layer 2, mask layer 1, carries out smooth to mask layer 2
Change；
C2. by photoetching technique definition source region and drain region；
C3. anisotropic etching mask layer 2 and backing material, the backing material thickness etched away is Ω type Fin top
Height
Degree, now due to the masking action of photoresist, mask layer 2 and backing material below will not be etched, and by
In covering
The masking action of film layer 1, backing material below also will not be etched；
C4. remove photoresist；
C5. one layer of dielectric material identical with mask layer 1 of deposit time quarter, side wall mask is formed；
C6. anisotropic etching backing material, the backing material thickness etched away is the height below Ω type Fin, this
Shi You
In mask layer 2 and the masking action of side wall mask, backing material below will not be etched, and forms source region, leakage
District,
And due to mask layer 1 and the masking action of side wall mask, backing material below also will not be etched, at the beginning of formation
Step
Fin channel region；
C7. the isolation between device is formed；
D. the Fin channel region of Ω type is formed；
D1. thermal oxidation technology is used to cut down preliminary Fin channel region, owing to having side wall mask and the protection of mask layer 1, just
The top of step Fin channel region can't be oxidized, and originally preliminary Fin channel region below side wall mask and mask layer 1 can quilt
Oxidation is cut down and is formed the Fin more narrower than top, so far defines complete Ω type Fin channel region, and the time of oxidation determines
Ω type Fin channel region is gone to the bottom live width；
D2. mask layer 2 is removed；
E. source and drain is injected and prepares gate electrode；
E1. by ion implantation technique, source and drain is carried out heavy doping, and activate annealing；
E2. remove mask layer 1, side wall mask and oxidation and cut down the silicon oxide formed；
E3. one layer of gate electrode layer is formed；
E4. by the figure of photoetching technique definition gate electrode；
E5. with photoresist for sheltering, anisotropic etching gate electrode layer, the grid line bar and the grid that are formed across channel region are drawn
District, grid line bar covers at the top of Ω type Fin channel region and sidewall；
E6. remove photoresist；
F. the metal contact of each end is formed；
F1. inter-level dielectric is deposited；
F2. planarization is realized by chemically mechanical polishing；
F3. the contact hole respectively held by photoetching technique definition source, leakage, grid；
F4. anisotropic etching inter-level dielectric, exposes grid draw-out area and source, the upper surface in drain region；
F5. remove photoresist；
F6. filler metal Metal 0 in each contact hole；
F7. by metal Metal 0 is carried out chemical-mechanical planarization, it is achieved the conductive layers apart between device, reach
The effect of device isolation；
It is follow-up that to complete device by published backend process integrated.
Further, Semiconductor substrate described in A, including body silicon substrate, SOI substrate, body germanium substrate, GOI substrate etc.；
Further, device isolation described in C, for body substrate (body silicon, body germanium etc.), can use trap isolation add shallow slot every
From (Shallow Trench Isolation, STI)；For substrates such as SOI, GOI, can only use shallow-trench isolation or island isolation；
Further, it is lithographically beamwriter lithography or 193nm liquid immersion lithography etc. described in B, E and can form nanoscale wire
The advanced photolithography techniques of bar；
Further, (Atomic Layer Deposition, atomic layer forms sediment to deposit optional ALD described in step B, C, F
Long-pending), LPCVD (Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor phase deposition), PECVD
(Plasma Enhanced Chemical Vapor Deposition, plasma enhanced CVD), ICPECVD
(Inductively Coupled Plasma Enhance Chemical Vapor Deposition, inductively coupled plasma
Body strengthens chemical vapor deposition) or sputtering etc..
Further, the dielectric material of the mask layer 2 described in C, it is desirable to different from mask layer 1, and it is to mask layer 1
Anisotropic corrosion rate is more than 5:1, it is ensured that the when that in C3, anisotropic etching forming preliminary Fin channel region, do not damage
The mask layer 1 at preliminary Fin channel region top；
Further, the dielectric material of the mask layer 1 described in B, it is desirable to identical with side wall mask material in C, and with lining
Bottom material is different；
Further, using thermal oxidation process in D can be dry-oxygen oxidation, wet-oxygen oxidation, Oxidation Process By Hydrogen Oxygen Synthesis etc..
Further, in E, annealing way uses rapid thermal annealing (Rapid Thermal Annealing), spike annealing
In (Spike Annealing), annealing of glittering (Flash Annealing) and laser annealing (Laser Annealing) one
Kind.
Further, the gate electrode layer formed described in E, when substrate is silicon-based substrate, can be gate oxide collocation
Polysilicon gate forms gate electrode layer, now uses dry-oxygen oxidation to prepare gate oxide, uses LPCVD to prepare polysilicon gate；Also may be used
To be that high-K gate dielectric collocation metal gate forms gate electrode layer, now use ALD to prepare high-K gate dielectric, use PVD to prepare metal
Grid；When substrate is germanio substrate, gate electrode layer can only be formed with high-K gate dielectric collocation metal gate, now use ALD to prepare high K
Gate medium, uses PVD to prepare metal gate；
Further, in B, C, E and F, anisotropic etching uses such as reactive ion etching (Reactive Ion
Etching, RIE) or inductively coupled plasma (Inductively Coupled Plasma, ICP) etc..
Further, as the filler metal Metal 0 of conductive layer described in F, it is desirable to possess low resistivity and lead to
Hole filling capacity, optional W, Cu, Al, Ti, Pt and composition metal lamination thereof.
Further, in F, filler metal employing is evaporated, sputters, is electroplated and chemical vapor deposition (Chemical Vapor
Deposition, CVD) in one.
A kind of Ω type top gate structure fin formula field effect transistor of offer is provided.
The Ω type top gate structure fin formula field effect transistor of the present invention includes: Semiconductor substrate, device isolation, Ω type Fin
Channel region, source region, drain region, gate electrode layer, inter-level dielectric, contact hole, Metal 0；Wherein, source is formed on a semiconductor substrate
District, drain region and connect the two Ω type Fin channel region and device isolation in addition；On the part surface of device isolation
Forming gate electrode layer, gate electrode layer includes grid line bar and grid draw-out area, two sides of grid line bar covering part Ω type Fin channel region
Wall and upper surface, grid draw-out area connects grid line bar；Inter-level dielectric cover source region, drain region, Ω type Fin channel region, gate electrode layer and
In addition device isolation；In inter-level dielectric, form contact hole, expose the upper table of fractional source regions, drain region and grid draw-out area
Face；Filler metal Metal 0 in the contact hole.
Advantages of the present invention and good effect are as follows:
1) the grid-control ability of Ω type grid structure that the present invention proposes is close to enclosing structure, therefore Ω type top-gated FinFET for
Grid-control ability at Fin upper 1/3 is necessarily greater than traditional rectangular top gate FinFET (the grid-control abilities of three grid), and this makes Ω type top
Gate FinFET Leakage Current can be less compared with traditional F inFET；
2) channels cross-section at the Fin of Ω type top-gated FinFET upper 1/3 is long-pending does not reduce, and therefore, can't bring ON state
The serious degradation of electric current；
3) by controlling the etching time of HNA corrosive liquid, the Fin width below Ω type Fin channel region can be controlled, when Ω type
Fin width below Fin channel region is more hour, although slightly have the reduction of ON state current, but the short-channel effect of device controls
Ability is the best, and threshold voltage is the biggest, is more suitable as low energy-consumption electronic device and applies；
4) the device source drain region that prepared by the present invention is the active island of monocrystalline, has less source-drain series resistance, with traditional
The fin FET using lifting source drain structure is compared, it is not necessary to epitaxy technique is prepared lifting source and drain and can be obtained higher
ON state current；
5) complete and mutually compatible with traditional integrated circuit manufacturing technology, technique is simple, and cost price is little.
Accompanying drawing explanation
Fig. 1-13 is the showing of each joint technique preparing N-type Ω type top gate structure fin formula field effect transistor in SOI substrate
It is intended to.In each figure, (a) is top view, and (b) is the profile in (a) along A-A ', and (c) is the profile in (a) along B-B '.
Wherein:
Fig. 1 deposits mask layer 1 on soi substrates；
Fig. 2 forms the figure of mask layer 1, as the mask of Ω type Fin；
Fig. 3 deposits mask layer 2, planarization；
Fig. 4 lithographic definition source-drain area, anisotropic etching mask layer 2 and certain thickness monocrystal silicon；
Fig. 5 deposits silicon dioxide and returns quarter, forms side wall mask；
Fig. 6 anisotropic etching monocrystal silicon, exposes the upper surface of oxygen buried layer；
Fig. 7 dry-oxygen oxidation cuts down preliminary Fin channel region, forms the Fin channel region of Ω type；
Fig. 8 removes mask layer 2, and source and drain is injected, and activates；
Fig. 9 removes mask layer 1, side wall mask and oxidation and cuts down the silicon oxide formed, and obtains source and drain and the connection source of device
The Fin raceway groove of the Ω type of leakage；
Figure 10 dry-oxygen oxidation forms gate oxide；
Figure 11 depositing polysilicon, ion implanting regulation polysilicon work function, photoetching also etches formation polysilicon gate；
Figure 12 deposits silicon dioxide as inter-level dielectric, planarization；
Figure 13 photoetching also etches each termination contact hole of formation, filler metal tungsten, planarization；
Figure 14 is the legend of Fig. 1～Figure 13.
Detailed description of the invention
The present invention is described in detail with instantiation below in conjunction with the accompanying drawings.
According to the following step can realize in SOI substrate prepare N-type Ω type top gate structure fin formula field effect transistor:
1) will utilize HNA solution that top silicon surface is thinned to 250nm, LPCVD in p-type (100) SOI substrate
SiO2100nm is as mask layer 1, as shown in Figure 1；
2) long 100nm, wide 50nm channel region mask pattern, the i.e. lines at Ω type Fin top are defined by beamwriter lithography
Width is 50nm, utilize photoresist for sheltering, ICP etching mask layer 1, formed rectangle Fin mask, the live width of rectangle Fin mask
50nm is the line thickness at Ω type Fin top, removes photoresist, as shown in Figure 2；
3) LPCVD 300nm silicon nitride is covered by mask layer 2 as mask layer 2, mask layer 1, carries out smooth to mask layer 2
Change, as shown in Figure 3；
4) by photoetching technique definition source region and drain region, ICP etching mask layer 2, ICP etches monocrystal silicon 80nm, etches away
Monocrystal silicon 80nm be the height at Ω type Fin top, now due to the masking action of photoresist, mask layer 2 He below
Monocrystal silicon will not be etched, and due to the masking action of mask layer 1, monocrystal silicon below also will not be etched, and removes photoresist, such as figure
Shown in 4；
5) LPCVD 100nm silicon nitride time quarter, side wall mask is formed, as shown in Figure 5；
6) ICP etches monocrystal silicon 170nm, exposes the upper surface of oxygen buried layer, and the monocrystal silicon 170nm etched away is Ω type
Height below Fin, now due to mask layer 2 and the masking action of side wall mask, monocrystal silicon below will not be etched, shape
Become source region, drain region, and due to mask layer 1 and the masking action of side wall mask, monocrystal silicon below also will not be etched, formed
Preliminary Fin channel region, between device due to bury the existence of oxide layer realize island isolation, as shown in Figure 6；
7) live width is to 20nm, owing to having side wall mask and mask to use dry-oxygen oxidation to cut down below preliminary Fin channel region
The protection of layer 1, the top of preliminary Fin channel region can't be oxidized, and originally preliminary below side wall mask and mask layer 1
Fin channel region can oxidized reduction and form the Fin more narrower than top, so far define the Ω type Fin channel region of monocrystal silicon, as
Shown in Fig. 7；
8) utilizing concentrated phosphoric acid to remove silicon nitride mask layer 2, corrosion temperature is 170 DEG C, As+Inject and source and drain is carried out weight
Doping, injects in three times, and Implantation Energy is respectively 30KeV, 45KeV, 65KeV, implantation dosage 5E15cm-2, and annealed by RTA
1000 DEG C, 10s, activator impurity makes source and drain impurity diffuse into source drain extension district, as shown in Figure 8 simultaneously；
9) HF:H is utilized2O=1:40 solution large area is removed mask layer 1, side wall mask and oxidation and is cut down the oxygen formed
SiClx, rinsing time 200s, exposes source region, drain region and connects both Ω type Fin channel regions, as shown in Figure 9；
10) dry-oxygen oxidation forms gate oxide 2nm, as shown in Figure 10；
11) LPCVD 250nm polysilicon, As+Inject regulation polysilicon work function, Implantation Energy 50KeV, implantation dosage
1E15cm-2, define grid line bar, with photoresist for sheltering, ICP etches polycrystalline silicon 250nm by beamwriter lithography, remove photoresist, formed
Striding across grid line bar and the grid draw-out area of channel region, grid line thickness is a length of 22nm of grid of 22nm, i.e. device, as shown in figure 11；
12) 400nm SiO is deposited by PECVD2As inter-level dielectric, and realize planarization by chemically mechanical polishing,
As shown in figure 12；
13) form device gate, source, the contact hole of each end of leakage by photoetching, ICP etching, remove photoresist；
14) sputtering 500nm tungsten, device gate, source, the contact hole of each end of leakage are filled by tungsten；
15) by tungsten is chemically-mechanicapolish polished, it is achieved the conductive layers apart between device, device isolation is reached
Effect, as shown in figure 13；
It is 16) follow-up that to complete device by published backend process integrated.
The embodiment of the present invention is not limited to the present invention.Any those of ordinary skill in the art, without departing from this
Under bright technical scheme ambit, technical solution of the present invention is made many by the method and the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from technical solution of the present invention
Content, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, the most still belongs to
In the range of technical solution of the present invention is protected.
Claims (13)
1. a Ω type top gate structure fin formula field effect transistor, it is characterised in that include Semiconductor substrate, device isolation, Ω
Type Fin channel region, source region, drain region, gate electrode layer, inter-level dielectric, contact hole and Metal 0；Wherein, shape on a semiconductor substrate
Become source region, drain region and connect the two Ω type Fin channel region and device isolation；The part surface of device isolation is formed grid
Electrode layer, gate electrode layer includes grid line bar and grid draw-out area, two sidewalls of grid line bar covering part Ω type Fin channel region and upper
Surface, grid draw-out area connects grid line bar；Inter-level dielectric cover source region, drain region, Ω type Fin channel region, gate electrode layer and device every
From；In inter-level dielectric, form contact hole, expose fractional source regions, drain region and the upper surface of grid draw-out area；Fill out in the contact hole
Fill metal Metal 0.
2. the preparation method of the fin formula field effect transistor of Ω type top gate structure as claimed in claim 1, its step includes:
A., semi-conductive substrate is provided；
B. forming the mask pattern of channel region, mask live width is for defining the live width at Ω type Fin top；
B1. one layer of dielectric material of deposit is as the first mask layer；
B2. by the line thickness at photoetching technique definition Ω type Fin top；
B3. utilize photoresist for sheltering, anisotropic etching the first mask layer, formed rectangle Fin mask, rectangle Fin mask
Live width is the line thickness at Ω type Fin top；
B4. remove photoresist；
C. source region, drain region, preliminary Fin channel region and device isolation are formed；
C1. one layer of dielectric material of deposit is covered by the second mask layer as the second mask layer, the first mask layer, to the second mask layer
Planarize；
C2. by photoetching technique definition source region and drain region；
C3. anisotropic etching the second mask layer and backing material, the backing material thickness etched away is Ω type Fin top
Highly；
C4. remove photoresist；
C5. one layer of dielectric material identical with the first mask layer of deposit time quarter, side wall mask is formed；
C6. anisotropic etching backing material, the backing material thickness etched away is the height below Ω type Fin；
C7. the isolation between device is formed；
D. the Fin channel region of Ω type is formed；
D1. using thermal oxidation technology to cut down preliminary Fin channel region, form complete Ω type Fin channel region, the time of oxidation is certainly
Determine Ω type Fin channel region to go to the bottom live width；
D2. the second mask layer is removed；
E. source and drain is injected and prepares gate electrode；
E1. by ion implantation technique, source and drain is carried out heavy doping, and activate annealing；
E2. remove the first mask layer, side wall mask and oxidation and cut down the silicon oxide formed；
E3. one layer of gate electrode layer is formed；
E4. by the figure of photoetching technique definition gate electrode；
E5. with photoresist for sheltering, anisotropic etching gate electrode layer, it is formed across grid line bar and the grid draw-out area of channel region,
Grid line bar covers at the top of Ω type Fin channel region and sidewall；
E6. remove photoresist；
F. the metal contact of each end is formed；
F1. inter-level dielectric is deposited；
F2. planarization is realized by chemically mechanical polishing；
F3. the contact hole respectively held by photoetching technique definition source, leakage, grid；
F4. anisotropic etching inter-level dielectric, exposes grid draw-out area and source, the upper surface in drain region；
F5. remove photoresist；
F6. filler metal Metal 0 in each contact hole；
F7. by metal Metal 0 is carried out chemical-mechanical planarization, it is achieved the conductive layers apart between device, device is reached
The effect of isolation；
G. finally enter conventional backend technique, complete device and prepare.
3. preparation method as claimed in claim 2, it is characterised in that Semiconductor substrate described in step A, serves as a contrast including body silicon
The end, SOI substrate, body germanium substrate or GOI substrate.
4. preparation method as claimed in claim 2, it is characterised in that in step C, trap is used for body silicon substrate, body germanium substrate
Isolation adds shallow-trench isolation；Shallow-trench isolation or island isolation are used for SOI substrate, GOI substrate.
5. preparation method as claimed in claim 2, it is characterised in that be lithographically described in step B, E beamwriter lithography or
193nm liquid immersion lithography.
6. preparation method as claimed in claim 2, it is characterised in that deposit described in step B, C, F is atomic layer deposition
ALD, low-pressure chemical vapor phase deposition LPCVD, plasma enhanced CVD PECVD, inductively coupled plasma strengthen
Chemical vapor deposition ICPECVD or sputtering.
7. preparation method as claimed in claim 2, it is characterised in that the dielectric material pair of the second mask layer 2 described in step C
The anisotropic corrosion rate of the first mask layer is more than 5:1.
8. preparation method as claimed in claim 2, it is characterised in that using thermal oxidation process in step D is dry-oxygen oxidation, wet
Oxygen oxidation or Oxidation Process By Hydrogen Oxygen Synthesis.
9. preparation method as claimed in claim 2, it is characterised in that in step E, annealing way uses rapid thermal annealing, spike
Annealing, the one glittered in annealing and laser annealing.
10. preparation method as claimed in claim 2, it is characterised in that in step E, when substrate is silicon-based substrate, be gate oxidation
Layer collocation polysilicon gate forms gate electrode layer, now uses dry-oxygen oxidation to prepare gate oxide, uses LPCVD to prepare polysilicon
Grid；Or high-K gate dielectric collocation metal gate forms gate electrode layer, now use ALD to prepare high-K gate dielectric, use PVD preparation gold
Belong to grid；If substrate is germanio substrate, uses high-K gate dielectric collocation metal gate to form gate electrode layer, now use ALD to prepare high K
Gate medium, uses PVD to prepare metal gate.
11. preparation methoies as claimed in claim 2, it is characterised in that in step B, C, E and F, anisotropic etching uses such as
Reactive ion etching RIE or inductively coupled plasma ICP.
12. preparation methoies as claimed in claim 2, it is characterised in that as the filler metal of conductive layer described in step F
Metal 0 is W, Cu, Al, Ti, Pt and composition metal lamination thereof.
13. preparation methoies as claimed in claim 2, it is characterised in that in step F, filler metal employing is evaporated, sputters, electroplated
With the one in chemical vapor deposition.
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| CN111697048A (en) * | 2019-03-13 | 2020-09-22 | 北京大学 | Method for improving total dose irradiation resistance of FinFET device |
| WO2023078083A1 (en) * | 2021-11-03 | 2023-05-11 | International Business Machines Corporation | Integrated short channel omega gate finfet and long channel finfet |
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