CN104377136B - Fin formula field effect transistor structure and preparation method thereof - Google Patents
Fin formula field effect transistor structure and preparation method thereof Download PDFInfo
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- CN104377136B CN104377136B CN201310360739.9A CN201310360739A CN104377136B CN 104377136 B CN104377136 B CN 104377136B CN 201310360739 A CN201310360739 A CN 201310360739A CN 104377136 B CN104377136 B CN 104377136B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract
The present invention provides a kind of fin formula field effect transistor structure and preparation method thereof, and the fin formula field effect transistor structure includes recessed in substrate, the substrate being formed with discrete first grid and second grid；Second gate dielectric layer, is strip and covers the first grid and second grid；It is formed with second grid material layer on the second gate dielectric layer intermediate region, the second grid material layer and the second gate dielectric layer below constitute the 3rd grid；A pair of side walls, are formed on the longitudinally opposed two side of second gate dielectric layer, source region and drain region are respectively formed with the substrate of the side wall both sides.The fin formula field effect transistor structure of the present invention has three independent grids, respectively different voltage can be added to be controlled raceway groove on three grids, operation is more flexible, can obtain bigger electric current and faster response speed, effectively the performance of lifting transistor arrangement；And raceway groove is located in substrate, reduces technology difficulty and cost-effective.
Description
Technical field
The invention belongs to field of semiconductor manufacture, it is related to a kind of transistor, more particularly to a kind of fin field effect crystal
Tubular construction and preparation method thereof.
Background technology
Current semiconductor manufacturing industry is developed rapidly under the guidance of Moore's Law, constantly improve integrated circuit performance and
Integration density, while reducing the power consumption of integrated circuit as far as possible.Therefore, high-performance, the ultrashort channel device of low-power consumption are prepared
The manufacturing focus of future semiconductor will be turned into.For complete depletion type transistor, in order to obtain the ideal sub-threshold ladder of transistor
Degree, the thickness of silicon main body must be about 1/3rd of transistor gate length.Reduce, reduce as far as possible however as grid length
The demand of silicon film thickness becomes increasingly unactual, because the processing that thickness is less than 10 nanometers of silicon fiml is extremely difficult.One
Aspect, the consistent sexual abnormality that chip is obtained in the magnitude of a nanometer is difficult, and on the other hand, thin silicon films are easy to follow-up
It is consumed in various cleaning procedures so that follow-up source-drain electrode growth becomes extremely difficult.
There is the fin semiconductor devices of double grid or multi-gate structure at present, above-mentioned ask can be solved to a certain extent
Topic.In general, double-gated devices have electrode in raceway groove both sides, so the thickness of silicon main body can be twice of single grid, and
And can still obtain complete depletion type transistor；Multi-gate structure is similarly.By multi-gate structure, grid can be strengthened very well for raceway groove
Control ability so that electric field line is difficult to reach source from drain terminal directly through raceway groove, thus can significantly improve leakage to gesture
Reduction effect is built, reduces leakage current, and suppress short-channel effect well.In addition, channel region need not be as conventional planar
Field-effect transistor equally carries out heavy doping to suppress short-channel effect, and the advantage that channel region is lightly doped is to reduce scattering
The mobility brought declines, so that the mobility of multi-gate structure device is significantly improved.Fin formula field effect transistor is made
For a kind of new construction device, very potential replacement conventional planar field-effect transistor.
Current fin formula field effect transistor structure has as a drawback that：（1）Technological requirement is high, because forming strip fin needs
The most of material of substrate surface is etched away, the strip fin structure of very little is left behind, technology difficulty is higher, is generally finished in etching
Also need to afterwards by regrowth to obtain the fin structure of ideal form, technique is relative complex；（2）Can only on two or more grids
Plus identical voltage, operating flexibility is high, is unfavorable for further improving the performance of transistor.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of fin formula field effect transistor knot
Structure and preparation method thereof is not high for solving fin formula field effect transistor structural manufacturing process complexity, operating flexibility in the prior art
The problem of.
In order to achieve the above objects and other related objects, the present invention provides a kind of making of fin formula field effect transistor structure
Method, at least comprises the following steps：
S1：One substrate is provided, it is recessed in the substrate to form discrete first grid and second grid；The first grid
Pole and second grid include first grid material layer and surround first grid Jie of the first grid material layer side wall and bottom
Matter layer；First grid and the second grid upper surface is flushed with the substrate top surface；
S2：The list structure of a covering first grid and second grid is formed over the substrate；The bar shaped knot
Structure includes the second gate dielectric layer and second grid material layer successively from bottom to top；
S3：A side wall is formed respectively on two longitudinally opposed sides of the list structure；Then in a pair of side walls two
Source region and drain region are formed respectively in the substrate of side；
S4：The strip structure two ends are etched until exposed portion the second gate dielectric layer upper surface；It is remaining after etching
Second grid material layer and the second gate dielectric layer below constitute the 3rd grid；
S5：Step S4 obtain structure on formed insulating barrier and be polished until the insulating barrier upper surface with it is described
3rd gate upper surface is flushed；Finally formed respectively above the first grid, second grid, source region and drain region
Contact hole.
Alternatively, the first grid and second grid being projected as in the horizontal plane are square, altitude range be 20nm~
60nm, width range is 10nm~30nm.
Alternatively, the longitudinally wide longitudinal direction more than or equal to the first grid and second grid of the 3rd grid is wide
Degree.
Alternatively, the transverse width of the 3rd grid is less than or equal to the spacing of the first grid and second grid.
Alternatively, the source region and drain region are formed by adulterating, and the depth of doping is less than or equal to described the
The height of one grid and second grid.
Alternatively, being formed in the step S1 before first grid and second grid is also included to substrate progress etc.
The step of gas ions are handled；The plasma includes the one or more in N, F or Ar.
Alternatively, the substrate is Si substrates or SOI substrate.
The present invention also provides a kind of fin formula field effect transistor structure, including：
It is recessed in substrate, the substrate to be formed with discrete first grid and second grid；The first grid and second
Grid includes first grid material layer and surrounds the first grid material layer side wall and the first gate dielectric layer of bottom；It is described
First grid and second grid upper surface are flushed with the substrate top surface；
Second gate dielectric layer, second gate dielectric layer is strip and covers the first grid and second grid；It is described
It is formed with second grid material layer on second gate dielectric layer intermediate region, the second grid material layer and second gate below
Dielectric layer constitutes the 3rd grid；
A pair of side walls, are formed at the longitudinally opposed two side of second gate dielectric layer and the second grid material layer is vertical
To on relative two side, the side wall upper surface is flushed with the 3rd gate upper surface；In the substrate of the side wall both sides
It is respectively formed with source region and drain region；
Insulating barrier, the insulating barrier is formed at the second gate dielectric layer surface at the 3rd grid two ends, the source area
Field surface and the drain region surface；The insulating barrier upper surface is flushed with the 3rd gate upper surface；The first grid
Contact hole is formed with above pole, second grid, source electrode and drain region.
Alternatively, the longitudinally wide longitudinal direction more than or equal to the first grid and second grid of the 3rd grid is wide
Degree.
Alternatively, the transverse width of the 3rd grid is less than or equal to the spacing of the first grid and second grid.
As described above, fin formula field effect transistor structure of the present invention and preparation method thereof, has the advantages that：This
Invention fin formula field effect transistor structure has three independent grids, can add different voltages pair on three grids respectively
Raceway groove is controlled, and obtains the performance of bigger electric current and faster response speed, effectively lifting transistor arrangement；The present invention's
Fin formula field effect transistor raceway groove is located in substrate, need not etch away substantial amounts of substrate during making, thus reduce etch period,
Cost has been saved, and has reduced technology difficulty.
Brief description of the drawings
Fig. 1 is shown as the process chart of the preparation method of the fin formula field effect transistor structure of the present invention.
The preparation method that Fig. 2 is shown as the fin formula field effect transistor structure of the present invention forms mask and figure on substrate
Cross-sectional view after change.
Fig. 3 is shown as the top view of structure shown in Fig. 2.
Fig. 4 is shown as the preparation method etched substrate formation groove of the fin formula field effect transistor structure of the present invention and in ditch
The cross-sectional view that groove sidewall and bottom are formed after the first gate dielectric layer.
Fig. 5 is shown as the top view of structure shown in Fig. 4.
Fig. 6 is shown as after the preparation method of the fin formula field effect transistor structure of present invention formation first grid material layer
Cross-sectional view.
Fig. 7 is shown as the preparation method formation first grid and second grid of the fin formula field effect transistor structure of the present invention
Cross-sectional view afterwards.
Fig. 8 is shown as the top view of structure shown in Fig. 7.
The preparation method formation one that Fig. 9 is shown as the fin formula field effect transistor structure of the present invention covers first grid and the
Cross-sectional view after the list structure of two grids.
Figure 10 is shown as the top view of structure shown in Fig. 9.
The preparation method that Figure 11 is shown as the fin formula field effect transistor structure of the present invention is longitudinally opposed in list structure
The structure top view after side wall is formed on two sides.
Figure 12 is shown as the preparation method formation source region and drain region of the fin formula field effect transistor structure of the present invention
Structure top view behind domain.
Figure 13 is shown as the structure after the preparation method of the fin formula field effect transistor structure of the present invention the 3rd grid of formation
Top view.
Figure 14 is shown as the diagrammatic cross-section of structure shown in Figure 13.
Figure 15 is shown as the section knot after the preparation method of the fin formula field effect transistor structure of present invention formation insulating barrier
Structure schematic diagram.
Figure 16 is shown as the top view of structure shown in Figure 15.
Figure 17 is shown as the cross-sectional view of the fin formula field effect transistor structure of the present invention.
Figure 18 is shown as the top view of structure shown in Figure 17.
Component label instructions
S1~S5 steps
1 substrate
2 masks
3 grooves
4 first gate dielectric layers
5 first grid material layers
6 first grids
7 second grids
8 second gate dielectric layers
9 second grid material layers
10 side walls
11 source regions
12 drain regions
13 the 3rd grids
14 insulating barriers
15 contact holes
d1The height of first grid
d2The width of first grid
d3First grid it is longitudinally wide
d4The spacing of first grid and second grid
d53rd grid it is longitudinally wide
d6The transverse width of 3rd grid
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 18.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment 1
Referring to Fig. 1, the process chart of the preparation method of the fin formula field effect transistor structure of the present invention is shown as, this
The preparation method of the fin formula field effect transistor structure of invention at least comprises the following steps：
Step S1 is recessed in the substrate to form discrete first grid and second grid there is provided a substrate；Described
One grid and second grid include the first of first grid material layer and the encirclement first grid material layer side wall and bottom
Gate dielectric layer；First grid and the second grid upper surface is flushed with the substrate top surface.
Specifically, the substrate can be any known Semiconductor substrate, including but not limited to Si substrates or SOI substrate.
Substrate described in the present embodiment is illustrated by taking Si substrates as an example.Referring to Fig. 2, as illustrated, first on substrate 1 by changing
The conventional methods such as vapour deposition one mask 2 of formation is learned, then in the graphical mask 2, formation two is recessed in the mask 2
Groove 3.The mask 2 can be photoresist or hard mask, be preferably hard mask in the present embodiment, advantageously form more smooth table
Face.The material of the hard mask includes but is not limited to SiN.Referring to Fig. 3, being shown as the top view of structure shown in Fig. 2.
Referring to Fig. 4, as illustrated, after the graphical mask 2, entering on the basis of the mask to the substrate 1
Two ditches for being for respectively forming first grid and second grid are recessed out in row etching, the substrate 1 under the region of groove 3
Groove, then forms the first gate dielectric layer 4 on the side wall of the groove and bottom.The material of first gate dielectric layer 4 includes
But conventional oxide or high K dielectric are not limited to, high K dielectric is a kind of material that may replace silica as gate medium, it has
Standby good insulation attribute, while higher field-effect can be produced between grid and silicon bottom passage, high K dielectric material includes
ZrO2、HfO2、Al2O3, one or more in HfSiO, HfSiON.Substrate described in the present embodiment is said using Si substrates
It is bright, directly the trenched side-wall and bottom can be aoxidized, form the first gate dielectric layer of silica 4.For for other materials
The substrate 1 of material, it would however also be possible to employ the method such as deposition forms first gate dielectric layer 4.Referring to Fig. 5, being shown as knot shown in Fig. 4
The top view of structure.
Referring to Fig. 6, as illustrated, filling first grid material layer 5, the first grid material layer in the trench
5 material includes but is not limited in polysilicon or metal material, the present embodiment by taking polysilicon as an example.Form the first grid material
After the bed of material 5, first grid material layer material and mask unnecessary outside the groove is removed using methods such as chemically mechanical polishings,
So as to form first grid and second grid, referring to Fig. 7, the diagrammatic cross-section of said structure is shown as, as illustrated, described
First grid 6 and second grid 7 are discrete and recessed be formed in the substrate 1.The first grid 6 and second grid 7 are wrapped
Include first grid material layer 5 and surround the side wall of first grid material layer 5 and the first gate dielectric layer 4 of bottom；Described first
Grid 6 and the upper surface of second grid 7 and the upper surface flush of substrate 1.In the present embodiment, the first grid 6 and second gate
Being projected as in the horizontal plane of pole 7 is square, as shown in fig. 7, the height of first grid is d1, the width of first grid is d2, wherein
d1Span be 20nm~60nm, d2Span be 10nm~30nm, the second grid 7 and the first grid 6
Height and width range it is identical.Referring to Fig. 8, being shown as showing first grid in the top view of structure shown in Fig. 7, figure
Longitudinally wide d3And the spacing d of first grid and second grid4.In the present embodiment, the second grid 7 has with first grid 6
Identical is longitudinally wide.
Specifically, can also be carried out before first grid 6 and second grid 7 is formed to the substrate 1 at plasma
Reason, the plasma includes the one or more in N, F or Ar, and it is to utilize the unsaturated state of ionic state and substrate surface that it, which is acted on,
Carry out chemical reaction to reduce substrate surface dangling bonds, improve device reliability.
Step S2, refers to Fig. 9 to Figure 10, forms a covering first grid and second grid over the substrate
List structure；The strip structure includes the second gate dielectric layer and second grid material layer successively from bottom to top.
Referring initially to Fig. 9, the cross-sectional view of said structure is shown as, the strip structure is situated between including second gate
Matter layer 8 and the second grid material layer 9 being formed thereon.The material of second gate dielectric layer 8 includes but is not limited to oxide
Or high K dielectric.The material of the second grid material layer 9 includes but is not limited to polysilicon or metal.It is Si for the substrate 1
The situation of substrate, the forming process of the strip structure can be that the structure upper surface for first obtaining step S1 is all aoxidized, so
Second grid material layer is deposited afterwards, then is patterned and is obtained the strip structure.Referring to Fig. 10, being shown as knot shown in Fig. 9
The top view of structure, as illustrated, the strip structure covers the first grid 6 and second grid 7.
Step S3, refers to Figure 11 to Figure 12, and one is formed respectively on two longitudinally opposed sides of the list structure
Side wall；Then source region and drain region are formed respectively in the substrate of a pair of side wall both sides.
Referring initially to Figure 11, as illustrated, being respectively formed with side on two longitudinally opposed sides of the strip structure
Wall 10, the material of the side wall 10 includes but is not limited to SiN, and the side wall is formed by the common process such as deposition and etching.Again
Figure 12 is referred to, as illustrated, being respectively formed with source region 11 and drain region 12 in the substrate of a pair of both sides of side wall 10.Tool
Body, the source region 11 and drain region 12 to be formed by adulterating in the substrate, and the depth of doping is less than or equal to described
The height of first grid 6 and second grid 7, can make it that channel region is formed between the first grid and second grid.
It is pointed out that the transverse width of the source region and the drain region is more than or equal to the first grid
Spacing between pole and second grid, the spacing between preferably greater than described first grid and second grid is described to ensure
In the first grid raceway groove adjacent with second grid carrier normal through.Source region and drain region are shown in Figure 12
Transverse width very wide situation.In addition, the transverse width of the side wall is also greater than or equal to the first grid and second gate
Spacing between pole, the transverse width of the side wall is wider, more advantageously reduces the parasitism between source region and each grid
Electric capacity, improves device performance.
Step S4, refers to Figure 13 to Figure 14, etches the strip structure two ends until the gate dielectric layer of exposed portion second
Upper surface；Remaining second grid material layer and the second gate dielectric layer below constitute the 3rd grid after etching.
Wherein, Figure 13 is shown as the top view of the structure of step S4 acquisitions, and Figure 14 is shown as the diagrammatic cross-section of the structure,
As shown in figure 14, remaining second grid material layer 9 and the second gate dielectric layer below constitute the 3rd grid 13 after etching.
The longitudinally wide d of the 3rd grid is also show in Figure 135And the 3rd grid transverse width d6, wherein, the longitudinal direction of the 3rd grid is wide
Spend d5More than or equal to the longitudinally wide d of the first grid3, the longitudinally wide d of the 3rd grid5Also greater than or equal to second gate
Pole it is longitudinally wide；The transverse width d of 3rd grid6Less than or equal to the first grid 6 and the spacing d of second grid 74.Figure
14 are shown the transverse width d of the 3rd grid6Equal to the first grid 6 and the spacing d of second grid 74Situation.For
The longitudinally wide of 3rd grid is more than the first grid and the longitudinally wide situation of second grid, because source and drain ion implanting
The window's position is really to be determined by the longitudinally wide of the 3rd grid plus side wall, so while the 3rd grid is longitudinally wide big
In the longitudinally wide of the first grid and second grid, ensure that source-drain area ion spreads but as long as passing through and optimizing the means such as annealing
It is enough to have a common boundary to the border of three grid, it is possible to ensure each raceway groove normally.For the transverse width d of the 3rd grid6It is less than
The spacing d of the first grid 6 and second grid 74Situation, can reduce between the 3rd grid and first grid parasitism electricity
Hold and the parasitic capacitance between the 3rd grid and second grid, device performance is more preferable.
Step S5, refers to Figure 15 to Figure 18, step S4 obtain structure on formed insulating barrier and be polished until
The insulating barrier upper surface is flushed with the 3rd gate upper surface；Finally respectively in the first grid, second grid, source electrode
Contact hole is formed above region and drain region.
Referring initially to Figure 15, it is shown as in the structure that is obtained in step S4 depositing insulating layer 14 and is polished until institute
The cross-sectional view after the upper surface of insulating barrier 14 is flushed with the 3rd gate upper surface is stated, Figure 16 is shown as shown in Figure 15
The top view of structure.Figure 17 is shown as formed as the diagrammatic cross-section of the structure after contact hole 15, so far, forms the fin of the present invention
Formula field-effect transistor structure.Figure 18 is shown as the top view of the structure.
The preparation method of the fin formula field effect transistor structure of the present invention forms three discrete grids：First grid 6,
The grid 13 of second grid 7 and the 3rd, so that three raceway grooves are formd in substrate 1, respectively positioned at the first grid 6 and second
In 7 of laterally opposite two adjacent substrates of medial surface of grid and in the adjacent substrate of the 3rd grid lower surface.During work,
Respectively different voltage can be added to be controlled raceway groove on three grids, obtain bigger electric current and faster response speed
The performance of degree, effectively lifting transistor arrangement；In addition, the fin formula field effect transistor raceway groove of the present invention is located in substrate, make
Shi Wuxu etches away substantial amounts of substrate, therefore reduces etch period, saved cost, and reduces technology difficulty.
Embodiment 2
Figure 17 and Figure 18 is referred to, the present invention also provides a kind of fin formula field effect transistor structure, including：
It is recessed in substrate 1, the substrate 1 to be formed with discrete first grid 6 and second grid 7；The first grid 6 and
Second grid 7 includes first grid material layer 5 and surrounds the side wall of first grid material layer 5 and the first gate medium of bottom
Layer 4；The first grid 6 and the upper surface of second grid 7 and the upper surface flush of substrate 1；
Second gate dielectric layer 8, second gate dielectric layer 8 is strip and covers the first grid 6 and second grid 7；
It is formed with second grid material layer 9 on the intermediate region of second gate dielectric layer 8, the second grid material layer 9 and below
The second gate dielectric layer constitute the 3rd grid 13；
A pair of side walls 10, are formed at the longitudinally opposed two side of second gate dielectric layer 8 and the second grid material
On 9 longitudinally opposed two side of layer, the upper surface of side wall 10 and the upper surface flush of the 3rd grid 13；10 liang of the side wall
Source region and drain region are respectively formed with the substrate of side；
Insulating barrier 14, the insulating barrier 14 is formed at the surface of the second gate dielectric layer 8, described at the two ends of the 3rd grid 13
Source region surface and the drain region surface；The upper surface of insulating barrier 14 and the upper surface flush of the 3rd grid 13；
Contact hole 15 is formed with above the first grid 6, second grid 7, source electrode and drain region.
Specifically, the 3rd grid 13 is longitudinally wide vertical more than or equal to the first grid 6 and second grid 7
To width, the transverse width of the 3rd grid 13 is less than or equal to the spacing of the first grid 6 and second grid 7.
Specifically, the first grid 6, the grid 13 of second grid 7 and the 3rd is the grid structures based on polysilicon or are
High-K metal gate structure, can also be polysilicon and metal composite structure, the first grid 6, the grid of second grid 7 and the 3rd
It may include dopant in 13.The first grid material layer 5 and second grid material layer 9 can be single layer structure, or
Composite lamainated structure.
The fin formula field effect transistor structure of the present invention includes three discrete grids, and three ditches are formed with the substrate
Same or different voltage can be added on road, three grids respectively, operable scope is big, and more flexibility can be obtained bigger
Electric current and faster response speed so that effectively lifted transistor arrangement performance.
In summary, the preparation method of fin formula field effect transistor structure of the present invention produces three in transistor arrangement
Independent grid, can obtain bigger electric current and more respectively on three grids plus different voltage is controlled to raceway groove
The performance of fast response speed, effectively lifting transistor arrangement；The fin formula field effect transistor raceway groove of the present invention is located in substrate,
Substantial amounts of substrate need not be etched away during making, therefore reduces etch period, saved cost, and reduces technology difficulty.Institute
So that the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of preparation method of fin formula field effect transistor structure, it is characterised in that at least comprise the following steps：
S1：One substrate is provided, it is recessed in the substrate to form discrete first grid and second grid；The first grid and
Second grid includes first grid material layer and surrounds the first grid material layer side wall and the first gate dielectric layer of bottom；
First grid and the second grid upper surface is flushed with the substrate top surface；
S2：The list structure of a covering first grid and second grid is formed over the substrate；The strip structure is certainly
Include the second gate dielectric layer and second grid material layer on down successively；
S3：A side wall is formed respectively on two longitudinally opposed sides of the list structure；Then a pair of side wall both sides
Source region and drain region are formed in substrate respectively；
S4：The strip structure two ends are etched until exposed portion the second gate dielectric layer upper surface；Remaining second after etching
Gate material layers and the second gate dielectric layer below constitute the 3rd grid；
S5：Insulating barrier is formed in the structure that step S4 is obtained and is polished until the insulating barrier upper surface and the described 3rd
Gate upper surface is flushed；Respectively contact hole is formed above the first grid, second grid, source region and drain region.
2. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：The first grid
Pole and second grid being projected as in the horizontal plane are square, and altitude range is 20nm~60nm, and width range is 10nm~30nm.
3. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：3rd grid
Pole it is longitudinally wide longitudinally wide more than or equal to the first grid and second grid.
4. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：3rd grid
The transverse width of pole is less than or equal to the spacing of the first grid and second grid.
5. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：The source area
Domain and drain region are formed by adulterating, and the depth of doping is less than or equal to the height of the first grid and second grid.
6. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：In the step
The step of also including carrying out corona treatment to the substrate before first grid and second grid is formed in S1；The grade from
Daughter includes the one or more in N, F or Ar.
7. the preparation method of fin formula field effect transistor structure according to claim 1, it is characterised in that：The substrate is
Si substrates or SOI substrate.
8. a kind of fin formula field effect transistor structure, it is characterised in that including：
It is recessed in substrate, the substrate to be formed with discrete first grid and second grid；The first grid and second grid
Include first grid material layer and surround the first grid material layer side wall and the first gate dielectric layer of bottom；Described first
Grid and second grid upper surface are flushed with the substrate top surface；
Second gate dielectric layer, second gate dielectric layer is strip and covers the first grid and second grid；Described second
It is formed with second grid material layer on gate dielectric layer intermediate region, the second grid material layer and the second gate medium below
Layer constitutes the 3rd grid；
A pair of side walls, are formed at the longitudinally opposed two side of second gate dielectric layer and the longitudinal phase of the second grid material layer
To two side on, the side wall upper surface is flushed with the 3rd gate upper surface；In the substrate of the side wall both sides respectively
It is formed with source region and drain region；
Insulating barrier, the insulating barrier is formed at the second gate dielectric layer surface at the 3rd grid two ends, the source region table
Face and the drain region surface；The insulating barrier upper surface is flushed with the 3rd gate upper surface；The first grid,
Contact hole is formed with above two grids, source electrode and drain region.
9. fin formula field effect transistor structure according to claim 8, it is characterised in that：The longitudinal direction of 3rd grid is wide
Degree is longitudinally wide more than or equal to the first grid and second grid.
10. fin formula field effect transistor structure according to claim 8, it is characterised in that：The transverse direction of 3rd grid
Width is less than or equal to the spacing of the first grid and second grid.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6876042B1 (en) * | 2003-09-03 | 2005-04-05 | Advanced Micro Devices, Inc. | Additional gate control for a double-gate MOSFET |
| CN101068029A (en) * | 2007-06-05 | 2007-11-07 | 北京大学 | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof |
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| US6800905B2 (en) * | 2001-12-14 | 2004-10-05 | International Business Machines Corporation | Implanted asymmetric doped polysilicon gate FinFET |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6876042B1 (en) * | 2003-09-03 | 2005-04-05 | Advanced Micro Devices, Inc. | Additional gate control for a double-gate MOSFET |
| CN101068029A (en) * | 2007-06-05 | 2007-11-07 | 北京大学 | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof |
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