CN109950305A - A kind of semiconductor power device and preparation method thereof - Google Patents
A kind of semiconductor power device and preparation method thereof Download PDFInfo
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- CN109950305A CN109950305A CN201711392314.0A CN201711392314A CN109950305A CN 109950305 A CN109950305 A CN 109950305A CN 201711392314 A CN201711392314 A CN 201711392314A CN 109950305 A CN109950305 A CN 109950305A
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Abstract
To overcome in existing semiconductor power device in the presence of sensitive to interface charge, the problem of influencing device lifetime and device reverse withstand voltage ability is caused to reduce, the present invention provides a kind of semiconductor power devices, including substrate, first oxygen layer, first offset field plate and the second offset field plate, the inner side surface of substrate is formed with field limiting ring, second offset field plate is between first offset field plate and the field limiting ring, first offset field plate and second offset field plate are electrically coupled, and second offset field plate and substrate by the just oxygen layer barrier to be formed with first capacitor area, first offset field plate, which is extended, is formed with the second capacitive region between the part and substrate of the second offset field plate, the capacitor of first capacitor area unit area is greater than the capacitor of the second capacitive region unit area.Meanwhile the invention also discloses the preparation methods of above-mentioned semiconductor power device.Semiconductor power device anti-breakdown voltage with higher provided by the invention and stronger anti-Interface electric field interference performance.
Description
Technical field
The invention belongs to semiconductor power device technology fields, and in particular to a kind of semiconductor power device and its preparation side
Method.
Background technique
With the continuous development of science and technology, the application requirement of semiconductor power device is gradually increased, to semiconductor devices
Terminal voltage endurance capability, more stringent requirements are proposed for reliability.Terminal is mainly in semiconductor power device at present or application has
There is the field limiting ring structure terminal of drift field plate, it is simple easy to accomplish in the end process, and by constantly coupling field limiting ring
And field plate, terminal can be made to reach a relatively high voltage endurance capability.
With the raising of applied voltage platform, there is the field limiting ring structure terminal of drift field plate to need the ability of wider area
Meet the needs of application.Aerospace, bullet train and armament weapon application semiconductor power device need, in face of than
More severe external environment, external electrical field, charge and hot conditions are easy to make the conventional field limiting ring structure with drift field plate
Terminal interface electric charge accumulation, and have the field limiting ring structure terminal of drift field plate more sensitive to interface charge, influence device lifetime
The reduction of device reverse withstand voltage ability is even resulted in, so as to cause application end failure.
Summary of the invention
It is sensitive to interface charge for existing in existing semiconductor power device, it influences device lifetime and causes device anti-
The problem of reducing to voltage endurance capability, the present invention provides a kind of semiconductor power devices and preparation method thereof.
It is as follows that the present invention solves technical solution used by above-mentioned technical problem:
On the one hand, the present invention provides a kind of semiconductor power device, including substrate, first oxygen layer, the first offset field plate and
Second offset field plate, the inner side surface of the substrate are formed with field limiting ring, and the just oxygen layer is located at the outer side surface of the substrate,
The head end of first offset field plate is electrically coupled with the field limiting ring, and the tail end of first offset field plate is towards the field limiting ring
The offset of ring outside direction, second offset field plate is between first offset field plate and the field limiting ring, and described first partially
Field plate and second offset field plate is moved to be electrically coupled, and second offset field plate and the substrate by the just oxygen layer obstruct with
It is formed with first capacitor area, the tail end of first offset field plate extends second offset field plate, and first offset
Field plate, which extends, is formed with the second capacitive region, the first capacitor area between the part and the substrate of second offset field plate
The capacitor of unit area is greater than the capacitor of second capacitive region unit area.
Optionally, the semiconductor power device further includes insulating medium layer, and the insulating medium layer is covered in described first
In oxygen layer and second offset field plate, first offset field plate is located on the insulating medium layer, the insulating medium layer
On be provided with the first contact hole being electrically coupled for first offset field plate and second offset field plate and for first offset
The second contact hole that field plate and the field limiting ring are electrically coupled, at second capacitive region, first offset field plate and described
It is obstructed between substrate by the just oxygen layer and the insulating medium layer.
Optionally, the semiconductor power device further includes passivation layer, and the passivation layer is located on the insulating medium layer,
Third capacitive region is formed between the tail end and the substrate of first offset field plate, second capacitive region unit area
Capacitor is greater than the capacitor of third capacitive region unit area, and the third capacitive region is located at second capacitive region away from described
The side in first capacitor area, at the third capacitive region, by the just oxygen between first offset field plate and the substrate
Layer, the insulating medium layer and passivation layer barrier.
Optionally, the passivation layer includes ramp and evener, the third capacitive region include the 4th capacitive region and
5th capacitive region, between second capacitive region and the 5th capacitive region, second capacitive region is single for the 4th capacitive region
The capacitor of plane product is greater than the capacitor of the 4th capacitive region unit area, and the capacitor of the 4th capacitive region unit area is greater than
The capacitor of the 5th capacitive region unit area；
At the 4th capacitive region, between first offset field plate and the substrate by it is described just oxygen layer, it is described absolutely
Edge dielectric layer and ramp barrier；
At the 5th capacitive region, between first offset field plate and the substrate by it is described just oxygen layer, it is described absolutely
Edge dielectric layer and evener barrier.
Optionally, multiple field limiting rings are formed on the substrate, multiple field limiting rings are arranged concentrically from the inside to the outside,
Corresponding, first offset field plate, second offset field plate and the passivation layer are also multiple, multiple first biased fields
Plate, multiple second offset field plates, multiple passivation layers and multiple field limiting rings are arranged in a one-to-one correspondence, the first internally positioned offset field plate
Tail end extend to the head end positioned at the first external offset field plate, and the tail end of the first internally positioned offset field plate and be located at
It is obstructed between the head end of the first external offset field plate by the passivation layer.
Optionally, the semiconductor power device further includes third offset field plate and the 4th offset field plate, the substrate
Inner side surface is formed with cut-off ring, and the cut-off ring is arranged concentrically with the field limiting ring, and the cut-off ring is located at field limit
The outside of ring, the head end of the third offset field plate are electrically coupled with the cut-off ring, and the tail end of the third offset field plate is towards institute
State cut-off ring ring in direction offset, the 4th offset field plate between the third offset field plate and the cut-off ring,
The third offset field plate and the 4th offset field plate are electrically coupled, and the 4th offset field plate and the substrate are by described first
Oxygen layer barrier, the tail end of the third offset field plate extend the 4th offset field plate.
Optionally, first offset field plate and the third offset field plate are that metal contacts field plate, second offset
Field plate and the 4th offset field plate are polysilicon field plate.
Optionally, the semiconductor power device further includes protective layer, and the protective layer is covered in first biased field
Outside plate.
On the other hand, the present invention provides the preparation method of semiconductor power device as described above, comprising the following steps:
Substrate is provided, just oxygen layer has been formed on the substrate；
Open field limiting ring region on substrate by chemical wet etching, the inner side surface by ion implanting in substrate forms field
Ring is limited, in the long oxide layer of boiler tube knot；
Deposit polycrystalline silicon on substrate is doped polysilicon, and carries out chemical wet etching to polysilicon, forms second partially
Move field plate；
Chemical wet etching forms contact hole, and splash-proofing sputtering metal layer carries out chemical wet etching to metal layer, forms the first offset field plate.
Optionally, the substrate is silicon substrate, forms the first oxygen layer of silica on the silicon substrate by thermal oxide.
Optionally, before described " deposit polycrystalline silicon on substrate " further include:
It opens cut-off ring region on substrate by chemical wet etching, is formed and cut in the inner side surface of substrate by ion implanting
Only ring, the cut-off ring are located at the outside of the field limiting ring.
Optionally, the 4th offset field plate is formed while forming the second offset field plate, is forming the first offset field plate
It is formed simultaneously third offset field plate.
Optionally, before described " chemical wet etching formation contact hole " further include:
Silica is deposited on substrate, forms insulating medium layer, and the insulating medium layer covers described second partially simultaneously
Move field plate and the just oxygen layer；
Boron-phosphorosilicate glass is deposited on insulating medium layer, and chemical wet etching is carried out to boron-phosphorosilicate glass, obtains passivation layer.
Optionally, after described " forming the first offset field plate " further include:
Protective layer is deposited, and hot setting is carried out to protective layer.
The semiconductor power device provided according to the present invention utilizes the ladder of the first offset field plate and the second offset field plate point
Cloth, so that forming the multistage field plate of multiple and different capacitors between the first offset field plate, the second offset field plate and substrate, and along first
The capacitor in capacitive region to the second capacitive region direction gradually decreases, when semiconductor power device is in reverse bias condition, first
Offset field plate and the second offset field plate limit by potential clamper in next field limiting ring from the field limiting ring edge to next
Ring surface, substrate surface and field plate potential difference are increasing, available by C=Q/U, and the charge that field plate capacitance exhausts will be on the scene
It is uniformly distributed between limit ring, therefore too strong peak electric field is not present between field limiting ring, substrate surface field distribution is more uniform, mentions
High semiconductor power device voltage endurance capability and the surface weakness leakage point of electricity for reducing surface field too strong production, to improve
Device reliability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 2 is the partial structure diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 3 is the first state structural schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 4 is the second status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 5 is the third state structural schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 6 is the 4th status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 7 is the 5th status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 8 is the 6th status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Fig. 9 is the 7th status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention；
Figure 10 is the state structural schematic diagram eight-shaped of semiconductor power device provided in an embodiment of the present invention；
Figure 11 is the 9th status architecture schematic diagram of semiconductor power device provided in an embodiment of the present invention.
Appended drawing reference in Figure of description is as follows:
1, substrate；11, field limiting ring；12, end ring；13, the first optical mask pattern；14, the second optical mask pattern；15, it protects
Sheath；2, first oxygen layer；3, the first offset field plate；4, the second offset field plate；5, insulating medium layer；51, the first contact hole；52,
Two contact holes；53, third contact hole；54, the 4th contact hole；6, passivation layer；61, ramp；62, evener；7, third deviates
Field plate；8, the 4th offset field plate；9a, first capacitor area；9b, the second capacitive region；9c, third capacitive region；91, the 4th capacitive region；
92, the 5th capacitive region.
Specific embodiment
In order to which the technical problems, technical solutions and beneficial effects solved by the present invention is more clearly understood, below in conjunction with
Accompanying drawings and embodiments, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
In the description of the present invention, it is to be understood that, term " head end ", " tail end ", "inner", "outside", "upper", "top",
The orientation or positional relationship of the instructions such as "bottom" is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of describing this hair
Bright and simplified description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with specific orientation
Construction and operation, therefore be not considered as limiting the invention.In the description of the present invention, unless otherwise indicated, " multiple "
It is meant that two or more.
Referring to figure 1 and figure 2, one embodiment of the invention discloses a kind of semiconductor power device, including substrate 1, just
Oxygen layer 2, the first offset field plate 3 and the second offset field plate 4, the inner side surface of the substrate 1 are formed with field limiting ring 11, the just oxygen
Layer 2 is located at the outer side surface of the substrate 1, and the head end of first offset field plate 3 is electrically coupled with the field limiting ring 11, and described the
The ring outside direction of the tail end of one offset field plate 3 towards the field limiting ring 11 deviates, and second offset field plate 4 is located at described first partially
It moves between field plate 3 and the field limiting ring 11, first offset field plate 3 and second offset field plate 4 are electrically coupled, and described the
Two offset field plates 4 are with the substrate 1 by just oxygen layer 2 barrier to be formed with first capacitor area 9a, first offset field plate 3
Tail end extend second offset field plate 4, and first offset field plate 3 extends the portion of second offset field plate 4
Point it is formed with the second capacitive region 9b the substrate 1 between, the capacitor of the first capacitor area 9a unit area is greater than described the
The capacitor of two capacitive region 9b unit areas.
The field limiting ring 11 is the partial pressure ring structure for improving breakdown voltage, and the field limiting ring 11 is located at space charge
Area, after break-through, the current potential of field limiting ring 11 is improved, if further increasing back-pressure, space-charge region will be attached in field limiting ring 11
Nearly expansion, the increased voltage of institute will be undertaken by field limiting ring 11.Although 11 technology of field limiting ring can make semiconductor power device reach compared with
The advantages of high-breakdown-voltage, but it is very sensitive to interface charge, therefore it is provided with the first offset field plate 3 and the second offset field plate 4,
First offset field plate 3 and second offset field plate 4 can be such that the electric fields uniform between two neighboring field limiting ring 11 is distributed,
The effect that conducting in time neutralizes Interface electric field is also functioned to simultaneously.
In some embodiments, the substrate 1 is N-type silicon substrate, and the field limiting ring 11 is p-type injection region.
The field limiting ring 11, which is injected by the partial region of the substrate 1 by P-type ion, to be formed, therefore the field limiting ring 11 is embedding
The inner side surface for entering the substrate 1 is integrally formed with the substrate 1.
The just oxygen layer 2 is silicon dioxide layer, with a thickness of 1~1.5 μm.
The effect of the just oxygen layer 2 is to avoid the second offset field plate 4 and substrate 1 and field to the progress insulation protection of substrate 1
The direct contact of ring 11 is limited, while avoiding influence of the external electrical field to substrate 1.
If the thickness of the just oxygen layer 2 is excessively thin, it is difficult to play insulation effect；If the thickness of the just oxygen layer 2 is blocked up,
Cause the capacitor between second offset field plate 4 and substrate 1 too small, influences its electric field adjusting effect.
It should be noted that in other embodiments, other materials for realizing function of the same race can also be used in the just oxygen layer 2
It is replaced.
The semiconductor power device further includes insulating medium layer 5, and the insulating medium layer 5 is covered in the just oxygen layer 2
In second offset field plate 4, first offset field plate 3 is located on the insulating medium layer 5, the insulating medium layer 5
On be provided with the first contact hole 51 being electrically coupled for first offset field plate 3 and second offset field plate 4 and supply described first
The second contact hole 52 that offset field plate 3 and the field limiting ring 11 are electrically coupled, at the second capacitive region 9b, first offset
It is obstructed between field plate 3 and the substrate 1 by just oxygen layer 2 and the insulating medium layer 5.
In some embodiments, the insulating medium layer 5 is silicon dioxide layer, with a thickness of 0.8~2 μm.
The effect of the insulating medium layer 5 is to adjust the dielectric constant and width of the second capacitive region 9b intermediate medium
Degree, to adjust the capacitor of the second capacitive region 9b.
If the thickness of the insulating medium layer 5 is excessively thin, it is difficult to make the second capacitive region 9b and the first capacitor area
The capacitor of 9a is distinguished；If the thickness of the insulating medium layer 5 is blocked up, lead to the capacitor mistake of the second capacitive region 9b
It is small, influence its electric field adjusting effect.
In some embodiments, the semiconductor power device further includes passivation layer 6, and the passivation layer 6 is located at described exhausted
On edge dielectric layer 5, it is formed with third capacitive region 9c between the tail end and the substrate 1 of first offset field plate 3, described second
The capacitor of capacitive region 9b unit area is greater than the capacitor of the third capacitive region 9c unit area, and the third capacitive region 9c is located at
The second capacitive region 9b deviates from the side of the first capacitor area 9a, at the third capacitive region 9c, first offset
It is obstructed between field plate 3 and the substrate 1 by just oxygen layer 2, the insulating medium layer 5 and the passivation layer 6.
The passivation layer 6 is borophosphosilicate glass layer, with a thickness of 2~6 μm.
It should be noted that in other embodiments, other materials for realizing function of the same race can also be used in the passivation layer 6
It is replaced.
As shown in Fig. 2, in a more preferred embodiment, the passivation layer 6 includes ramp 61 and evener 62, described
Third capacitive region 9c includes the 4th capacitive region 91 and the 5th capacitive region 92, and the 4th capacitive region 91 is located at second capacitive region
Between 9b and the 5th capacitive region 92, the capacitor of the second capacitive region 9b unit area is greater than 91 unit plane of the 4th capacitive region
Long-pending capacitor, the capacitor of 91 unit area of the 4th capacitive region are greater than the capacitor of 92 unit area of the 5th capacitive region.
At the 4th capacitive region 91, by the just oxygen layer 2, institute between first offset field plate 3 and the substrate 1
It states insulating medium layer 5 and the ramp 61 obstructs.
At the 5th capacitive region 92, by the just oxygen layer 2, institute between first offset field plate 3 and the substrate 1
It states insulating medium layer 5 and the evener 62 obstructs.
Ladder distribution and lining of the present invention using the first offset field plate 3 and the second offset field plate 4 of large area covering terminal
The intermediate medium of different-thickness between 1 surface of bottom forms the multistage field plate of several different capacitors, and is made by multistage field plate
Electric fields uniform is distributed between two field limiting rings 11, to obtain higher voltage endurance capability.
As shown in Fig. 2, on the outside of the ring of field limiting ring 11, the first offset field plate 3, the second offset field plate 4 and 1 surface shape of substrate
At 4 kinds of different capacitive regions (first capacitor area 9a, the second capacitive region 9b, the 4th capacitive region 91 and the 5th capacitive region 92): wherein
The capacitor of first capacitor area 9a unit area is C1, in first capacitor area 9a, the second offset field plate 4 is formed with 1 surface of substrate
Intermediate medium only just oxygen layer 2；The capacitor of second capacitive region 9b unit area is C2, in the second capacitive region 9b, first partially
The intermediate medium for moving field plate 3 and the formation of 1 surface of substrate is first oxygen layer 2 and insulating medium layer 5；4th capacitive region, 91 unit area
Capacitor is C3, in the 4th capacitive region 91, the intermediate medium that the first offset field plate 3 is formed with 1 surface of substrate is first oxygen layer 2, absolutely
Edge dielectric layer 5 and ramp 61 (6 wet-etching technology of passivation layer forms a longer slope in wafer production), are gradual change electricity
Hold；The capacitor of 5th capacitive region, 92 unit area is C4, in the 5th capacitive region 92, the first offset field plate 3 and 1 surface shape of substrate
At intermediate medium be first oxygen layer 2, insulating medium layer 5 and evener 62 (the 6 consistency of thickness part of passivation layer).
C=ε S/4k π d
From the above equation, we can see that the capacitor of unit area is only and dielectric constant and width, four kinds of capacitive regions in terminal of the present invention
Unit area capacitance size sequence be C1> C2> C3> C4.When the power semiconductor is in reverse bias condition,
First offset field plate 3 and the second offset field plate 4 are by potential clamper in terminal field limiting ring, i.e., from 11 edge of field limiting ring under
One 11 surface of field limiting ring, 1 surface of substrate and field plate potential difference are increasing, and available by C=Q/U, field plate capacitance exhausts
Charge will be uniformly distributed between field limiting ring 11, therefore too strong peak electric field is not present between field limiting ring 11, power partly leads
Body device surface field distribution is more uniform, improves power semiconductor voltage endurance capability and reduces surface field and produces by force very much
Raw surface weakness leakage point of electricity, to improve power semiconductor reliability.
As shown in Figure 1, being formed with multiple field limiting rings 11 on the substrate 1, multiple field limiting rings 11 are from the inside to the outside
Be arranged concentrically, it is corresponding, first offset field plate 3, second offset field plate 4 and the passivation layer 6 be also it is multiple, it is more
A first offset field plate 3, multiple second offset field plates 4, multiple passivation layers 6 and multiple field limiting rings 11 are arranged in a one-to-one correspondence, and are located at
The tail end of the first internal offset field plate 3 extends to the head end positioned at the first external offset field plate 3, and internally positioned first
It is obstructed between the tail end of offset field plate 3 and the head end of the first offset field plate 3 positioned at outside by the passivation layer 6.
In this power semiconductor, the first offset field plate 3 used extends directly into next 11 region of field limiting ring, from
And it avoids and causes the risk of strong electrical field in 3 tail end of the first offset field plate, and the first offset field plate 3 is substantially covered
On entire power semiconductor surface, the ability of the anti-external electrical field of device and charge is improved；Simultaneously in order to avoid first
Conducting between offset field plate 3 has one layer of thicker passivation layer between field limiting ring 11, prevents the ingoing powers such as steam, charge half
Conductor device surface, the passivation layer 6 are located at the 3 tail end bottom of the first offset field plate, can be by first offset field plate 3
Tail end is raised, so that 3 tail end of the first offset field plate and next first offset field plate, 3 head end misplace up and down, to reach protection device
Effect and increase stair-step so that electric fields uniform be distributed, obtain higher pressure resistance.
The semiconductor power device further includes third offset field plate 7 and the 4th offset field plate 8, the surface of the substrate 1
Inside is formed with cut-off ring 12, and the cut-off ring 12 is arranged concentrically with the field limiting ring 11, and the cut-off ring 12 is positioned at described
The outside of field limiting ring 11, the head end of the third offset field plate 7 are electrically coupled with the cut-off ring 12, the third offset field plate 7
Tail end deviated towards direction in the ring of the cut-off ring 12, the 4th offset field plate 8 is located at the third offset field plate 7 and institute
It states between cut-off ring 12, the third offset field plate 7 and the 4th offset field plate 8 are electrically coupled, and the 4th offset field plate 8
It is obstructed with the substrate 1 by the just oxygen layer 2, the tail end of the third offset field plate 7 extends the 4th offset field plate 8.
The doping type of the cut-off ring 12 is identical as substrate 1 and doping concentration is higher by substrate 1.In the present embodiment, institute
Stating cut-off ring 12 is N-type injection region.The cut-off ring 12 be terminal protection structure, the semiconductor power device conducting when it
Electric current is not provided, in reverse blocking state for terminating inversion layer formed on the surface of the device due to various reasons.
First offset field plate 3 and the third offset field plate 7 are that metal contacts field plate, second offset field plate 4
It is polysilicon field plate with the 4th offset field plate 8.
As shown in figure 11, in some embodiments, the semiconductor power device further includes protective layer 15, the protective layer
15 are covered in outside first offset field plate 3, protect for the interface to semiconductor power device, while reducing outside
Electric jamming.
Another embodiment of the present invention provides the preparation method of semiconductor power device as described above, including following step
It is rapid:
Substrate 1 is provided, just oxygen layer 2 is formed on substrate 1；
Field limiting ring region is opened on substrate 1 by chemical wet etching, the inner side surface by ion implanting in substrate 1 is formed
Field limiting ring 11, in the long oxide layer of boiler tube knot；
Deposit polycrystalline silicon, is doped polysilicon on substrate 1, and carries out chemical wet etching to polysilicon, forms second
Offset field plate 4；
Chemical wet etching forms contact hole, and splash-proofing sputtering metal layer carries out chemical wet etching to metal layer, forms the first offset field plate 3.
Specifically, the preparation method of the semiconductor power device includes:
As shown in figure 3, providing substrate 1, the substrate 1 is silicon substrate 1, is formed on the silicon substrate 1 by thermal oxide
The first oxygen layer 2 of silica.
In other embodiments, the just oxygen layer 2 can also pass through chemical meteorology deposition, physical vapor deposition and anodic oxidation
Etc. modes form.
As shown in figure 4, opening field limiting ring region on substrate 1 by chemical wet etching.
In some embodiments, chemical wet etching mainly include 1 surface clean drying of silicon substrate, it is linging, spin coating photoresist, soft
Dry, alignment exposure, it is rear dry, development, it is hard dry, etching and detection process, to form the first photomask pattern, in the first light of formation
It is etched on mask pattern, extra first oxygen layer 2 is removed, the field limiting ring region on silicon substrate 1 is exposed, remove the first light
Mask pattern 13.
It is similar to the above using chemical wet etching method below.
As shown in figure 5, the inner side surface by ion implanting in substrate 1 forms field limiting ring 11, in the long oxidation of boiler tube knot
Layer.
The ion implanting of the field limiting ring 11 is injected using P-type ion, and boron ion, aluminium ion can be used in the P-type ion
Deng according to the selection of the progress ion implantation dosage of dopant concentration needed for the field limiting ring 11.
As shown in fig. 6, cut-off 12 region of ring is opened on substrate 1 by chemical wet etching, by ion implanting in substrate 1
Inner side surface forms cut-off ring 12, and the cut-off ring 12 is located at the outside of the field limiting ring 11.
The second photomask pattern is formed on 1 surface of substrate, is etched on the second photomask pattern of formation, it will be extra
First oxygen layer 2 remove, by silicon substrate 1 cut-off ring region expose, remove the second optical mask pattern 14.
The ion implanting of the cut-off ring 12 is injected using N-type ion, and arsenic ion, phosphonium ion can be used in the N-type ion
Deng according to the selection of dopant concentration progress ion implantation dosage needed for the cut-off ring 12.
As shown in fig. 7, the deposit polycrystalline silicon on substrate 1, makes polysilicon be covered in just 2 surface of oxygen layer, to polysilicon
It is doped, and chemical wet etching is carried out to polysilicon, retain field limiting ring 11 and end the Offset portion of the polysilicon of 12 top of ring,
The second offset field plate 4 and the 4th offset field plate 8 are formed, the ring outside direction of second offset field plate 4 towards the field limiting ring 11 is inclined
It moves, the 4th offset field plate 8 is deviated towards direction in the ring of the cut-off ring 12.
As shown in figure 8, the chemical meteorology deposition silica on substrate 1, forms insulating medium layer 5, the dielectric
Layer 5 covers second offset field plate 4 and the just oxygen layer 2 simultaneously.
In other embodiments, the insulating medium layer 5 can also be formed by modes such as physical vapor depositions,
As shown in figure 9, depositing boron-phosphorosilicate glass on insulating medium layer 5, and chemical wet etching is carried out to boron-phosphorosilicate glass, obtained
It is consistent with the above to the position of passivation layer 6, the passivation layer 6.
As shown in Figure 10, chemical wet etching forms contact hole, splash-proofing sputtering metal layer, to metal layer on the insulating medium layer 5
Chemical wet etching is carried out, the first offset field plate 3 and third offset field plate 7 are formed, the contact hole includes supplying first biased field
The first contact hole 51 that plate 3 and second offset field plate 4 are electrically coupled, for first offset field plate 3 and the field limiting ring 11
The second contact hole 52 being electrically coupled, the third contact hole 53 being electrically coupled for third offset field plate 7 and the 4th offset field plate 8 with
And for third offset field plate 7 and the 4th contact hole 54 for ending ring 12 and being electrically coupled.
As shown in figure 11, protective layer 15 is deposited, and hot setting is carried out to protective layer 15.
The semiconductor power device that the preparation method provided through the invention obtains anti-breakdown voltage with higher and compared with
Strong anti-Interface electric field interference performance.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (14)
1. a kind of semiconductor power device, which is characterized in that including substrate, first oxygen layer, the first offset field plate and the second biased field
Plate, the inner side surface of the substrate are formed with field limiting ring, and the just oxygen layer is located at the outer side surface of the substrate, and described first partially
The head end for moving field plate is electrically coupled with the field limiting ring, and the ring outside direction of tail end towards the field limiting ring of first offset field plate is inclined
It moves, second offset field plate is between first offset field plate and the field limiting ring, first offset field plate and institute
It states the second offset field plate to be electrically coupled, and second offset field plate and the substrate are obstructed by the just oxygen layer to be formed with first
Capacitive region, the tail end of first offset field plate extends second offset field plate, and first offset field plate is extended
The second capacitive region is formed between the part and the substrate of second offset field plate, first capacitor area unit area
Capacitor is greater than the capacitor of second capacitive region unit area.
2. semiconductor power device according to claim 1, which is characterized in that the semiconductor power device further includes exhausted
Edge dielectric layer, the insulating medium layer are covered in the just oxygen layer and second offset field plate, first offset field plate
On the insulating medium layer, it is provided on the insulating medium layer for first offset field plate and second offset field plate
The first contact hole for being electrically coupled and the second contact hole being electrically coupled for first offset field plate and the field limiting ring, described the
At two capacitive regions, obstructed between first offset field plate and the substrate by the just oxygen layer and the insulating medium layer.
3. semiconductor power device according to claim 2, which is characterized in that the semiconductor power device further includes blunt
Change layer, the passivation layer is located on the insulating medium layer, is formed between the tail end and the substrate of first offset field plate
There is third capacitive region, the capacitor of second capacitive region unit area is greater than the capacitor of third capacitive region unit area, institute
It states third capacitive region and is located at the side that second capacitive region deviates from the first capacitor area, at the third capacitive region, institute
It states and is obstructed between the first offset field plate and the substrate by just oxygen layer, the insulating medium layer and the passivation layer.
4. semiconductor power device according to claim 3, which is characterized in that the passivation layer includes ramp peace
Whole, the third capacitive region includes the 4th capacitive region and the 5th capacitive region, and the 4th capacitive region is located at second capacitor
Between area and the 5th capacitive region, the capacitor of second capacitive region unit area is greater than the electricity of the 4th capacitive region unit area
Hold, the capacitor of the 4th capacitive region unit area is greater than the capacitor of the 5th capacitive region unit area；
At the 4th capacitive region, it is situated between first offset field plate and the substrate by the just oxygen layer, the insulation
Matter layer and ramp barrier；
At the 5th capacitive region, it is situated between first offset field plate and the substrate by the just oxygen layer, the insulation
Matter layer and evener barrier.
5. semiconductor power device according to claim 3 or 4, which is characterized in that be formed with multiple institutes on the substrate
Field limiting ring is stated, multiple field limiting rings are arranged concentrically from the inside to the outside, corresponding, first offset field plate, second offset
Field plate and the passivation layer are also multiple, multiple first offset field plates, multiple second offset field plates, multiple passivation layers and multiple
Field limiting ring is arranged in a one-to-one correspondence, and the tail end of the first internally positioned offset field plate is extended to positioned at the first external offset field plate
Head end, and by described blunt between the tail end of the first internally positioned offset field plate and the head end of the first offset field plate positioned at outside
Change layer barrier.
6. semiconductor power device according to claim 1, which is characterized in that the semiconductor power device further includes
Three offset field plates and the 4th offset field plate, the inner side surface of the substrate are formed with cut-off ring, and the cut-off ring and the field limit
Ring is arranged concentrically, and the cut-off ring is located at the outside of the field limiting ring, the head end of the third offset field plate and the cut-off
Ring is electrically coupled, and the tail end of the third offset field plate is deviated towards direction in the ring of the cut-off ring, the 4th offset field plate position
Between the third offset field plate and the cut-off ring, the third offset field plate and the 4th offset field plate are electrically coupled,
And the 4th offset field plate and the substrate are obstructed by the just oxygen layer, the tail end of the third offset field plate extends described
4th offset field plate.
7. semiconductor power device according to claim 6, which is characterized in that first offset field plate and the third
Offset field plate is that metal contacts field plate, and second offset field plate and the 4th offset field plate are polysilicon field plate.
8. semiconductor power device according to claim 1, which is characterized in that the semiconductor power device further includes protecting
Sheath, the protective layer are covered in outside first offset field plate.
9. the preparation method of the semiconductor power device as described in claim 1~8 any one, which is characterized in that including with
Lower step:
Substrate is provided, just oxygen layer has been formed on the substrate；
It opens field limiting ring region on substrate by chemical wet etching, field is formed in the inner side surface of substrate by ion implanting and is limited
Ring, in the long oxide layer of boiler tube knot；
Deposit polycrystalline silicon on substrate is doped polysilicon, and carries out chemical wet etching to polysilicon, forms the second biased field
Plate；
Chemical wet etching forms contact hole, and splash-proofing sputtering metal layer carries out chemical wet etching to metal layer, forms the first offset field plate.
10. the preparation method of semiconductor power device according to claim 9, which is characterized in that the substrate is silicon lining
Bottom forms the first oxygen layer of silica by thermal oxide on the silicon substrate.
11. the preparation method of semiconductor power device according to claim 9, which is characterized in that described " to sink on substrate
Before product polysilicon " further include:
Open cut-off ring region on substrate by chemical wet etching, the inner side surface by ion implanting in substrate forms cut-off
Ring, the cut-off ring are located at the outside of the field limiting ring.
12. the preparation method of semiconductor power device according to claim 11, which is characterized in that deviated in formation second
The 4th offset field plate is formed while field plate, and third offset field plate is formed while forming the first offset field plate.
13. the preparation method of semiconductor power device according to claim 9, which is characterized in that " the chemical wet etching shape
At contact hole " before further include:
Silica is deposited on substrate, forms insulating medium layer, and the insulating medium layer covers second biased field simultaneously
Plate and the just oxygen layer；
Boron-phosphorosilicate glass is deposited on insulating medium layer, and chemical wet etching is carried out to boron-phosphorosilicate glass, obtains passivation layer.
14. the preparation method of semiconductor power device according to claim 9, which is characterized in that described " to form first partially
Move field plate " after further include:
Protective layer is deposited, and hot setting is carried out to protective layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178104A (en) * | 2013-02-20 | 2013-06-26 | 国网智能电网研究院 | Semiconductor device multistage field plate terminal structure and manufacturing method thereof |
| CN105185829A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and manufacturing method thereof |
| US20170338335A1 (en) * | 2016-05-19 | 2017-11-23 | Rohm Co., Ltd. | High-speed diode and method for manufacturing the same |
-
2017
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178104A (en) * | 2013-02-20 | 2013-06-26 | 国网智能电网研究院 | Semiconductor device multistage field plate terminal structure and manufacturing method thereof |
| CN105185829A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and manufacturing method thereof |
| US20170338335A1 (en) * | 2016-05-19 | 2017-11-23 | Rohm Co., Ltd. | High-speed diode and method for manufacturing the same |
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