CN101620996A - Method for preparing gate oxidation layer - Google Patents
Method for preparing gate oxidation layer Download PDFInfo
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- CN101620996A CN101620996A CN200810135916A CN200810135916A CN101620996A CN 101620996 A CN101620996 A CN 101620996A CN 200810135916 A CN200810135916 A CN 200810135916A CN 200810135916 A CN200810135916 A CN 200810135916A CN 101620996 A CN101620996 A CN 101620996A
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Abstract
The invention provides a method for preparing a gate oxidation layer, including the following steps: a first nitride layer is precipitated on a pad oxidation layer on the surface of a substrate; the first nitride layer is used as a hard mask layer to etch the nitride layer and the substrate, thereby forming a deep groove with predetermined thickness; a second nitride layer is precipitated; the second nitride layer on the bottom of the deep groove is removed by etching, and a bottom oxide layer is formed on the bottom of the deep groove; the nitride layer on the pad oxidation layer and the nitride layer in the groove are removed by etching; and a gate oxide layer is formed on the upper surface of the formed structure. The gate oxidation layer prepared by adopting the method of the invention can increase the thickness of the oxidation layer on the bottom of the groove of a transistor, and can reduce the gate charge-discharge capacitance, without influencing other electrical parameters of the transistor.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly a kind of manufacture method of gate oxide.
Background technology
In order to improve the switch switch speed of groove type power transistor, make it have higher operating frequency and the minimizing switch cost (Switching Loss) that switch motion caused, in the present manufacturing technology, usually requiring is not influencing under other electrical parameters of transistor, reduces the quantity of electric charge (Qg) that grid charges and discharge electric capacity as far as possible.Groove type power transistor manufacturing process of the prior art, generally be to use oxide layer as hard mask layer, go out the zone of groove by lithographic definition, adopt the method for dry ecthing to form groove then, form grid oxic horizon via the furnace oxidation growth again, oxide layer channel bottom of Xing Chenging and sidewall thickness are basically identicals like this.As shown in Figure 1, in the semiconductor device structure that the polysilicon 16 by N+ substrate 11, N-epitaxial loayer 12, source electrode ion district 13,14, grid oxic horizon 15 and doping PH3 constitutes, the thickness of grid oxide layer of channel bottom and sidewall is consistent.But for the groove type power transistor manufacturing process, wishing increases the channel bottom thickness of oxide layer under situation about not increasing as the trenched side-wall thickness of oxide layer of grid oxic horizon, realize reducing the purpose that grid charges and discharge electric capacity.
Summary of the invention
In view of above-mentioned, propose now a kind of can be under the situation that does not increase the trenched side-wall oxidated layer thickness, reduce the purpose that grid charges and discharge electric capacity by the channel bottom oxidated layer thickness is increased.
The present invention proposes a kind of manufacture method of gate oxide, may further comprise the steps:
Step 1, on the bed course oxide layer of substrate surface the deposition first nitride layer;
Step 2, form as this nitride layer of curtain layer of hard hood etching and substrate with this first nitride layer and to have the deep trench of predetermined thickness;
Step 3, deposit second nitride layer again;
Second nitride layer of deep trench bottom is removed in step 4, etching, then forms bottom oxide layer in the deep trench bottom;
Nitride layer and the interior nitride layer of groove on the bed course oxide layer removed in step 5, etching;
Step 6, the structure upper surface that forms in step 5 form gate oxide level.
As preferably, the thickness of above-mentioned first nitride layer is greater than above-mentioned bed course oxide layer.
As preferably, the thickness of above-mentioned second nitride layer is less than above-mentioned first nitride layer.
As preferably, the thickness of the oxide skin(coating) in the step 4 is greater than gate oxide.
As preferably, above-mentioned substrate comprises the N+ substrate, N-epitaxial loayer, and the source electrode that constitutes of the well region that constitutes of P-ion and N+ ion.
As preferably, comprise in the above-mentioned steps 2 and at first utilize photoetching or engraving method definition deep trench zone, etch the scope in deep trench zone, then utilize the dry etching method etching to form deep trench.
As preferably, utilize dry etching method to remove second nitride layer of deep trench bottom in the step 4.
As preferably, utilize Wet-type etching method to remove nitride layer in the step 5.
As preferably, comprise in the above-mentioned steps 6:
Step 60, the bed course oxide layer is removed in etching;
Step 61 forms layer of oxide layer, and this oxide layer is a sacrificial oxide layer;
Step 62, sacrificial oxide layer is removed in etching;
Step 63 forms gate oxide.
As preferably, above-mentioned sacrificial oxide layer and gate oxide pass through all that oxidation growth forms in boiler tube.
Adopt method of the present invention to make gate oxide the oxidated layer thickness of transistorized channel bottom is increased, reduce grid and charge and discharge electric capacity, and do not influence transistorized other electrical parameters.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.
Description of drawings
Figure 1A is for adopting the transistor device generalized section of existing technology.
The transistor device generalized section of Figure 1B for adopting manufacture method of the present invention to form.
Fig. 2-Figure 11 is the schematic diagram of device in formed each stage of manufacture method of the gate oxide of a preferred embodiment of the present invention.
Embodiment
Be described in further detail below in conjunction with the manufacture method of the drawings and specific embodiments gate oxide of the present invention.
The device architecture that utilizes method manufacturing of the present invention to form can be shown in Figure 1B, comprising polysilicon 36 by N+ substrate 2, N-epitaxial loayer 12, source electrode ion district 33,34, grid oxic horizon 35 and doping PH3, also can be other similar or different structures, as long as bottom oxidization layer is thicker than sidewall oxide.
The manufacture method of a kind of gate oxide of a preferred embodiment of the present invention may further comprise the steps shown in Fig. 2-11:
Step 1, by substrate 21, epitaxial loayer 22, the substrate surface that bed course oxide layer 23 constitutes deposits first nitride layer 24, form structure as shown in Figure 2, first nitride layer 24 can be a silicon nitride layer, also can be that other suitable nitride constitute, wherein the thickness of first nitride layer 24 is greater than the thickness of bed course oxide layer 23, substrate 21 can be N+ or N-substrate, also can be other suitable substrates, epitaxial loayer 22 can be N-or N+ epitaxial loayer, also can be other suitable epitaxial loayers, bed course oxide layer 23 belows can also have the source electrode ion of injection, and for example the N+ ion to be constituting source electrode, thereby finally forms the dependency structure device.
Step 2, with first nitride layer 24 as curtain layer of hard hood, the suprabasil bed course oxide layer 23 of photoetching/etching, define the scope of trench region, form structure as shown in Figure 3, then adopt dry etching method, epitaxial loayer 22 is carried out etching, formation has the deep trench of predetermined thickness, form structure as shown in Figure 4, the thickness of this deep trench can determine as required, can certainly adopt the engraving method of other types to finish.
Step 3, deposit one deck second nitride layer again, it for example is silicon nitride layer, the thickness of second nitride layer is less than first nitride layer 24, form structure as shown in Figure 5, in the present embodiment, this first nitride layer is identical with the material of second nitride layer, it for example all is silicon nitride, so it is among the figure that its expression is as a whole, represent that with 25 this moment, the sidewall and the bottom of groove also deposited one deck nitride layer, and trenched side-wall equates with the nitride layer thickness of bottom, and the thickness of the nitride layer on the bed course oxide layer 23 is this first nitride layer and the second nitride layer sum, and thickness is thicker.
Second nitride layer in the deep trench is removed in step 4, etching, form structure as shown in Figure 6, general second nitride layer that adopts in dry etching method removal devices surface portion second nitride layer and the deep trench in this step, because the anisotropic of dry etching method, so still there is silicon nitride layer in the deep trench sidewall, have only channel bottom to expose epitaxial film materials.
Step 5, then this device is sent into boiler tube, furnace tubing reaches oxidizing temperature, bottom oxide layer 26 is formed on the deep trench bottom that acts on device by oxygen, form structure as shown in Figure 7, bottom oxide layer 26 for example is a silicon oxide layer, by the time decision of aerating oxygen and heating, generally speaking, the thickness of this oxide skin(coating) is greater than the gate oxide level that will generate as required for concrete thickness.
Step 6, utilize the Wet-type etching method etching to remove the nitride layer on the bed course oxide layer and the nitride layer of deep trench sidewall, all nitride are removed in etching this time as far as possible, form structure as shown in Figure 8.
Step 7, utilize the method for wet etching that the pad oxide of structure shown in Figure 8 is removed, then form layer of oxide layer at the structure upper surface that forms, the formation method that the formation method can be led to bottom oxide layer recited above is identical, form by oxidation growth in boiler tube, this oxide layer forms sacrificial oxide layer 27, as shown in Figure 9, and after etching is removed sacrificial oxide layer 27 and residual polysilicon, the also etched removal part of bottom oxidization layer, only stay the part bottom oxidization layer, as shown in figure 10, then again via furnace oxidation growth grid oxic horizon, form structure as shown in figure 11, because the oxide layer of deep trench bottom just exists originally, the oxide layer of deep trench bottom is more many than the oxidation bed thickness of deep trench sidewall in this structure, so just can not increase under the situation as the deep trench sidewall oxidation layer thickness of gate oxide the thickness of increase deep trench bottom oxidization layer.Thereby reach not influencing under other electrical parameters of transistor, reduce the purpose that grid charges and discharge the quantity of electric charge of electric capacity as far as possible.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (10)
1, a kind of manufacture method of gate oxide is characterized in that may further comprise the steps:
Step 1, on the bed course oxide layer of substrate surface the deposition first nitride layer;
Step 2, form as this nitride layer of curtain layer of hard hood etching and substrate with this first nitride layer and to have the deep trench of predetermined thickness;
Step 3, deposit second nitride layer again;
Second nitride layer of deep trench bottom is removed in step 4, etching, then forms bottom oxidization layer in the deep trench bottom;
Nitride layer and the interior nitride layer of groove on the bed course oxide layer removed in step 5, etching;
Step 6, the structure upper surface that forms in step 5 form gate oxide layers.
2, the manufacture method of a kind of gate oxide according to claim 1, the thickness that it is characterized in that above-mentioned first nitride layer is greater than above-mentioned bed course oxide layer.
3, the manufacture method of a kind of gate oxide according to claim 1 and 2, the thickness that it is characterized in that above-mentioned second nitride layer is less than above-mentioned first nitride layer.
4, the manufacture method of a kind of gate oxide according to claim 1 is characterized in that the thickness of the thickness of the bottom oxidization layer in the step 4 greater than the gate oxide that forms in the step 6.
5, the manufacture method of a kind of gate oxide according to claim 1 is characterized in that above-mentioned substrate comprises the N+ substrate, N-epitaxial loayer, and the source electrode of the well region of P-ion formation and N+ ion formation.
6, the manufacture method of a kind of gate oxide according to claim 1, it is characterized in that comprising in the above-mentioned steps 2 and at first utilize photoetching or engraving method definition deep trench zone, etch the scope in deep trench zone, then utilize the dry etching method etching to form deep trench.
7, the manufacture method of a kind of gate oxide according to claim 1 is characterized in that utilizing in the step 4 dry etching method to remove second nitride layer of deep trench bottom.
8, the manufacture method of a kind of gate oxide according to claim 1 is characterized in that utilizing in the step 5 Wet-type etching method to remove nitride layer.
9, the manufacture method of a kind of gate oxide according to claim 1 is characterized in that comprising in the above-mentioned steps 6:
Step 60, the bed course oxide layer is removed in etching;
Step 61 forms layer of oxide layer, and this oxide layer is a sacrificial oxide layer;
Step 62, sacrificial oxide layer is removed in etching;
Step 63 forms gate oxide.
10, the manufacture method of a kind of gate oxide according to claim 9 is characterized in that above-mentioned sacrificial oxide layer and gate oxide all pass through oxidation growth formation in boiler tube.
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| CN200810135916A CN101620996B (en) | 2008-07-03 | 2008-07-03 | Method for preparing gate oxidation layer |
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| CN200810135916A CN101620996B (en) | 2008-07-03 | 2008-07-03 | Method for preparing gate oxidation layer |
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| CN101620996B CN101620996B (en) | 2012-10-10 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937840A (en) * | 2010-09-10 | 2011-01-05 | 上海宏力半导体制造有限公司 | Method for forming grid oxide layer |
| WO2011143836A1 (en) * | 2010-05-21 | 2011-11-24 | 香港商莫斯飞特半导体有限公司 | Method for manufacturing trench with thick insulating bottom and semiconductor device thereof |
| CN102005373B (en) * | 2009-08-28 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of grid electrode and power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
| CN103137482A (en) * | 2011-11-29 | 2013-06-05 | 和舰科技(苏州)有限公司 | Method of reducing V-shaped groove at top end of polycrystalline silicon inside groove of groove-type power transistor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411553B (en) * | 1999-08-04 | 2000-11-11 | Mosel Vitelic Inc | Method for forming curved oxide on bottom of trench |
| US6437386B1 (en) * | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
| CN100461342C (en) * | 2005-04-18 | 2009-02-11 | 力晶半导体股份有限公司 | Formation of slotted grid dielectric layer |
| US7807576B2 (en) * | 2008-06-20 | 2010-10-05 | Fairchild Semiconductor Corporation | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
-
2008
- 2008-07-03 CN CN200810135916A patent/CN101620996B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005373B (en) * | 2009-08-28 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of grid electrode and power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
| WO2011143836A1 (en) * | 2010-05-21 | 2011-11-24 | 香港商莫斯飞特半导体有限公司 | Method for manufacturing trench with thick insulating bottom and semiconductor device thereof |
| CN101937840A (en) * | 2010-09-10 | 2011-01-05 | 上海宏力半导体制造有限公司 | Method for forming grid oxide layer |
| CN101937840B (en) * | 2010-09-10 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | Method for forming grid oxide layer |
| CN103137482A (en) * | 2011-11-29 | 2013-06-05 | 和舰科技(苏州)有限公司 | Method of reducing V-shaped groove at top end of polycrystalline silicon inside groove of groove-type power transistor |
| CN103137482B (en) * | 2011-11-29 | 2015-08-05 | 和舰科技(苏州)有限公司 | Reduce the method for polysilicon top V-type groove in groove type power transistor groove |
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| CN101620996B (en) | 2012-10-10 |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |