CN103137482B - Reduce the method for polysilicon top V-type groove in groove type power transistor groove - Google Patents
Reduce the method for polysilicon top V-type groove in groove type power transistor groove Download PDFInfo
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- CN103137482B CN103137482B CN201110386845.5A CN201110386845A CN103137482B CN 103137482 B CN103137482 B CN 103137482B CN 201110386845 A CN201110386845 A CN 201110386845A CN 103137482 B CN103137482 B CN 103137482B
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Abstract
The invention discloses a kind of method reducing polysilicon top V-type groove in groove type power transistor groove, it comprises the following steps: on power transistor, form groove; In groove, deposit spathic silicon is to form grid, forms V-type groove on polysilicon top simultaneously; Then at the polysilicon of upper surface deposition for filling V-type groove of grid; The polysilicon of final etch deposition has formed the less V-type groove of cup depth.The present invention can reduce the V-type groove cup depth on polysilicon top greatly, reach and to reduce above grid Cont resistance and prevent Cont from cannot connect grid and cause switching device to lose efficacy, it can be widely used in the formation of groove type power transistor groove inner grid.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of method reducing polysilicon top V-type groove in groove type power transistor groove.
Background technology
At present, power transistor is widely used in high-power switch device, and this kind of device generally adopts vertical conductive structure.In the physical structure of device, slot type structure is a kind of typical structure wherein, and is widely used.
The grid of groove type power transistor is positioned at groove, when forming grid, needs to fill polysilicon in groove.In traditional handicraft, polysilicon deposition thickness is about 6K.Because groove very dark (degree of depth > 1.0um), therefore after polysilicon filling groove, the height in the horizontal direction of the polysilicon top end face in groove is lower than source electrode.After polysilicon etch process, in groove, polysilicon surface then forms the V-type groove of depression, and groove width is wider, and V-type geosynclinal concave falls into more serious.This V-type groove can affect switching device leakage current, increase Cont (contactor) resistance above grid, and then affect switching speed and the power consumption of switching device, above grid, ILD (inner layer dielectric layer) thickness can increase along with the depression of V-type groove and increase simultaneously, this situation can reduce Cont etch process window, after depression acquires a certain degree, ILD thickness more likely can be made too thick and cannot etch clean, so that Cont well cannot be connected to grid, switching device is caused to lose efficacy.
Have two kinds of improving technique that can solve the problem at present: the first increases polysilicon deposition thickness (about 10K), but this technique is while increase cost, effect is not remarkable; The second is before polysilicon etch, increase by a step polysilicon CMP (Chemical MechanicalPolishing, cmp) processing procedure, this processing procedure makes the polysilicon in groove and the polysilicon above source electrode almost be in same level position, obviously can improve V-groove during etching, but polysilicon CMP cost is higher.
Summary of the invention
For the problems referred to above, the object of this invention is to provide that a kind of cost is low, the method for polysilicon top V-type groove in the reduction groove type power transistor groove of Be very effective.
For achieving the above object, the present invention adopts following technical scheme:
Reduce a method for polysilicon top V-type groove in groove type power transistor groove, comprise the following steps:
Step 1 a: substrate is provided, described upper surface of substrate is provided with epitaxial loayer, and described epitaxial loayer upper surface is provided with bed course oxide layer, and described bed course oxide layer upper surface is provided with curtain layer of hard hood;
Step 2: adopt photoetching to define trench region on described curtain layer of hard hood; Then adopt in the described bed course oxide layer below the trench region being etched in and being positioned at described curtain layer of hard hood and continue definition groove;
Step 3: on the groove basis that described step 2 is finally formed, adopt the groove described epitaxial loayer being etched in the beneath trenches being positioned at described bed course oxide layer being formed and is used as grid further;
Step 4: be used as, on the groove basis of grid, to remove described curtain layer of hard hood in the formation of described step 3;
Step 5: on the basis of described step 4, arranges grid oxic horizon at the upper surface of described epitaxial loayer; Then the polysilicon of filling groove is used in the upper surface deposition of described grid oxic horizon;
Step 6: to etch in described step 5 for the polysilicon of filling groove to form grid, polysilicon top forms V-type groove in groove simultaneously;
Step 7: the polysilicon of upper surface deposition for filling V-type groove of the grid formed on the basis of described step 6;
Step 8: etch the polysilicon of deposition in described step 7 to form grid.
Further, described substrate is N+ substrate, and described epitaxial loayer is N-epitaxial loayer.
Further, the curtain layer of hard hood of described bed course oxide layer adopts the method for chemical vapour deposition (CVD) to be formed.
Further, the concrete grammar of lithographic definition trench region in described step 2, is adopted to be: to be coated on described curtain layer of hard hood by photoresist, and patterned trench region, make to corrode described curtain layer of hard hood with photoresist, described curtain layer of hard hood defines trench region.
Further, in described step 5, the polysilicon thickness of deposition is 6K.
Further, in described step 7, the polysilicon thickness of deposition is 3K.
Further, after completing described step 8, repeating said steps 7 and described step 8 can also be continued.
The present invention adopts above technical scheme, and it has the following advantages: the present invention, on traditional handicraft basis, increases the deposition of a polysilicon, namely after first time, polysilicon etch completed, then deposits one deck polysilicon filling V-type groove, and then etches.The present invention can reduce the cup depth of V-type groove greatly, and reach and to reduce above grid Cont resistance and prevent Cont from cannot connect grid and cause switching device to lose efficacy, it can be widely used in the formation of groove type power transistor groove inner grid.
Accompanying drawing explanation
Fig. 1 to Fig. 6 be in traditional handicraft in groove type power transistor deposit spathic silicon to form the processing step flow chart of grid.
Fig. 7 to Fig. 8 is the processing step flow chart that the present invention reduces polysilicon top V-type groove in groove type power transistor groove in traditional handicraft.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Fig. 1 ~ Fig. 8, the invention provides a kind of method reducing polysilicon top V-type groove in groove type power transistor groove, comprise the following steps:
Step 1: as shown in Figure 1, the invention provides a substrate 1, surface is provided with epitaxial loayer 2 on the base 1, and epitaxial loayer 2 upper surface is provided with bed course oxide layer 3, and bed course oxide layer 3 upper surface is provided with curtain layer of hard hood 4; In the present embodiment, substrate 1 is N+ substrate, and epitaxial loayer 2 is N-epitaxial loayer.
Step 2: as shown in Figure 2, adopts photoetching to define trench region 41 on curtain layer of hard hood 4; Then adopt in 4 bed course oxide layers 3 below the trench region being etched in and being positioned at curtain layer of hard hood 4 and continue definition groove 31; In the present embodiment, the concrete grammar of employing lithographic definition trench region 41 is: be coated in by photoresist on curtain layer of hard hood 4, and patterned trench region 41, make to corrode curtain layer of hard hood 4 with photoresist, curtain layer of hard hood 4 defines trench region 41.
Step 3: as shown in Figure 3, on the groove basis that step 2 is finally formed, adopts the groove 21 epitaxial loayer 2 be etched in below the groove 31 being positioned at bed course oxide layer 3 being formed and is used as grid further;
Step 4: as shown in Figure 4, is used as, on groove 21 basis of grid, to remove curtain layer of hard hood 4 in the formation of step 3;
Step 5: as shown in Figure 5, on the basis of step 4, arranges grid oxic horizon 5 at the upper surface of epitaxial loayer 2; Then the polysilicon 6 of filling groove is used in the upper surface deposition of grid oxic horizon 5; The polysilicon thickness deposited in this step is 6K;
Step 6: as shown in Figure 6, in etching step 5 for the polysilicon 6 of filling groove to form grid, simultaneously in groove, polysilicon top forms V-type groove 7;
Step 7: as shown in Figure 7, the polysilicon 6 of upper surface deposition for filling V-type groove 7 of the grid that the basis of step 6 is formed; The polysilicon thickness deposited in this step is 3K;
Step 8: as shown in Figure 8, in etching step 7, the polysilicon 6 of deposition is to form grid.
Curtain layer of hard hood 4 above bed course oxide layer 3 of the present invention preferably adopts the method for chemical vapour deposition (CVD) to be formed.
As a kind of preferred version, after completing described step 8, repeating said steps 7 and described step 8 can also be continued, until the cup depth making V-type groove reaches minimum.
To sum up, the present invention adopts and in groove type power transistor groove, polysilicon top V-type groove continues again deposition polysilicon on the basis of traditional handicraft, namely after first time, polysilicon etch completed, then deposit one deck polysilicon filling V-type groove, and then etch.Relative to the top V-type groove cup depth of the polysilicon formed in traditional handicraft, the cup depth of the V-type groove adopting processing step of the present invention to obtain reduces greatly, reaches the object reducing Cont resistance above grid and prevent Cont from cannot connect grid and cause switching device to lose efficacy.
The foregoing is only preferred embodiment of the present invention, be not used for limiting practical range of the present invention; If do not depart from the spirit and scope of the present invention, the present invention is modified or equivalent to replace, in the middle of the protection range that all should be encompassed in the claims in the present invention.
Claims (5)
1. reduce a method for polysilicon top V-type groove in groove type power transistor groove, it is characterized in that, comprise the following steps:
Step 1 a: substrate is provided, described upper surface of substrate is provided with epitaxial loayer, and described epitaxial loayer upper surface is provided with bed course oxide layer, and described bed course oxide layer upper surface is provided with curtain layer of hard hood;
Step 2: adopt photoetching to define trench region on described curtain layer of hard hood; Then adopt in the described bed course oxide layer below the trench region being etched in and being positioned at described curtain layer of hard hood and continue definition groove;
Step 3: on the groove basis that described step 2 is finally formed, adopt the groove described epitaxial loayer being etched in the beneath trenches being positioned at described bed course oxide layer being formed and is used as grid further;
Step 4: be used as, on the groove basis of grid, to remove described curtain layer of hard hood in the formation of described step 3;
Step 5: on the basis of described step 4, arranges grid oxic horizon at the upper surface of described epitaxial loayer; Then the polysilicon of filling groove is used in the upper surface deposition of described grid oxic horizon;
Step 6: to etch in described step 5 for the polysilicon of filling groove to form grid, polysilicon top forms V-type groove in groove simultaneously;
Step 7: the polysilicon of upper surface deposition for filling V-type groove of the grid formed on the basis of described step 6;
Step 8: etch the polysilicon of deposition in described step 7 to form grid.
2. the method for polysilicon top V-type groove in reduction groove type power transistor groove according to claim 1, it is characterized in that, described substrate is N+ substrate, and described epitaxial loayer is N-epitaxial loayer.
3. the method for polysilicon top V-type groove in reduction groove type power transistor groove according to claim 1, is characterized in that, the curtain layer of hard hood of described bed course oxide layer adopts the method for chemical vapour deposition (CVD) to be formed.
4. the method for polysilicon top V-type groove in reduction groove type power transistor groove according to claim 1, it is characterized in that, the concrete grammar of lithographic definition trench region is adopted to be in described step 2: to be coated in by photoresist on described curtain layer of hard hood, and patterned trench region, use photoetching process to define trench region on described curtain layer of hard hood.
5. in the reduction groove type power transistor groove according to claim 1 or 2 or 3 or 4, the method for polysilicon top V-type groove, is characterized in that, after completing described step 8, can also continue repeating said steps 7 and described step 8.
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| CN101620996A (en) * | 2008-07-03 | 2010-01-06 | 和舰科技(苏州)有限公司 | Method for preparing gate oxidation layer |
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
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| US5723376A (en) * | 1994-06-23 | 1998-03-03 | Nippondenso Co., Ltd. | Method of manufacturing SiC semiconductor device having double oxide film formation to reduce film defects |
| CN101924130A (en) * | 2009-06-09 | 2010-12-22 | 上海韦尔半导体股份有限公司 | Grooved MOSFET with grooved contact hole and preparation method thereof |
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| JPH0870124A (en) * | 1994-06-23 | 1996-03-12 | Nippondenso Co Ltd | Fabrication of silicon carbide semiconductor device |
| US6265269B1 (en) * | 1999-08-04 | 2001-07-24 | Mosel Vitelic Inc. | Method for fabricating a concave bottom oxide in a trench |
| TW578238B (en) * | 2001-10-19 | 2004-03-01 | Infineon Technologies Ag | A method of forming a silicon dioxide layer |
| CN101330037A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing isolation of shallow channel |
| CN101620996A (en) * | 2008-07-03 | 2010-01-06 | 和舰科技(苏州)有限公司 | Method for preparing gate oxidation layer |
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
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