CN103137482A - Method of reducing V-shaped groove at top end of polycrystalline silicon inside groove of groove-type power transistor - Google Patents
Method of reducing V-shaped groove at top end of polycrystalline silicon inside groove of groove-type power transistor Download PDFInfo
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- CN103137482A CN103137482A CN2011103868455A CN201110386845A CN103137482A CN 103137482 A CN103137482 A CN 103137482A CN 2011103868455 A CN2011103868455 A CN 2011103868455A CN 201110386845 A CN201110386845 A CN 201110386845A CN 103137482 A CN103137482 A CN 103137482A
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Abstract
The invention discloses a method of reducing a V-shaped groove at the top end of polycrystalline silicon inside a groove of a groove-type power transistor. The method comprises a first step of forming the groove on the power transistor, depositing the polycrystalline silicon inside the groove to form a grid and form the V-shaped groove at the top end of the polycrystalline silicon at the same time, depositing the polycrystalline silicon used for filling the V-shaped groove on the upper surface of the grid, and the etched and deposited polycrystalline silicon forming the V-shaped groove with a small depth. The method can greatly reduce the depth of the V-shaped groove at the top end of the polycrystalline silicon, reduce contactor (Cont) resistance on the grid, and prevent a switch component from losing effectiveness because the Cont resistance can not be connected with the grid. The method can be widely applied to forming of the grid inside the groove of the groove-type power transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of method that reduces polysilicon top V-type groove in the groove type power transistor groove.
Background technology
At present, power transistor is widely used in high-power switch device, and this kind device generally adopts vertical conductive structure.Aspect the physical structure of device, slot type structure is a kind of typical structure wherein, and is widely used.
The grid of groove type power transistor is positioned at groove, when forming grid, need to fill polysilicon in groove.In traditional handicraft, polysilicon deposition thickness is about 6K.Because the very dark (degree of depth＞1.0um), so after the polysilicon filling groove, the polysilicon top end face height in the horizontal direction in groove is lower than source electrode of groove.After the polysilicon etch process, in groove, polysilicon surface forms the V-type groove of depression, and groove width is wider, and the V-type geosynclinal concave falls into more serious.This V-type groove can affect the switching device leakage current, increase Cont (contactor) resistance of grid top, and then affect switching speed and the power consumption of switching device, grid top ILD (inner layer dielectric layer) thickness can increase along with the depression of V-type groove and increase simultaneously, this situation can be dwindled Cont etch process window, after depression acquires a certain degree, more likely can make ILD thickness too thick and can't etching clean, so that Cont can't well be connected to grid, causes switching device to lose efficacy.
Two kinds of improvement techniques that can address the above problem are arranged at present: the first is to increase polysilicon deposition thickness (approximately 10K), but this technique is when increasing cost, and effect is not remarkable; The second is before the polysilicon etching, increase by a step polysilicon CMP (Chemical Mechanical Polishing, cmp) processing procedure, this processing procedure makes polysilicon and the polysilicon above source electrode in groove almost be in the same level position, can obviously improve V-groove during etching, but polysilicon CMP cost is higher.
Summary of the invention
For the problems referred to above, the purpose of this invention is to provide a kind of method that cost is low, effect reduces polysilicon top V-type groove in the groove type power transistor groove significantly.
For achieving the above object, the present invention adopts following technical scheme:
A kind of method that reduces polysilicon top V-type groove in the groove type power transistor groove comprises the following steps:
Step 1: a substrate is provided, and described upper surface of substrate is provided with epitaxial loayer, and described epitaxial loayer upper surface is provided with the bed course oxide layer, and described bed course oxide layer upper surface is provided with curtain layer of hard hood;
Step 2: adopt photoetching to define trench region on described curtain layer of hard hood; Then adopt on the described bed course oxide layer be etched in the trench region below that is positioned at described curtain layer of hard hood and continue the definition groove;
Step 3: on the described step 2 final groove basis that forms, further adopt the groove that forms on the described epitaxial loayer that is etched in the beneath trenches that is positioned at described bed course oxide layer as grid;
Step 4: on the formation of the described step 3 groove basis as grid, remove described curtain layer of hard hood;
Step 5: on the basis of described step 4, at the upper surface of described epitaxial loayer, grid oxic horizon is set; Then be used for the polysilicon of filling groove in the upper surface deposition of described grid oxic horizon;
Step 6: be used for the polysilicon of filling groove in the described step 5 of etching to form grid, the polysilicon top forms the V-type groove in groove simultaneously;
Step 7: the upper surface deposition of the grid that forms on the basis of described step 6 is used for filling the polysilicon of V-type groove;
Step 8: in the described step 7 of etching, the polysilicon of deposition is to form grid.
Further, described substrate is the N+ substrate, and described epitaxial loayer is the N-epitaxial loayer.
Further, the curtain layer of hard hood above described bed course oxide layer is to adopt the method for chemical vapour deposition (CVD) to form.
Further, adopt the concrete grammar of lithographic definition trench region to be in described step 2: photoresist is coated on described curtain layer of hard hood, and patterned trench to be regional, makes and corrodes with photoresist described curtain layer of hard hood, defines trench region on described curtain layer of hard hood.
Further, in described step 5, the polysilicon thickness of deposition is 6K.
Further, in described step 7, the polysilicon thickness of deposition is 3K.
Further, after completing described step 8, can also continue repeating said steps 7 and described step 8.
The present invention adopts above technical scheme, and it has the following advantages: the present invention increases the deposition of a polysilicon on the traditional handicraft basis, and namely after polysilicon etching is for the first time completed, then deposit one deck polysilicon and fill the V-type groove, and then etching.The present invention can reduce the cup depth of V-type groove greatly, reaches reduce grid top Cont resistance and prevent Cont from can't connect grid and cause switching device to lose efficacy, and it can be widely used in the formation of groove type power transistor groove inner grid.
Description of drawings
Fig. 1 to Fig. 6 be in traditional handicraft in groove type power transistor deposit spathic silicon to form the processing step flow chart of grid.
Fig. 7 to Fig. 8 is that the present invention reduces in traditional handicraft the processing step flow chart of polysilicon top V-type groove in the groove type power transistor groove.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
As Fig. 1～shown in Figure 8, the invention provides a kind of method that reduces polysilicon top V-type groove in the groove type power transistor groove, comprise the following steps:
Step 1: as shown in Figure 1, the invention provides a substrate 1, be provided with epitaxial loayer 2 at substrate 1 upper surface, be provided with bed course oxide layer 3 at epitaxial loayer 2 upper surfaces, bed course oxide layer 3 upper surfaces are provided with curtain layer of hard hood 4; In the present embodiment, substrate 1 is the N+ substrate, and epitaxial loayer 2 is the N-epitaxial loayer.
Step 2: as shown in Figure 2, adopt photoetching to define trench region 41 on curtain layer of hard hood 4; Then adopt on the 4 bed course oxide layers 3 be etched in the trench region below that is positioned at curtain layer of hard hood 4 and continue definition groove 31; In the present embodiment, adopt the concrete grammar of lithographic definition trench region 41 to be: photoresist is coated on curtain layer of hard hood 4, and patterned trench zone 41, make and corrode with photoresist curtain layer of hard hood 4, define trench region 41 on curtain layer of hard hood 4.
Step 3: as shown in Figure 3, on the step 2 final groove basis that forms, further adopt the groove 21 that forms on the epitaxial loayer 2 that is etched in groove 31 belows that are positioned at bed course oxide layer 3 as grid;
Step 4: as shown in Figure 4, on the formation of step 3 groove 21 bases as grid, remove curtain layer of hard hood 4;
Step 5: as shown in Figure 5, on the basis of step 4, at the upper surface of epitaxial loayer 2, grid oxic horizon 5 is set; Then be used for the polysilicon 6 of filling groove in the upper surface deposition of grid oxic horizon 5; The polysilicon thickness that deposits in this step is 6K;
Step 6: as shown in Figure 6, be used for the polysilicon 6 of filling groove in etching step 5 to form grid, the polysilicon top forms V-type groove 7 in groove simultaneously;
Step 7: as shown in Figure 7, the upper surface of the grid that forms on the basis of step 6 deposition is used for filling the polysilicon 6 of V-type groove 7; The polysilicon thickness that deposits in this step is 3K;
Step 8: as shown in Figure 8, in etching step 7, the polysilicon 6 of deposition is to form grid.
The curtain layer of hard hood 4 of bed course oxide layer of the present invention 3 tops is preferably to adopt the method for chemical vapour deposition (CVD) to form.
As a kind of preferred version, after completing described step 8, can also continue repeating said steps 7 and described step 8, reach minimum until make the cup depth of V-type groove.
To sum up, the present invention adopts and continuing polysilicon of deposition on the basis of traditional handicraft on the V-type groove of polysilicon top again in the groove type power transistor groove, namely after polysilicon etching is for the first time completed, then deposit one deck polysilicon and fill the V-type groove, and then etching.Top V-type geosynclinal concave with respect to the polysilicon that forms in traditional handicraft falls into the degree of depth, adopt the cup depth of the resulting V-type groove of processing step of the present invention greatly to reduce, reached and reduce grid top Cont resistance and prevent Cont from can't connect grid and the purpose that causes switching device to lose efficacy.
The above is only preferred embodiment of the present invention, is not to limit practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is modified or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (7)
1. a method that reduces polysilicon top V-type groove in the groove type power transistor groove, is characterized in that, comprises the following steps:
Step 1: a substrate is provided, and described upper surface of substrate is provided with epitaxial loayer, and described epitaxial loayer upper surface is provided with the bed course oxide layer, and described bed course oxide layer upper surface is provided with curtain layer of hard hood;
Step 2: adopt photoetching to define trench region on described curtain layer of hard hood; Then adopt on the described bed course oxide layer be etched in the trench region below that is positioned at described curtain layer of hard hood and continue the definition groove;
Step 3: on the described step 2 final groove basis that forms, further adopt the groove that forms on the described epitaxial loayer that is etched in the beneath trenches that is positioned at described bed course oxide layer as grid;
Step 4: on the formation of the described step 3 groove basis as grid, remove described curtain layer of hard hood;
Step 5: on the basis of described step 4, at the upper surface of described epitaxial loayer, grid oxic horizon is set; Then be used for the polysilicon of filling groove in the upper surface deposition of described grid oxic horizon;
Step 6: be used for the polysilicon of filling groove in the described step 5 of etching to form grid, the polysilicon top forms the V-type groove in groove simultaneously;
Step 7: the upper surface deposition of the grid that forms on the basis of described step 6 is used for filling the polysilicon of V-type groove;
Step 8: in the described step 7 of etching, the polysilicon of deposition is to form grid.
2. the method that reduces polysilicon top V-type groove in the groove type power transistor groove according to claim 1, is characterized in that, described substrate is the N+ substrate, and described epitaxial loayer is the N-epitaxial loayer.
3. the method that reduces polysilicon top V-type groove in the groove type power transistor groove according to claim 1, is characterized in that, the curtain layer of hard hood above described bed course oxide layer is to adopt the method for chemical vapour deposition (CVD) to form.
4. the method that reduces polysilicon top V-type groove in the groove type power transistor groove according to claim 1, it is characterized in that, adopt the concrete grammar of lithographic definition trench region to be in described step 2: photoresist is coated on described curtain layer of hard hood, and patterned trench is regional, make and corrode with photoresist described curtain layer of hard hood, define trench region on described curtain layer of hard hood.
5. the method that reduces polysilicon top V-type groove in the groove type power transistor groove according to claim 1, is characterized in that, in described step 5, the polysilicon thickness of deposition is 6K.
6. the method that reduces polysilicon top V-type groove in the groove type power transistor groove according to claim 1, is characterized in that, in described step 7, the polysilicon thickness of deposition is 3K.
7. according to claim 1 and 2 or 3 or 4 or the 5 or 6 described methods that reduce polysilicon top V-type groove in the groove type power transistor groove, is characterized in that, after completing described step 8, can also continue repeating said steps 7 and described step 8.
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Citations (8)
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| JPH0870124A (en) * | 1994-06-23 | 1996-03-12 | Nippondenso Co Ltd | Fabrication of silicon carbide semiconductor device |
| US5723376A (en) * | 1994-06-23 | 1998-03-03 | Nippondenso Co., Ltd. | Method of manufacturing SiC semiconductor device having double oxide film formation to reduce film defects |
| US6265269B1 (en) * | 1999-08-04 | 2001-07-24 | Mosel Vitelic Inc. | Method for fabricating a concave bottom oxide in a trench |
| TW578238B (en) * | 2001-10-19 | 2004-03-01 | Infineon Technologies Ag | A method of forming a silicon dioxide layer |
| CN101330037A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing isolation of shallow channel |
| CN101620996A (en) * | 2008-07-03 | 2010-01-06 | 和舰科技(苏州)有限公司 | Method for preparing gate oxidation layer |
| CN101924130A (en) * | 2009-06-09 | 2010-12-22 | 上海韦尔半导体股份有限公司 | Grooved MOSFET with grooved contact hole and preparation method thereof |
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
-
2011
- 2011-11-29 CN CN201110386845.5A patent/CN103137482B/en active Active
Patent Citations (8)
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| JPH0870124A (en) * | 1994-06-23 | 1996-03-12 | Nippondenso Co Ltd | Fabrication of silicon carbide semiconductor device |
| US5723376A (en) * | 1994-06-23 | 1998-03-03 | Nippondenso Co., Ltd. | Method of manufacturing SiC semiconductor device having double oxide film formation to reduce film defects |
| US6265269B1 (en) * | 1999-08-04 | 2001-07-24 | Mosel Vitelic Inc. | Method for fabricating a concave bottom oxide in a trench |
| TW578238B (en) * | 2001-10-19 | 2004-03-01 | Infineon Technologies Ag | A method of forming a silicon dioxide layer |
| CN101330037A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing isolation of shallow channel |
| CN101620996A (en) * | 2008-07-03 | 2010-01-06 | 和舰科技(苏州)有限公司 | Method for preparing gate oxidation layer |
| CN101924130A (en) * | 2009-06-09 | 2010-12-22 | 上海韦尔半导体股份有限公司 | Grooved MOSFET with grooved contact hole and preparation method thereof |
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
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