CN107978555A - The process of grid curb wall - Google Patents
The process of grid curb wall Download PDFInfo
- Publication number
- CN107978555A CN107978555A CN201711163456.XA CN201711163456A CN107978555A CN 107978555 A CN107978555 A CN 107978555A CN 201711163456 A CN201711163456 A CN 201711163456A CN 107978555 A CN107978555 A CN 107978555A
- Authority
- CN
- China
- Prior art keywords
- grid
- silicon
- curb wall
- layer
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 8
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 239000011241 protective layer Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000004224 protection Effects 0.000 claims description 5
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000006117 anti-reflective coating Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000000227 grinding Methods 0.000 abstract description 2
- 238000005234 chemical deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a kind of process of grid curb wall, comprising：Step 1, forms one layer of polysilicon, then re-forms one layer of silicon oxynitride on a silicon substrate；Step 2, photoetching offset plate figure is formed using the light shield of grid level；Then silicon oxynitride and polysilicon are performed etching, forms the grid of transistor；Form gate silicon dioxide protective layer；Step 3, deposited silicon nitride and silica；And silicon chip is generally etched, so as to form grid curb wall；The silicon oxynitride of top portions of gates is etched away again；Step 4, carries out source-drain area injection and forms cobalt silicon alloy；Etching barrier layer and contact hole dielectric layer are formed, carries out chemical mechanical grinding；Carry out contact hole etching.The grid curb wall that the present invention is formed has the grid curb wall height of higher, or, with there is thicker grid curb wall during height, so as to preferably protect grid when contact hole etching, is improving the breakdown voltage between contact hole and grid with grid.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of process of grid curb wall.
Background technology
Traditional grid curb wall technique includes：Step 1: one layer of polysilicon of chemical vapor deposition is utilized on a silicon substrate, so
Afterwards photoetching offset plate figure is formed using the light shield of grid level；Then polysilicon is performed etching, forms the grid of transistor；Step
2nd, rapid thermal annealing or boiler tube are carried out to grid, so as to form gate silicon dioxide protective layer；Step 3: then utilize low pressure
The method deposited silicon nitride and silica of chemical deposition；And silicon chip is generally etched, so as to form grid curb wall；Use again
Wet etching falls the silica with top portions of gates on grid curb wall；Step 4: then to transistor carry out source-drain electrode implantation and
Cobalt alloy.
In traditional grid curb wall, as shown in Figure 1, since there are over etching and wet method when grid curb wall 1 etches
Process, causes the height h2 of grid curb wall to be less than the height h1 of grid；When top portions of gates forms cobalt silicon alloy 2, grid top
The volume in portion can increase, so that the meeting of cobalt silicon alloy 2 of top portions of gates to grid both sides and upwardly extends, form the process of through hole
In, since the offset of contact hole 3 causes contact hole close to grid；Since grid curb wall cannot provide top portions of gates enough protections
And top portions of gates cobalt silicon alloy causes spacing between contact hole and grid too small to lateral extension, as in Fig. 1 at dashed circle
Shown, breakdown voltage dies down.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of process of grid curb wall, can preferably protect grid
Pole, improves the breakdown voltage between contact hole and grid.
To solve the above problems, the process of grid curb wall of the present invention, comprising：
Step 1, forms one layer of polysilicon, then re-forms one layer of silicon oxynitride on a silicon substrate；
Step 2, photoetching offset plate figure is formed using the light shield of grid level；Then silicon oxynitride and polysilicon are performed etching, shape
Into the grid of transistor；Form gate silicon dioxide protective layer；
Step 3, deposited silicon nitride and silica；And silicon chip is generally etched, so as to form grid curb wall；Etch again
Fall the silicon oxynitride of top portions of gates；
Step 4, carries out source-drain area injection and forms cobalt silicon alloy；Etching barrier layer and contact hole dielectric layer are formed, carries out chemistry
Mechanical lapping；Carry out contact hole etching.
Further, in the step 1, polysilicon and silicon oxynitride use chemical vapour deposition technique.
Further, in the step 1, the optimal thickness of wherein silicon oxynitride layer is bottom when forming grid exposure
The thickness of portion's anti-reflection coating；Optimal thickness is the thickness more than subsequent gate side wall nitride silicon.
Further, in the step 2, rapid thermal annealing is carried out to grid or furnace process forms silica protection
Layer.
Further, in the step 3, silicon nitride and silica is formed using the method for low pressure chemical deposition, is used
Wet etching falls the silicon oxynitride of top portions of gates.
Further, in the step 4, etching barrier layer and contact hole medium are formed using chemical vapor deposition method
Layer.
Further, in the step 4, contact hole uses dry etching.
The process of grid curb wall of the present invention, compared with traditional grid curb wall forming method, shape of the present invention
Into grid curb wall have the grid curb wall height of higher, or with grid with there is thicker grid curb wall during height so that
Grid is preferably protected when contact hole etching, improves the breakdown voltage between contact hole and grid.
The present invention merely add the silicon oxynitride layer of deposition top portions of gates, grid relative to conventional gate formation method for side wall
Hard mask layer when silicon oxynitride at the top of pole can be as grid etch, this layer of hard mask layer when grid etch to providing
Protection, forms more preferable gate topography, in addition, the thickness of the photoresist of grid can be so reduced, to the grid in silicon chip
Size has more preferable uniformity.
Brief description of the drawings
Fig. 1 is the grid and contact hole pattern schematic diagram that traditional handicraft is formed.
Fig. 2~5 are present invention process method and step figures；
Fig. 6 is present invention process method flow diagram.
Description of reference numerals
H1 gate heights, h2 height of side wall, 1 grid curb wall, 2 cobalt silicon alloys, 3 contact holes, 4 etching barrier layers, 5 polysilicons, 6
Silicon oxynitride, 7 be grid oxic horizon.
Embodiment
The process of grid curb wall of the present invention, is described with reference to the drawings as follows：
Step 1, as shown in Fig. 2, forming one layer of polysilicon 5 on a silicon substrate using chemical vapour deposition technique, then re-forms one
Layer silicon oxynitride.The optimal thickness of silicon oxynitride layer 6 is the thickness of bottom antireflective coating when forming grid exposure；It is optimal
Thickness be more than subsequent gate side wall nitride silicon thickness.
Step 2, photoetching offset plate figure is formed using the light shield of grid level；Then silicon oxynitride and polysilicon are carved
Erosion, forms the grid of transistor；Gate silicon dioxide protective layer 7 is formed using rapid thermal annealing or furnace process, such as Fig. 3 institutes
Show.
Step 3, with the method deposited silicon nitride and silica of low pressure chemical deposition；And silicon chip is generally etched,
So as to form grid curb wall 1；Fall the silicon oxynitride of top portions of gates using wet etching again；As shown in Figure 4.
Step 4, carries out source-drain area injection and forms cobalt silicon alloy；Etch stopper is formed using chemical vapor deposition method
Layer 4 and contact hole dielectric layer, carry out chemical mechanical grinding；Carry out contact hole etching and form contact hole 3.As shown in Figure 5.
As shown in dashed circle in Fig. 5, the grid curb wall that the present invention is formed has the grid curb wall height of higher, Huo Zhe
With grid with there is thicker grid curb wall during height, so as to preferably protect grid when contact hole etching, improve and connect
Breakdown voltage between contact hole and grid.
It these are only the preferred embodiment of the present invention, be not intended to limit the present invention.Come for those skilled in the art
Say, the invention may be variously modified and varied.Within the spirit and principles of the invention, it is any modification for being made, equivalent
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (7)
- A kind of 1. process of grid curb wall, it is characterised in that：Comprising：Step 1, forms one layer of polysilicon, then re-forms one layer of silicon oxynitride on a silicon substrate；Step 2, photoetching offset plate figure is formed using the light shield of grid level；Then silicon oxynitride and polysilicon are performed etching, shape Into the grid of transistor；Form gate silicon dioxide protective layer；Step 3, deposited silicon nitride and silica；And silicon chip is generally etched, so as to form grid curb wall；Etch again Fall the silicon oxynitride of top portions of gates；Step 4, carries out source-drain area injection and forms cobalt silicon alloy；Etching barrier layer and contact hole dielectric layer are formed, carries out chemistry Mechanical lapping；Carry out contact hole etching.
- 2. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 1, polysilicon and nitrogen Silica uses chemical vapour deposition technique.
- 3. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 1, wherein nitrogen oxidation The optimal thickness of silicon layer is the thickness of bottom antireflective coating when forming grid exposure；Optimal thickness is more than subsequent gate The thickness of pole side wall nitride silicon.
- 4. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 2, grid is carried out Rapid thermal annealing or furnace process form silicon dioxide layer of protection.
- 5. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 3, low pressure is utilized The method for learning deposition forms silicon nitride and silica, and the silicon oxynitride of top portions of gates is fallen using wet etching.
- 6. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 4, chemical gas is utilized Phase depositing operation forms etching barrier layer and contact hole dielectric layer.
- 7. the process of grid curb wall as claimed in claim 1, it is characterised in that：In the step 4, contact hole uses Dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711163456.XA CN107978555A (en) | 2017-11-21 | 2017-11-21 | The process of grid curb wall |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711163456.XA CN107978555A (en) | 2017-11-21 | 2017-11-21 | The process of grid curb wall |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107978555A true CN107978555A (en) | 2018-05-01 |
Family
ID=62010660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711163456.XA Pending CN107978555A (en) | 2017-11-21 | 2017-11-21 | The process of grid curb wall |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107978555A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809004A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method, circuit and application of memory |
| CN116884884A (en) * | 2023-09-06 | 2023-10-13 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
| CN117316876A (en) * | 2023-11-28 | 2023-12-29 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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| US20020177080A1 (en) * | 2001-05-23 | 2002-11-28 | Cheng-Hui Chung | Interconnects with dual dielectric spacers and method for forming the same |
| CN101207028A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal-oxide-semiconductor device and semiconductor device |
| CN101740512A (en) * | 2008-11-27 | 2010-06-16 | 和舰科技(苏州)有限公司 | Method for removing improved silicon oxynitride |
| CN105826364A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN107833857A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The process of self-aligned contact hole |
-
2017
- 2017-11-21 CN CN201711163456.XA patent/CN107978555A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020177080A1 (en) * | 2001-05-23 | 2002-11-28 | Cheng-Hui Chung | Interconnects with dual dielectric spacers and method for forming the same |
| CN101207028A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal-oxide-semiconductor device and semiconductor device |
| CN101740512A (en) * | 2008-11-27 | 2010-06-16 | 和舰科技(苏州)有限公司 | Method for removing improved silicon oxynitride |
| CN105826364A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN107833857A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The process of self-aligned contact hole |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809004A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method, circuit and application of memory |
| CN116884884A (en) * | 2023-09-06 | 2023-10-13 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
| CN116884884B (en) * | 2023-09-06 | 2023-11-24 | 粤芯半导体技术股份有限公司 | Warming-up sheet for grid side wall ICP etching, preparation method thereof and warming-up method |
| CN117316876A (en) * | 2023-11-28 | 2023-12-29 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180501 |
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