CN102709167A - Side wall structure construction method - Google Patents
Side wall structure construction method Download PDFInfo
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- CN102709167A CN102709167A CN2012102089082A CN201210208908A CN102709167A CN 102709167 A CN102709167 A CN 102709167A CN 2012102089082 A CN2012102089082 A CN 2012102089082A CN 201210208908 A CN201210208908 A CN 201210208908A CN 102709167 A CN102709167 A CN 102709167A
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Abstract
The invention provides a side wall structure construction method which comprises the following steps: providing a semiconductor substrate, wherein a grid electrode is formed on the semiconductor substrate; forming an initial oxidation layer which covers the surfaces of the semiconductor substrate and the grid electrode; thinning the initial oxidation layer on two sides of the grid electrode so as to form a side wall oxidation layer of which the thickness is less than that of the initial oxidation layer, wherein the oxidation layers at the top of the grid electrode and the surface of the semiconductor substrate serve as protection layers; forming silicon nitride layers which cover the surfaces of the side wall oxidation layer and the protection layers; and carrying out an etching process so as to remove the silicon nitride layers positioned on the surfaces of the protection layers and the partial silicon nitride layer on the surface of the side wall oxidation layer, wherein the side wall oxidation layer and the residual silicon nitride layers on the two sides of the grid electrode together form a side wall structure. Due to the adoption of the wall side wall structure construction method provided by the invention, the side wall structure with smaller thickness (50-60 angstrom) can be constructed.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly the manufacture method of sidewall structure.
Background technology
In the transistor fabrication process, need utilize depositing operation and etching technics etc. to make sidewall structure in the grid both sides usually.For device feature size is the transistor more than 55 nanometers, and the width of its sidewall structure is usually greater than 100 dusts.Along with device feature size constantly reduces, then need reduce the thickness of sidewall structure.In order to make the less sidewall structure of thickness; Prior art adopts the single thin layer dielectric layer to make sidewall structure; Make sidewall structure such as thin silicon oxide layer that adopts individual layer or silicon nitride layer, but adopt the single thin layer silica to make sidewall structure, form in the process of sidewall structure at etching oxidation silicon; Can cause the silicon damage (Si loss) of the Semiconductor substrate of grid down either side; If adopt the single thin layer silicon nitride layer to make sidewall structure, then silicon nitride layer can cause bigger stress on device, thereby influences the performance of device.
Therefore need a kind of method of making sidewall structure, can produce the less sidewall structure of thickness.
Summary of the invention
The technical problem that the present invention solves has provided a kind of manufacture method of sidewall structure, can produce the less sidewall structure of thickness (thickness range is 50～60 dusts).
In order to address the above problem, the present invention proposes a kind of manufacture method of sidewall structure, comprising:
Semiconductor substrate is provided, is formed with grid on the said Semiconductor substrate;
Form initial oxide layer, said initial oxide layer covers the surface of said Semiconductor substrate and grid;
The initial oxide layer of grid both sides is carried out thickness cut out technology, form the side wall oxide layer of thickness less than said initial oxidation layer thickness, the oxide layer of top portions of gates and semiconductor substrate surface is as protective layer;
Form silicon nitride layer, said silicon nitride layer covers the surface of said side wall oxide layer and protective layer;
Carry out etching technics, remove silicon nitride layer that is positioned at the protective layer surface and the part silicon nitride layer that is positioned at side wall oxide layer surface, said side wall oxide layer and grid both sides residual silicon nitride layer constitute sidewall structure.
Alternatively; The thickness range of said initial oxide layer is 45～55 dusts; Said side wall thickness of oxide layer scope is 10～20 dusts; The thickness range of said silicon nitride layer is 65～75 dusts, and the thickness range of said side wall oxide layer both sides residual silicon nitride layer is 35～45 dusts, and the thickness range of said sidewall structure is 50～60 dusts.
Alternatively; Said thickness cutting technology utilization plasma etch process is carried out; The gas of said plasma etch process is CF4 and O2 gas mixture body, and the scope of the flow-rate ratio of CF4 and O2 gas is 2: 1～5: 1, and bias power is 0; The chamber pressure of plasma etch process is 30～70mTorr, and the process time is 10～25 seconds.
Alternatively, said initial oxide layer utilizes low-pressure chemical vapor deposition process to make.
Alternatively, the etching technics using plasma etching technics of said silicon nitride layer carries out, and comprising:
Utilize CF4 gas to form plasma silicon nitride layer is carried out etching, the thickness of the silicon nitride layer of removal is 18～22 dusts;
Utilize the mist of CF4, O2, inert gas that silicon nitride layer is carried out etching, the flow-rate ratio scope of said CF4 and O2 is 1: 1～4: 1, and etch period is 10～15 seconds;
The flow-rate ratio scope that the mist of employing CH3F and O2 carries out said CH3F of etching and O2 is 1: 1～3: 1, and etch period is 20～30 seconds.
Alternatively, said silicon nitride layer utilizes boiler tube technology to make.
Alternatively, also comprise:
Cleaning step is removed said thickness and is cut out polymer and the particle that technology forms.
Compared with prior art, the present invention has the following advantages:
The present invention carries out thickness to the initial oxide layer of grid both sides and cuts out technology; Formed the less side wall oxide layer of thickness; Thereby can guarantee the less sidewall structure of formation thickness; And the oxide layer of top portions of gates and semiconductor substrate surface is as protective layer, and this protective layer makes Semiconductor substrate and grid avoid receiving the damage of etching technics carrying out can protecting Semiconductor substrate and top portions of gates when etching technics is removed silicon nitride layer; Utilizing the thickness range of the sidewall structure of embodiment of the invention formation is 50～60 dusts;
Further optimally; Said thickness is cut out the technology utilization plasma etch process and is carried out; The parameter of said plasma etch process is: gas is CF4 and O2 gas mixture body; The scope of the flow-rate ratio of CF4 and O2 gas is 2: 1～5: 1, and bias power is 0, and the chamber pressure of plasma etch process is 30～70mTorr; Process time is 10～25 seconds; Thereby guaranteed vertical selection to the horizontal/of said initial oxide layer than higher, promptly reduced and when forming the side wall oxide layer, guaranteed that also the thickness of initial silicon oxide layer of semiconductor substrate surface is constant basically at thickness with the initial oxide layer of grid both sides; Thereby this initial silicon oxide layer that is positioned at semiconductor substrate surface and top portions of gates can be used as protective layer; Remove the process of the part silicon nitride layer of the silicon nitride layer be arranged in the protective layer surface and grid both sides carrying out etching technics, avoid top portions of gates and Semiconductor substrate to sustain damage, reduced requirement the selection ratio of the etching technics of silicon nitride layer;
Further optimally, said initial silicon oxide layer and silicon nitride layer utilize existing low-pressure chemical vapor deposition process and boiler tube technology to make respectively, thereby the manufacture craft of sidewall structure of the present invention is simple.
Description of drawings
Fig. 1 is the manufacture method schematic flow sheet of the sidewall structure of one embodiment of the invention;
Fig. 2～Fig. 6 is the cross-sectional view of the sidewall structure of one embodiment of the invention.
Embodiment
In 65 nanometers and above technology, the thickness of sidewall structure is bigger for characteristic size, and usually greater than 100 dusts, the manufacture craft of sidewall structure is relatively easy.But along with reducing of device feature size, the inventor finds, utilizes prior art can't form the less sidewall structure of thickness.Make sidewall structure if adopt mono-layer oxidized silicon layer; Then can cause the silicon damage (Siloss) of Semiconductor substrate in the process of etching oxidation silicon layer formation sidewall structure; Make sidewall structure if adopt the individual layer silicon nitride layer; Then silicon nitride layer causes bigger stress on device, thereby influences the performance of device.Therefore the inventor considers to adopt silicon oxide layer and silicon nitride layer to make sidewall structure; For the thickness of the sidewall structure that guarantees to form can satisfy 50～60 dusts; The thickness that then need guarantee silicon oxide layer is no more than 55 dusts; The thickness of silicon nitride layer is no more than 75 dusts, need improve the technology of existing silicon oxide layer and silicon nitride layer like this, thus can't be compatible with existing processes.
In order to address the above problem, the present invention proposes a kind of manufacture method of sidewall structure, specifically please combine the manufacture method schematic flow sheet of the sidewall structure of the described one embodiment of the invention of Fig. 1, and said method comprises:
Step S1 provides Semiconductor substrate, is formed with grid on the said Semiconductor substrate;
Step S2 forms initial oxide layer, and said initial oxide layer covers the surface of said Semiconductor substrate and grid;
Step S3 carries out thickness to the initial oxide layer of grid both sides and cuts out technology, forms the side wall oxide layer of thickness less than said initial oxidation layer thickness, and the oxide layer of top portions of gates and semiconductor substrate surface is as protective layer;
Step S4 forms silicon nitride layer, and said silicon nitride layer covers the surface of said side wall oxide layer and protective layer;
Step S5 carries out etching technics, removes silicon nitride layer that is positioned at the protective layer surface and the part silicon nitride layer that is positioned at side wall oxide layer surface, and said side wall oxide layer and grid both sides residual silicon nitride layer constitute sidewall structure.
Below in conjunction with concrete embodiment technical scheme of the present invention is carried out detailed explanation.For technical scheme of the present invention is described better, please combine the manufacture method schematic flow sheet of sidewall structure of the one embodiment of the invention of Fig. 2～shown in Figure 6.
At first, please combine Fig. 2, Semiconductor substrate 100 is provided, be formed with grid 110 on the said Semiconductor substrate 100.The material of said Semiconductor substrate 100 can be silicon.
Then, please refer to Fig. 3, form initial oxide layer 120, said initial oxide layer 120 covers the surface of said Semiconductor substrate 100 and grid 110.The thickness range of said initial oxide layer 120 is 45～55 dusts.As an optional embodiment of the present invention, the thickness of said initial oxide layer 120 is 50 dusts.As an embodiment, said initial oxide layer 120 utilizes low-pressure chemical vapor deposition (LPCVD) technology to make.In follow-up processing step; To carry out thickness and cut out technology; The feasible thickness that is positioned at the initial oxide layer of grid 110 both sides reduces; And the thickness of initial oxide layer at surface and grid 110 tops that is positioned at Semiconductor substrate 100 is constant; Thereby the initial oxide layer 120 that is positioned at said Semiconductor substrate 100 surfaces and grid 110 tops will be protected the top of Semiconductor substrate 100 surfaces and grid 110 as protective layer follow-up, forms the less side wall oxide layer of thickness and cut out the back at the initial oxide layer of grid 110 both sides through thickness.
Then, please refer to Fig. 4, the initial oxide layer of grid 110 both sides is carried out thickness cutting technology, form side wall oxide layer 121 in grid 110 both sides, and the surperficial initial oxide layer of the top that remaines in grid 110 and Semiconductor substrate 100 is as protective layer 122.
In the present embodiment; Said thickness cut out technology to the vertical selection of the horizontal/of said initial oxide layer than higher; Promptly reduce and when forming the side wall oxide layer, guaranteed that also the thickness of initial silicon oxide layer of semiconductor substrate surface is constant basically at thickness with the initial oxide layer of grid 110 both sides.As an embodiment; Said thickness is cut out the technology utilization plasma etch process and is carried out; The parameter of said plasma etch process is: gas is CF4 and O2 gas mixture body, and the scope of the flow-rate ratio of CF4 and O2 gas is 2: 1～5: 1, and bias power is 0; The chamber pressure of plasma etch process is 30～70mTorr, and the process time is 10～25 seconds.
In order to guarantee to form the less sidewall structure of thickness, the thickness range of cutting out the side wall oxide layer 121 of technology formation through thickness should be 10～20 dusts.As an embodiment, the thickness of said side wall oxide layer 121 is 15 dusts.
As preferred embodiment, after thickness is cut out technology, can carry out cleaning step, remove said thickness and cut out polymer and the particle that technology forms, prevent that above-mentioned polymer and particle from causing cross pollution to subsequent process steps, improve the yield of device.
Then, please refer to Fig. 5, form the silicon nitride layer 130 that covers said side wall oxide layer 121 and protective layer 122.As an embodiment, said silicon nitride layer 130 utilizes existing boiler tube technology to make.The thickness range of said silicon nitride layer 130 is 65～75 dusts.As an embodiment, the thickness range of said silicon nitride layer 130 is 60 dusts.Remove at the follow-up silicon nitride layer that will will be positioned at through etching technics above the protective layer 122, and keep the silicon nitride layer that is positioned at side wall oxide layer 121 both sides.
Please refer to Fig. 6, carry out etching technics, remove silicon nitride layer that is positioned at protective layer 122 surfaces and the part silicon nitride layer that is positioned at side wall oxide layer surface, said side wall oxide layer 121 constitutes sidewall structure 140 with grid 110 both sides residual silicon nitride layers 131.The thickness range of said side wall oxide layer 121 both sides residual silicon nitride layers 131 is 35～45 dusts, and the thickness range of said sidewall structure is 50～60 dusts.As an embodiment, the thickness of said side wall oxide layer 121 both sides residual silicon nitride layers 131 is 40 dusts, and the thickness range of said side wall oxide layer 121 is 15 dusts, and the thickness range of the final sidewall structure 121 that forms is 55 dusts.
The etching technics using plasma etching technics of said silicon nitride layer carries out, and comprising:
First etch step is utilized CF4 gas to form plasma silicon nitride layer is carried out etching, and the thickness of the silicon nitride layer of removal is 18～22 dusts;
Second etch step also is the main etching step, utilizes the mist of CF4, O2, inert gas that silicon nitride layer is carried out etching, and the flow-rate ratio scope of said CF4 and O2 is 1: 1～4: 1, and etch period is 10～15 seconds;
The 3rd etching step also is the over etching step, and the flow-rate ratio scope that the mist of employing CH3F and O2 carries out said CH3F of etching and O2 is 1: 1～3: 1, and etch period is 20～30 seconds.
In the above-mentioned etching technics, 122 pairs of Semiconductor substrate of protective layer 100 are protected with grid 110.
Compared with prior art, the present invention has the following advantages:
The present invention carries out thickness to the initial oxide layer of grid both sides and cuts out technology; Formed the less side wall oxide layer of thickness; Thereby can guarantee the less sidewall structure of formation thickness; And the oxide layer of top portions of gates and semiconductor substrate surface is as protective layer, and this protective layer makes Semiconductor substrate and grid avoid receiving the damage of etching technics carrying out can protecting Semiconductor substrate and top portions of gates when etching technics is removed silicon nitride layer; Utilizing the thickness range of the sidewall structure of embodiment of the invention formation is 50～60 dusts;
Further optimally; Said thickness is cut out the technology utilization plasma etch process and is carried out; The parameter of said plasma etch process is: gas is CF4 and O2 gas mixture body; The scope of the flow-rate ratio of CF4 and O2 gas is 2: 1～5: 1, and bias power is 0, and the chamber pressure of plasma etch process is 30～70mTorr; Process time is 10～25 seconds; Thereby guaranteed vertical selection to the horizontal/of said initial oxide layer than higher, promptly reduced and when forming the side wall oxide layer, guaranteed that also the thickness of initial silicon oxide layer of semiconductor substrate surface is constant basically at thickness with the initial oxide layer of grid both sides; Thereby this initial silicon oxide layer that is positioned at semiconductor substrate surface and top portions of gates can be used as protective layer; Remove the process of the part silicon nitride layer of the silicon nitride layer be arranged in the protective layer surface and grid both sides carrying out etching technics, avoid top portions of gates and Semiconductor substrate to sustain damage, reduced requirement the selection ratio of the etching technics of silicon nitride layer;
Further optimally, said initial silicon oxide layer and silicon nitride layer utilize existing low-pressure chemical vapor deposition process and boiler tube technology to make respectively, thereby the manufacture craft of sidewall structure of the present invention is simple.
Therefore, above-mentioned preferred embodiment is merely explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (7)
1. the manufacture method of a sidewall structure is characterized in that, comprising:
Semiconductor substrate is provided, is formed with grid on the said Semiconductor substrate;
Form initial oxide layer, said initial oxide layer covers the surface of said Semiconductor substrate and grid;
The initial oxide layer of grid both sides is carried out thickness cut out technology, form the side wall oxide layer of thickness less than said initial oxidation layer thickness, the oxide layer of top portions of gates and semiconductor substrate surface is as protective layer;
Form silicon nitride layer, said silicon nitride layer covers the surface of said side wall oxide layer and protective layer;
Carry out etching technics, remove silicon nitride layer that is positioned at the protective layer surface and the part silicon nitride layer that is positioned at side wall oxide layer surface, said side wall oxide layer and grid both sides residual silicon nitride layer constitute sidewall structure.
2. the manufacture method of sidewall structure as claimed in claim 1; It is characterized in that; The thickness range of said initial oxide layer is 45～55 dusts, and said side wall thickness of oxide layer scope is 10～20 dusts, and the thickness range of said silicon nitride layer is 65～75 dusts; The thickness range of said side wall oxide layer both sides residual silicon nitride layer is 35～45 dusts, and the thickness range of said sidewall structure is 50～60 dusts.
3. the manufacture method of sidewall structure as claimed in claim 1; It is characterized in that said thickness cutting technology utilization plasma etch process is carried out, the gas of said plasma etch process is CF4 and O2 gas mixture body; The scope of the flow-rate ratio of CF4 and O2 gas is 2: 1～5: 1; Bias power is 0, and the chamber pressure of plasma etch process is 30～70mTorr, and the process time is 10～25 seconds.
4. the manufacture method of sidewall structure as claimed in claim 1 is characterized in that, said initial oxide layer utilizes low-pressure chemical vapor deposition process to make.
5. the manufacture method of sidewall structure as claimed in claim 1 is characterized in that, the etching technics using plasma etching technics of said silicon nitride layer carries out, and comprising:
Utilize CF4 gas to form plasma silicon nitride layer is carried out etching, the thickness of the silicon nitride layer of removal is 18～22 dusts;
Utilize the mist of CF4, O2, inert gas that silicon nitride layer is carried out etching, the flow-rate ratio scope of said CF4 and O2 is 1: 1～4: 1, and etch period is 10～15 seconds;
The flow-rate ratio scope that the mist of employing CH3F and O2 carries out said CH3F of etching and O2 is 1: 1～3: 1, and etch period is 20～30 seconds.
6. the manufacture method of sidewall structure as claimed in claim 1 is characterized in that, said silicon nitride layer utilizes boiler tube technology to make.
7. the manufacture method of sidewall structure as claimed in claim 1 is characterized in that, also comprises: cleaning step, and remove said thickness and cut out polymer and the particle that technology forms.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417526A (en) * | 2017-02-09 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113808939A (en) * | 2020-06-15 | 2021-12-17 | 长鑫存储技术有限公司 | Method for forming silicon dioxide film and method for forming metal gate |
| WO2023133999A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174587A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Variable width offset spacers for mixed signal and system on chip devices |
| CN101599429A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Form the side wall method |
| CN101866852A (en) * | 2009-04-14 | 2010-10-20 | 中芯国际集成电路制造(北京)有限公司 | Method for constructing interval wall |
| CN102299062A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid sidewall of semiconductor part |
-
2012
- 2012-06-21 CN CN2012102089082A patent/CN102709167A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174587A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Variable width offset spacers for mixed signal and system on chip devices |
| CN101599429A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Form the side wall method |
| CN101866852A (en) * | 2009-04-14 | 2010-10-20 | 中芯国际集成电路制造(北京)有限公司 | Method for constructing interval wall |
| CN102299062A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid sidewall of semiconductor part |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417526A (en) * | 2017-02-09 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113808939A (en) * | 2020-06-15 | 2021-12-17 | 长鑫存储技术有限公司 | Method for forming silicon dioxide film and method for forming metal gate |
| CN113808939B (en) * | 2020-06-15 | 2023-09-22 | 长鑫存储技术有限公司 | Method for forming silicon dioxide film and method for forming metal gate |
| WO2023133999A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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Application publication date: 20121003 |