CN106558499B - The forming method of MOS transistor - Google Patents
The forming method of MOS transistor Download PDFInfo
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- CN106558499B CN106558499B CN201510642573.9A CN201510642573A CN106558499B CN 106558499 B CN106558499 B CN 106558499B CN 201510642573 A CN201510642573 A CN 201510642573A CN 106558499 B CN106558499 B CN 106558499B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A kind of forming method of MOS transistor, comprising: provide semiconductor substrate, the semiconductor substrate surface has gate structure, has stress material layer in the semiconductor substrate of the gate structure two sides；The first coating is formed in the stress material layer surface, the thickness of the central area of first coating is higher than the thickness of fringe region；First coating is etched, to reduce the thickness of the first coating central area；Several layers coating is formed on first coating after etching, previous coating is performed etching before one layer of coating of every formation, until the overall thickness of the fringe region of first coating and the coating is less than the overall thickness of central area and the overall thickness of fringe region is greater than 6nm, the overall thickness of central area is less than 40nm.The forming method of the MOS transistor improves the performance of MOS transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of MOS transistor.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source-drain area positioned at the gate structure of semiconductor substrate surface, in gate structure semiconductor substrates on two sides.
The working principle of MOS transistor is: by applying voltage in grid, adjusting is generated by the electric current of gate structure bottom channel
Switching signal.
The material of usual source-drain area is the material with stress, the direct shape of the metal silicide layer being subsequently formed in order to prevent
It misplaces between the contact surface on source-drain area surface on source-drain area surface, needs to form covering on the surface of source-drain area
Layer.
However, the performance for the MOS transistor that the prior art is formed is poor.
Summary of the invention
Problems solved by the invention is that the overall thickness in the central area of the first coating and coating keeps a certain range
When interior, avoid the overall thickness of the fringe region in the first coating and coating of stress material layer surface formation relatively thin, improve
The protective effect of the corresponding dead-wood bed of material, to improve the performance of MOS transistor.
To solve the above problems, the present invention provides a kind of forming method of MOS transistor, comprising: semiconductor substrate is provided,
The semiconductor substrate surface has gate structure, has stress material layer in the semiconductor substrate of the gate structure two sides；
The first coating is formed in the stress material layer surface, the thickness of the central area of first coating is higher than fringe region
Thickness；First coating is etched, to reduce the thickness of the first coating central area；Described first after etching is covered
Several layers coating is formed on cap rock, previous coating is performed etching before one layer of coating of every formation, until described
The overall thickness of the fringe region of first coating and the coating is less than the overall thickness of central area and the total thickness of fringe region
Degree is greater than 6nm, and the overall thickness of central area is less than 40nm.
Optionally, the technique for etching the coating is wet-etching technique.
Optionally, the parameter of the wet-etching technique are as follows: the etching solution used is tetramethyl ammonium hydroxide solution, tetramethyl
The mass percent concentration of ammonium hydroxide is 1%~30%, and etching temperature is 20 degrees Celsius~50 degrees Celsius.
Optionally, the parameter of the wet-etching technique are as follows: for the etching solution used for KOH solution, the mass percent of KOH is dense
Degree is 0.1%~40%, and etching temperature is 20 degrees Celsius~50 degrees Celsius.
Optionally, the material of the coating is silicon.
Optionally, the technique for forming each layer of coating is selective epitaxial growth process.
Optionally, the parameter of the selective epitaxial growth process are as follows: the gas used is SiH4And H2Cl2One in Si
Kind or combinations thereof, the total flow of the gas is 30sccm~300sccm, and temperature is 550 degrees Celsius~750 degrees Celsius, chamber
Pressure is 1torr~50mtorr.
Optionally, the number of plies of the coating is 1 to 4 layers.
Optionally, when the MOS transistor is N-type MOS transistor, the material of the stress material layer is germanium silicon.
Optionally, when the MOS transistor is N-type MOS transistor, the material of the stress material layer is carbon silicon.
Compared with prior art, technical solution of the present invention has the advantage that
Due to etching first coating to reduce the thickness of the first coating central area, then the after etching
Several coatings are formed on one coating, previous coating is performed etching before one layer of coating of every formation, until institute
State the fringe region of the first coating and the coating overall thickness be less than central area overall thickness and fringe region it is total
Thickness is greater than 6nm, and the overall thickness of central area is less than 40nm.So that the overall thickness of the central area of the first coating and coating
It keeps a certain range of while increasing the overall thickness of the fringe region of the first coating and coating.It first coating and covers
The overall thickness of the central area of cap rock is kept in a certain range, so that the thickness of the central area of the first coating and coating is not
Can be too thick, it not will increase the resistance between the metal silicide layer being subsequently formed and stress material layer；Simultaneously as increasing
The protective effect that the overall thickness of the fringe region of one coating and coating, the first coating and coating correspond to the dead-wood bed of material increases
By force, the surface of stress material layer will not be exposed in subsequent etching technics, will not be damaged to stress material layer and be subtracted
The stress of small stress material layer；The overall thickness for avoiding the central area of the first coating and coating needs to keep a certain range
While interior, the overall thickness of the fringe region of the first coating and coating is excessively thin and corresponding to the protective effect of the dead-wood bed of material reduces
The phenomenon that, to improve the performance of MOS transistor.
Further, the number of plies of several coatings is 1 to 4 layers, as the number of plies of coating increases, the first coating
Further decreased with the difference of the overall thickness of the overall thickness and central area of the fringe region of coating so that the first coating and
Under the conditions of the overall thickness of the central area of coating keeps a certain range of, the fringe region of the first coating and coating
Overall thickness further increases；Meanwhile the number of plies of coating is unlikely to excessively, to reduce manufacturing technology steps, saved manufacture at
This.
Detailed description of the invention
Fig. 1 to Fig. 4 is the schematic diagram of MOS transistor forming process in the prior art；
Fig. 5 to Fig. 9 is the schematic diagram of MOS transistor forming process in first embodiment of the invention；
Figure 10 and Figure 11 is the schematic diagram of MOS transistor forming process in second embodiment of the invention；
Figure 12 and Figure 13 is the schematic diagram of MOS transistor forming process in third embodiment of the invention.
Specific embodiment
As described in background, the performance for the MOS transistor that the prior art is formed is poor.
Fig. 1 to Fig. 4 is the schematic diagram of MOS transistor forming process in the prior art.
With reference to Fig. 1, semiconductor substrate 100 is provided, 100 surface of semiconductor substrate has gate structure 110, the grid
There is groove 120 in the semiconductor substrate 100 of 110 two sides of pole structure.
The crystal orientation of the semiconductor substrate 100 is (100).
The 110 two sides sidewall surfaces of gate structure have side wall 111.
With reference to Fig. 2, stress material layer 121 is formed in the groove 120 (referring to Fig. 1).
The material of the stress material layer 121 is germanium silicon.
With reference to Fig. 3, coating 130 is formed on 121 surface of stress material layer.
The material of the coating 130 is silicon.
The effect of the coating 130 are as follows: answer dead-wood for preventing the metal silicide layer being subsequently formed to be formed directly into
121 surface of the bed of material avoids misplacing between stress material layer 121 and the contact surface of metal silicide layer.
The study found that there are the poor reasons of performance to be for the MOS transistor of above method formation:
During forming the coating, silicon is much larger than the life in (111) crystal face in the growth rate of (100) crystal face
Long rate, so that overall thickness of the overall thickness of the fringe region of the coating much smaller than the central area of the coating, and
In order to enable the resistance between the metal silicide layer being subsequently formed and stress material layer is unlikely to excessive, need to make the covering
The overall thickness of layer central area is kept in a certain range, if the overall thickness of the coating central area is maintained at a certain range
It is interior, cause the overall thickness in the cover layer edges region that cannot increase, institute as the overall thickness of coating central area increases
The overall thickness for stating the fringe region of coating is relatively thin, in subsequent etching technics, is easy the fringe region to the coating
Etching injury is caused, the surface (with reference to Fig. 4) for exposing part stress material layer subtracts so that the corresponding dead-wood bed of material causes to damage
Stress in small stress material layer, to reduce the performance of MOS transistor.
On this basis, the present invention provides a kind of forming method of MOS transistor, forms first in stress material layer surface
Coating and after performing etching to the first coating, forms several coatings in the first cover surface, forms one layer every and covers
Preceding layer coating is performed etching before cap rock, so that the overall thickness of the central area of the first coating and the coating
Under the premise of in a certain range, the overall thickness of the fringe region of the first coating and the coating increases, so that the
One coating and the coating correspond to dead-wood bed of material protective effect increase.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
First embodiment
Fig. 5 to Fig. 9 is the schematic diagram of MOS transistor forming process in first embodiment of the invention.
With reference to Fig. 5, semiconductor substrate 200 is provided, 200 surface of semiconductor substrate has gate structure 210, the grid
There is groove 230 in the semiconductor substrate 200 of 210 two sides of pole structure.
The semiconductor substrate 200 provides technique platform to be subsequently formed MOS transistor.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can also be other semiconductor materials, here no longer
It illustrates one by one.In the present embodiment, the material of the semiconductor substrate 200 is silicon.
In the present embodiment, the crystal orientation of the semiconductor substrate 200 is (100).It should be noted that in other embodiments
In, the crystal orientation of semiconductor substrate 200 can be (101), (001), (010) or (110).
The gate structure 210 includes positioned at the gate dielectric layer 211 on 200 surface of semiconductor substrate and positioned at gate dielectric layer
The gate electrode layer 212 on 211 surfaces.
In the present embodiment, the material of the gate dielectric layer 211 is silica, and the material of the gate electrode layer 212 is polycrystalline
Silicon.In other embodiments, the material of the gate dielectric layer 211 is high K dielectric material (K is greater than 3.9), such as HfO2、La2O3、
HfSiON、HfAlO2、SiO2、ZrO2、Al2O3、HfO2、HfSiO4、La2O3, HfSiON or HfAlO2, the gate electrode layer 212
Material is metal.
The method for forming gate structure 210 are as follows: gate dielectric material is formed on 200 surface of semiconductor substrate using depositing operation
The layer of gate electrode material (not shown) of layer (not shown) and cover grid layer of dielectric material；It is formed in the gate material layer surface
Patterned mask layer (not shown), the patterned mask layer define the position of gate structure 210；With described patterned
Mask layer is exposure mask, etches the gate dielectric material layer and the layer of gate electrode material, until exposing semiconductor substrate 200
Surface forms gate structure 210.
In the present embodiment, the 210 two sides sidewall surfaces of gate structure are also formed with side wall 220.The work of the side wall 220
With are as follows: define the distance between the source-drain area being subsequently formed and gate structure 210；Protect gate structure 210.The side wall 220
Material be silicon nitride or silicon oxynitride.
The method for forming the side wall 220 are as follows: covering semiconductor substrate 200 and gate structure are formed using depositing operation
210 spacer material layer；The spacer material layer is etched using anisotropy dry carving technology until exposing semiconductor substrate 200
Surface forms side wall 220.
In the present embodiment, by taking the MOS transistor is N-type MOS transistor as an example, the section shape of the groove 230 is
Sigma's shape, the groove 230 of Sigma's shape are conducive to arrive the stress release for being filled in the stress material layer 231 of groove 230
In channel.
The method for forming the groove 230 are as follows: form covering gate structure 210, side wall 220 and semiconductor substrate 200
Mask layer；The graphical mask layer, forms patterned mask layer, the patterned mask layer defines ditch
The position of slot 230；Using the patterned mask layer as exposure mask, using dry carving technology etch semiconductor substrates 200, described half
The side wall opening (not shown) vertical with bottom is formed in conductor substrate 200；Wet etching is carried out to the opening, until in semiconductor
The groove 230 of Sigma's shape is formed in substrate 200.
The material of the patterned mask layer is silicon nitride or silicon oxynitride, after forming groove 230, is not removed described
Patterned mask layer is being subsequently formed stress material layer, the first coating and positioned at several coverings of the first cover surface
During layer, the patterned mask layer is used to cover 210 surface of 200 top surface of semiconductor substrate and gate structure,
It prevents subsequent stress material layer, the first coating and is grown in semiconductor substrate positioned at several coatings of the first cover surface
210 surface of 200 top surfaces and gate structure.
In other embodiments, the section shape of the groove 230 can be bowl-type or rectangular.
With reference to Fig. 6, stress material layer 231 is formed in groove 230 (referring to Fig. 5).
When the MOS transistor is N-type MOS transistor, the material of the stress material layer 231 is germanium silicon.When described
When MOS transistor is N-type MOS transistor, the material carbon silicon of the stress material layer 231.In the present embodiment, MOS transistor P
Type MOS transistor, the material of stress material layer 231 are germanium silicon.
Using epitaxial growth technology in groove 230 growth stress material layer 231.
In the present embodiment, the stress material layer 231 is single layer structure；In other embodiments, the stress material layer
231 be laminated construction, specifically, the stress material layer 231 includes the first stress material layer (not shown) and is located at described the
Second stress material layer (not shown) of one stress material layer surface.For PMOS transistor, in the second stress material layer
The atomicity percent concentration of germanium is greater than the atomicity percent concentration of germanium in the first stress material layer；For NMOS crystal
It manages, the atomicity percent concentration of carbon is greater than the atomicity of carbon in the first stress material layer in the second stress material layer
Percent concentration.
With reference to Fig. 7, the first coating 240 is formed on 231 surface of stress material layer.
The material of first coating 240 is silicon or germanium silicon, for preventing the metal silicide layer being subsequently formed direct
It is formed in 231 surface of stress material layer and stress material layer 231 and the contact surface of metal silicide layer is caused to misplace.
When the material of first coating 240 is germanium silicon, the atomicity percentage of germanium in first coating 240
Greater than 0% and less than 10%.In the present embodiment, the material of first coating 240 is silicon.
The method for forming first coating 240 is depositing operation, such as plasma activated chemical vapour deposition technique, atom
Layer depositing operation or selective epitaxial growth process.
In the present embodiment, the method for forming first coating 240 is selective epitaxial growth process, specific technique
Parameter are as follows: the gas used is SiH4And H2Cl2One of Si or combinations thereof, the total flow of the gas be 30sccm~
300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.
First coating 240 has fringe region and central area, and the fringe region of the first coating 240 refers to close
The region of 230 top side wall of groove, in addition to the first covering in the first coating 240 that the central area of the first coating 240 refers to
The part of 240 fringe region of layer, the central area of first coating 240 are thicker than the fringe region of the first coating 240.It needs
It is noted that the definition for central area and fringe region is no longer described in detail suitable for each coating being subsequently formed.
During forming the first coating 240, silicon is much larger than in the growth rate of (100) crystal face in (111) crystal face
Growth rate so that the thickness of the fringe region of first coating 240 be much smaller than first coating 240 center
The thickness in region is easy pair if directly carrying out subsequent etching technics, especially dry carving technology on 240 surface of the first coating
The fringe region of first coating 240 causes etching injury, the surface of part stress material layer 231 is exposed, thus right
Stress material layer 231 causes to damage, and reduces the stress in stress material layer 231.
First coating, 240 central area with a thickness of 15nm~30nm.
With reference to Fig. 8, first coating 240 is etched to reduce the central area thickness of first coating 240.
The technique for etching first coating 240 is wet-etching technique, and the solution of the wet-etching technique can be organic base
Property solution, can also be inorganic caustic solutions, the etch rate of 240 central area of the first coating is greater than to the first coating
The etch rate of 240 fringe regions.
When the solution of the wet-etching technique is organic alkaline solution, the organic alkaline solution can be tetramethyl hydrogen-oxygen
Change ammonium (Tetramethy lammonium Hydroxide, TMAH) solution；The solution of the wet-etching technique is that inorganic alkaline is molten
When liquid, the inorganic caustic solutions are KOH, NaOH or NH4OH solution.
In the present embodiment, the etching solution that the first coating 240 of etching uses is tetramethyl ammonium hydroxide solution；Another
In a embodiment, the etching solution that the first coating 240 of etching uses is KOH solution.
It is too small to the rate of the first coating 240 etching if the concentration of etching solution is too low, reduce process efficiency；If
The excessive concentration of etching solution also will increase while increase 240 central area of the first coating etching degree and cover to first
The etching degree of 240 fringe region of cap rock, the thickness that the first coating 240 etches back edge region is excessively thin, therefore, molten when etching
When liquid is tetramethyl ammonium hydroxide solution, selecting the mass percent concentration of tetramethylammonium hydroxide is 1%~30%, works as etching
When solution is KOH solution, selecting the mass percent concentration of KOH is 0.1%~40%.
It is increased same to 240 central area of the first coating etching degree if the etching temperature of the first coating 240 is excessively high
When also will increase etching degree to 240 fringe region of the first coating, the first coating 240 etches the thickness in back edge region
It is excessively thin, if the etching temperature of the first coating 240 is too low, it can to reduce the etch rate of the first coating 240, reduce and carve
Efficiency is lost, therefore, when etching solution is tetramethyl ammonium hydroxide solution, selective etching temperature is 20 degrees Celsius~50 Celsius
Degree, when etching solution is KOH solution, selective etching temperature is 20 degrees Celsius~50 degrees Celsius.
In the present embodiment, the first coating 240 has crystal face (110), (100) and (111), the tetramethylammonium hydroxide
Solution is 66:33:1 to the etch rate ratio of the first coating 240 on (110), (100) and (111) crystal face.In other embodiments
In, etch rate ratio of the tetramethyl ammonium hydroxide solution to the first coating 240 on (110), (100) and (111) crystal face
Value can choose other numerical value.
The first coating 240 is performed etching using wet-etching technique, along the corrosion rate of silicon wafer face (100) and (110)
It is faster than the corrosion rate along silicon wafer face (111), therefore, the central area thickness of first coating 240 can be reduced, and
The variation of the thickness of the fringe region of first coating 240 is smaller, so that 240 central area of the first coating and marginal zone
The thickness difference in domain reduces.
First coating, 240 central area with a thickness of 10nm~20nm after etching.
With reference to Fig. 9,240 surface of the first coating after etching forms the second coating 241.
After forming the second coating 241, the overall thickness of the fringe region of the first coating 240 and the second coating 241 is big
Overall thickness in first thickness and the central area of the first coating 240 and the second coating 241 is less than second thickness.
The first thickness is 6nm, and the second thickness is 40nm.
The effect of second coating 241 are as follows: answered for preventing the metal silicide layer being subsequently formed to be formed directly into
231 surface of the dead-wood bed of material and cause stress material layer 231 and the contact surface of metal silicide layer to misplace；Increase by the first covering
The overall thickness of the fringe region of layer 240 and the second coating 241.
The material of second coating 241 is silicon or germanium silicon.When the material of second coating 241 is germanium silicon,
The atomicity percentage of germanium is greater than 0% and less than 10% in second coating 241.In the present embodiment, second covering
The material of layer 241 is silicon.
The central area of second coating 241 with a thickness of 10nm~20nm.
The method for forming second coating 241 is depositing operation, such as plasma activated chemical vapour deposition technique, atom
Layer depositing operation or selective epitaxial growth process.
In the present embodiment, the method for forming second coating 241 is selective epitaxial growth process, specific technique
Parameter are as follows: the gas used is SiH4And H2Cl2One of Si or combinations thereof, the total flow of the gas be 30sccm~
300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.
It should be noted that if the overall thickness of the central area of the first coating 240 and the second coating 241 is excessively thin, it is right
The protective effect of stress material layer 231 weakens, and in subsequent etching technics, especially dry carving technology is easy to expose stress
The surface of material layer 231, so that the corresponding dead-wood bed of material 231 causes etching injury；If the first coating 240 and the second coating
The overall thickness of 241 central area is blocked up, so that the resistance between the metal silicide layer being subsequently formed and stress material layer 231
Increase；Therefore, it is necessary to the overall thickness of the central area of the first coating 240 and the second coating 241 to be maintained at a certain range.This
In embodiment, the overall thickness of 241 central area of the first coating 240 and the second coating is 20nm~40nm.
The central area thickness that first coating 240 is reduced due to first etching the first coating 240, is then being carved
240 surface of the first coating after erosion forms the second coating 241, so that in the first coating 240 and the second coating 241
Under the premise of the overall thickness in heart district domain is maintained at a certain range, the fringe region of the first coating 240 and the second coating 241
Overall thickness increases, and the protective effect of the first coating 240 and corresponding 231 edge region of the dead-wood bed of material of the second coating 241 increases
By force.In subsequent etching technics, the surface of stress material layer 231 will not be exposed.
After forming the second coating 241, with side wall 220 and gate structure 210 be exposure mask correspond to the dead-wood bed of material 231 carry out from
Son injection forms source-drain area.For PMOS transistor, Doped ions are P-type ion, such as B or In；For NMOS transistor, doping
Ion is N-type ion, such as P (phosphorus) or As.Then metal silicide layer is formed on 241 surface of the second coating (not scheme
Show).
In the present embodiment, one layer of coating is formed on the first coating 240.
Second embodiment
Figure 10 to Figure 11 is the schematic diagram of MOS transistor forming process in second embodiment of the invention.
The difference of second embodiment and first embodiment is: on the basis of first embodiment, carving to the second coating
It loses to reduce the thickness of the central area of the second coating, then the surface of the second coating after etching forms third covering
Layer.First coating and second in the thickness and first embodiment of first coating and each layer of the second coating in second embodiment
The thickness of each layer of coating is different.Identical part in second embodiment and first embodiment is no longer described in detail.
With reference to Figure 10, Figure 10 is the schematic diagram formed on the basis of Fig. 9, etches second coating 241 to reduce
State the central area thickness of the second coating 241.
In the present embodiment, the first coating 240 etching before central area with a thickness of 15nm~30nm, the first coating
After 240 etchings central area with a thickness of 8nm~15nm, before the second coating 241 etching central area with a thickness of
15nm~30nm, the second coating 241 etching after central area with a thickness of 8nm~15nm.
The technique for etching the second coating 241 is wet-etching technique, and the solution of the wet-etching technique can be molten for organic basic
Liquid can also be inorganic caustic solutions, be greater than the etch rate of 241 central area of the second coating to the second coating 241
The etch rate of fringe region.
When the solution of the wet-etching technique is organic alkaline solution, the organic alkaline solution can be tetramethyl hydrogen-oxygen
Change ammonium (Tetramethy lammonium Hydroxide, TMAH) solution；The solution of the wet-etching technique is that inorganic alkaline is molten
When liquid, the inorganic caustic solutions are KOH, NaOH or NH4OH solution.
In the present embodiment, the etching solution that the second coating 241 of etching uses is tetramethyl ammonium hydroxide solution；Another
In a embodiment, the etching solution that the second coating 241 of etching uses is KOH solution.
It is too small to the rate of the second coating 241 etching if the concentration of etching solution is too low, reduce process efficiency；If
The excessive concentration of etching solution also will increase while increase 241 central area of the second coating etching degree and cover to second
The etching degree of 241 fringe region of cap rock, the thickness that the second coating 241 etches back edge region is excessively thin, therefore, molten when etching
When liquid is tetramethyl ammonium hydroxide solution, selecting the mass percent concentration of tetramethylammonium hydroxide is 1%~30%.Work as etching
When solution is KOH solution, selecting the mass percent concentration of KOH is 0.1%~40%.
It is increased same to 241 central area of the second coating etching degree if the etching temperature of the second coating 241 is excessively high
When also will increase etching degree to 241 fringe region of the second coating, the second coating 241 etches the thickness in back edge region
It is excessively thin, if the etching temperature of the second coating 241 is too low, it can to reduce the etch rate of the second coating 241, reduce and carve
Efficiency is lost, therefore, when etching solution is tetramethyl ammonium hydroxide solution, selective etching temperature is 20 degrees Celsius~50 Celsius
Degree, when etching solution is KOH solution, selective etching temperature is 20 degrees Celsius~50 degrees Celsius.
Second coating 241 has crystal face (110), (100) and (111), the tetramethyl ammonium hydroxide solution pair
(110), the etch rate ratio of the second coating 241 is 66:33:1 on (100) and (111) crystal face.In other embodiments, institute
Stating tetramethyl ammonium hydroxide solution can be with to the etch rate ratio of the first coating 240 on (110), (100) and (111) crystal face
It selects other.
The second coating 241 is performed etching using wet-etching technique, along the corrosion rate of silicon wafer face (100) and (110)
It is faster than the corrosion rate along silicon wafer face (111), therefore, the central area thickness of second coating 241 can be reduced, and
The variation of the thickness of the fringe region of second coating 241 is smaller.
With reference to Figure 11,241 surface of the second coating after etching forms third coating 242.
After forming third coating 242, first coating 240, the second coating 241 and third coating 243
The overall thickness of fringe region is greater than first thickness, and first coating 240, the second coating 241 and third coating 243
Central area overall thickness be less than second thickness.
The first thickness is 6nm, and the second thickness is 40nm.
The effect of the third coating 242 are as follows: answered for preventing the metal silicide layer being subsequently formed to be formed directly into
231 surface of the dead-wood bed of material and cause stress material layer 231 and the contact surface of metal silicide layer to misplace；Increase by the first covering
The overall thickness of the fringe region of the 240, second coating 241 of layer and third coating 242.
The material of the third coating 242 be silicon, 242 central area of third coating with a thickness of 4nm~10nm.
The overall thickness of 242 central area of first coating 240, the second coating 241 and third coating be 20nm~
40nm。
The method for forming the third coating 242 is depositing operation, such as plasma activated chemical vapour deposition technique, atom
Layer depositing operation or selective epitaxial growth process.
In the present embodiment, the method for forming the third coating 242 is selective epitaxial growth process, specific technique
Parameter are as follows: the gas used is SiH4And H2Cl2One of Si or combinations thereof, the total flow of the gas be 30sccm~
300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.
The thickness of 241 central area of the second coating is reduced due to etching, then the second coating 241 after etching
Surface forms third coating 242, so that 242 central area of the first coating 240, the second coating 241 and third coating
Overall thickness keep a certain range under the premise of, the edge of the first coating 240, the second coating 241 and third coating 242
The overall thickness in region further increases, the corresponding dead-wood bed of material of the first coating 240, the second coating 241 and third coating 242
The protective effect of 231 edge regions further enhances.
After forming third coating 242, with side wall 220 and gate structure 210 be exposure mask correspond to the dead-wood bed of material 231 carry out from
Son injection forms source-drain area.Then metal silicide layer (not shown) is formed on 242 surface of third coating.
In the present embodiment, two layers of coating, respectively the second coating 241 and are formd on the first coating 240
Three coatings 242.
3rd embodiment
Figure 12 and Figure 13 is the schematic diagram of MOS transistor forming process in third embodiment of the invention.
The difference of the present embodiment and second embodiment is: on the basis of second embodiment, etching to third coating
To reduce the thickness of the central area of third coating, then the surface of third coating after etching forms the 4th covering
Layer.In 3rd embodiment first in the first coating, the thickness of the second coating and each layer of third coating and second embodiment
Coating, the second coating are different with the thickness of each layer of third coating.For identical in the present embodiment and second embodiment
Part is no longer described in detail.
With reference to Figure 12, Figure 12 is the schematic diagram formed on the basis of Figure 11, and etching third coating 242 is covered with reducing third
The thickness of the central area of cap rock 242.
In the present embodiment, the first coating 241 etching before central area with a thickness of 10nm~20nm, the first coating
After 241 etchings central area with a thickness of 5nm~10nm, before the second coating 241 etching central area with a thickness of
10nm~20nm, after the second coating 241 etching central area with a thickness of 5nm~10nm, 242 etching of third coating
Preceding central area with a thickness of 10nm~20nm, central area with a thickness of 5nm~10nm after third coating 242 etches.
The technique for etching third coating 242 is wet-etching technique, and the solution of the wet-etching technique can be molten for organic basic
Liquid can also be inorganic caustic solutions, be greater than the etch rate of 242 central area of third coating to third coating 242
The etch rate of fringe region.
When the solution of the wet-etching technique is organic alkaline solution, the organic alkaline solution can be tetramethyl hydrogen-oxygen
Change ammonium (Tetramethy lammonium Hydroxide, TMAH) solution；The solution of the wet-etching technique is that inorganic alkaline is molten
When liquid, the inorganic caustic solutions are KOH, NaOH or NH4OH solution.
In the present embodiment, the etching solution that etching third coating 242 uses is tetramethyl ammonium hydroxide solution；Another
In a embodiment, the etching solution of etching third coating 242 is KOH solution.
If the concentration of etching solution is too low, the rate etched to third coating 242 is too small, reduces process efficiency；If
The excessive concentration of etching solution also will increase while increase 242 central area of third coating etching degree and cover to third
The etching degree of 242 fringe region of cap rock, the thickness that third coating 242 etches back edge region is excessively thin, therefore, molten when etching
When liquid is tetramethyl ammonium hydroxide solution, selecting the mass percent concentration of tetramethylammonium hydroxide is 1%~30%, works as etching
When solution is KOH solution, selecting the mass percent concentration of KOH is 0.1%~40%.
It is increased same to 242 central area of third coating etching degree if the etching temperature of third coating 242 is excessively high
When also will increase etching degree to 242 fringe region of third coating, third coating 242 etches the thickness in back edge region
It is excessively thin, if the etching temperature of third coating 242 is too low, it can to reduce the etch rate of third coating 242, reduce and carve
Efficiency is lost, therefore, when etching solution is tetramethyl ammonium hydroxide solution, selective etching temperature is 20 degrees Celsius~50 Celsius
Degree, when etching solution is KOH solution, selective etching temperature is 20 degrees Celsius~50 degrees Celsius.
The third coating 242 has crystal face (110), (100) and (111), the tetramethyl ammonium hydroxide solution pair
(110), the etch rate ratio of third coating 242 is 66:33:1 on (100) and (111) crystal face.In other embodiments, institute
Stating tetramethyl ammonium hydroxide solution can be with to the etch rate ratio of the first coating 240 on (110), (100) and (111) crystal face
It selects other.
Third coating 242 is performed etching using wet-etching technique, along the corrosion rate of silicon wafer face (100) and (110)
It is faster than the corrosion rate along silicon wafer face (111), therefore, the central area thickness of the third coating 242 can be reduced, and
The variation of the thickness of the fringe region of the third coating 242 is smaller.
With reference to Figure 13,242 surface of third coating after etching forms the 4th coating 243.
After forming the 4th coating 243, the first coating 240, the second coating 241, third coating 242 and the 4th cover
The overall thickness of 243 central area of cap rock is 20nm~40nm, first coating 240, the second coating 241, third covering
The overall thickness of layer 242 and 243 edge region of the 4th coating is greater than first thickness and in the overall thickness of central area less than the
Two thickness.
The first thickness is 6nm, and the second thickness is 40nm.
The effect of 4th coating 243 are as follows: answered for preventing the metal silicide layer being subsequently formed to be formed directly into
231 surface of the dead-wood bed of material and cause stress material layer 231 and the contact surface of metal silicide layer to misplace；Increase by the first covering
The overall thickness of the fringe region of the 240, second coating 241 of layer, third coating 242 and the 4th coating 243.
The material of 4th coating 243 be silicon, 243 central area of the 4th coating with a thickness of 5nm~10nm.
The method for forming the 4th coating 243 is depositing operation, such as plasma activated chemical vapour deposition technique, atom
Layer depositing operation or selective epitaxial growth process.
In the present embodiment, the method for forming the 4th coating 243 is selective epitaxial growth process, specific technique
Parameter are as follows: the gas used is SiH4And H2Cl2One of Si or combinations thereof, the total flow of the gas be 30sccm~
300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.
The thickness of 242 central area of third coating is reduced due to etching, then third coating 242 after etching
Surface forms the 4th coating 243, so that the first coating 240, the second coating 241, third coating 242 and the 4th covering
Under the premise of the overall thickness of 243 central area of layer keeps a certain range, the first coating 240, the second coating 241, third are covered
The overall thickness of the fringe region of cap rock 242 and the 4th coating 243 further increases, the first coating 240, the second coating
241, the protective effect of third coating 242 and corresponding 231 edge region of the dead-wood bed of material of the 4th coating 243 further increases
By force.
After forming the 4th coating 243, with side wall 220 and gate structure 210 be exposure mask correspond to the dead-wood bed of material 231 carry out from
Son injection forms source-drain area.Then metal silicide layer (not shown) is formed on 243 surface of the 4th coating.
In the present embodiment, three layers of coating, respectively the second coating 241, third are formd on the first coating 240
Coating 242 and the 4th coating 243.
It should be noted that several layers coating can be formed in the first cover surface, in one layer of coating of every formation
Preceding layer coating is performed etching before, the etch rate of preceding layer coating central area is greater than, preceding layer is covered
The etch rate of layer fringe region, until the overall thickness in the first coating and cover layer edges region is greater than first thickness and first
Coating and the thickness of coating central area are less than second thickness.
The fringe region of the coating refers to the region at the top of trenched side-wall, the central area of the coating
Refer to the part in coating in addition to fringe region, and the central area of coating is thicker than cover layer edges region.
As the number of plies of the coating formed on the first coating increases, so that the center of the first coating and coating
Under the premise of the overall thickness in domain keeps a certain range, the overall thickness of the fringe region of the first coating and coating further increases
Add, and the difference of the overall thickness of the overall thickness and central area of the fringe region of the first coating and coating reduces, first covers
Cap rock and coating further enhance the protective effect of the edge region of the stress material layer.
In actual process, it is contemplated that the factor of manufacturing cost and manufacturing technology steps, the number of plies of several coatings
It is 1~4 layer.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of MOS transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface has gate structure, and the semiconductor of the gate structure two sides serves as a contrast
There is stress material layer in bottom；
The first coating is formed in the stress material layer surface, the thickness of the central area of first coating is higher than edge
The thickness in region；
First coating is etched, to reduce the thickness of the first coating central area, the first coating center after etching
Domain with a thickness of 10nm~20nm；
Several layers coating is formed on first coating after etching, to previous before one layer of coating of every formation
Coating performs etching, until the overall thickness of the fringe region of first coating and the coating is less than central area
Overall thickness and the overall thickness of fringe region are greater than 6nm, and the overall thickness of central area is less than 40nm.
2. the forming method of MOS transistor according to claim 1, which is characterized in that the technique for etching the coating
For wet-etching technique.
3. the forming method of MOS transistor according to claim 2, which is characterized in that the parameter of the wet-etching technique are as follows:
For the etching solution used for tetramethyl ammonium hydroxide solution, the mass percent concentration of tetramethylammonium hydroxide is 1%~30%,
Etching temperature is 20 degrees Celsius~50 degrees Celsius.
4. the forming method of MOS transistor according to claim 2, which is characterized in that the parameter of the wet-etching technique are as follows:
For the etching solution used for KOH solution, the mass percent concentration of KOH is 0.1%~40%, etching temperature is 20 degrees Celsius~
50 degrees Celsius.
5. the forming method of MOS transistor according to claim 1, which is characterized in that the material of the coating is silicon.
6. the forming method of MOS transistor according to claim 1, which is characterized in that form the work of each layer of coating
Skill is selective epitaxial growth process.
7. the forming method of MOS transistor according to claim 6, which is characterized in that the selective epitaxial growth work
The parameter of skill are as follows: the gas used is SiH4And H2Cl2One of Si or combinations thereof, the total flow of the gas are 30sccm
~300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.
8. the forming method of MOS transistor according to claim 1, which is characterized in that the number of plies of the coating arrives for 1
4 layers.
9. the forming method of MOS transistor according to claim 1, which is characterized in that when the MOS transistor is p-type
When MOS transistor, the material of the stress material layer is germanium silicon.
10. the forming method of MOS transistor according to claim 1, which is characterized in that when the MOS transistor is N-type
When MOS transistor, the material of the stress material layer is carbon silicon.
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