CN101599429A - Form the side wall method - Google Patents
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- CN101599429A CN101599429A CNA2008101143007A CN200810114300A CN101599429A CN 101599429 A CN101599429 A CN 101599429A CN A2008101143007 A CNA2008101143007 A CN A2008101143007A CN 200810114300 A CN200810114300 A CN 200810114300A CN 101599429 A CN101599429 A CN 101599429A
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- side wall
- wall layer
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Abstract
A kind of formation side wall method comprises the steps: to provide Semiconductor substrate, be formed with grid structure on the described Semiconductor substrate, be formed at the grid structure both sides and on first side wall layer and second side wall layer; On the etching grid structure and Semiconductor substrate on second side wall layer; Second side wall layer of etching grid structure both sides and Semiconductor substrate intersection is to preliminary dimension; Remove on the grid structure and second side wall layer on the Semiconductor substrate.The present invention by with second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to the etch step of preliminary dimension with remove on the grid structure and on the Semiconductor substrate step of the second residual side wall layer separate and carry out, reach the purpose of easy control side wall shape.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation side wall method.
Background technology
Generally all can use the structure of side wall in the production process of semiconductor below 1 micron, side wall generally is used for around polysilicon gate, thereby prevents that more heavy dose of source/too approaching raceway groove of leakage injection from causing generation source/leakage break-through (punch through).
Prior art discloses a kind of method that forms side wall, and the schematic flow sheet with reference to Fig. 1 provides the method that forms side wall comprises:
The first step is at the silicon chip surface silicon dioxide thin film growth; Second step, grown silicon nitride film on silica membrane; The 3rd step, the side wall etching; In the 4th step, repeating step two and three carries out grown silicon nitride film and side wall etching for the second time second time respectively, is the side wall of " D " shape of 500-800 dust until the acquisition width.
In being 200610071764 Chinese patent application, application number can also find more information relevant with technique scheme.
In technique scheme, the silicon nitride film of described silica membrane and growth for the first time constitutes first side wall layer, the silicon nitride film of growth constitutes second side wall layer for the second time, promptly behind growth first side wall layer, second side wall layer, carry out the first step etching and the second step etching at every turn, increase on the one hand processing step, simultaneously can not better controlled have respectively gone on foot the last section shape that stops layer and etching of etching.
Prior art also discloses a kind of technical scheme that forms side wall, with reference to shown in Fig. 2 to 3.At first with reference to Fig. 2, Semiconductor substrate 11 is provided, be formed with grid structure 12 that gate dielectric layer, grid constitute on the described Semiconductor substrate 11, be formed on the grid structure and first side wall layer 13 and second side wall layer 14 of both sides, also form active/drain extension region in 11 at the bottom of the semiconductor of described grid structure 12 both sides,, not shown at this for simplicity of illustration.Described first side wall layer 13 and second side wall layer 14 adopt the dielectric material preparation, at the composite bed (ON) that first side wall layer 13 described in the practical semiconductor technology generally adopts silica and silicon nitride to form successively, described second side wall layer, the 14 general silicon nitrides that adopt.
With reference to Fig. 3, second side wall layer 14 and first side wall layer 13 are carried out etching, this etch step comprises two steps: at first, adopt first etching gas to carry out first etching, described first etching gas is CF
4, CHF
3, O
2And Ar, volume ratio is 40: 80: 20: 250, second side wall layer 14 in this step on main etching semiconductor substrate 11 and the grid structure 12, generally speaking, this step can not removed second side wall layer 14 on conductive substrate 11 and the grid structure 12 totally fully, and second side wall layer of grid structure 12 both sides forms " D " shape; Then, adopt second etching gas to carry out second etching, described second etching gas is CH
3F, O
2And Ar, volume ratio is 20: 80: 100.In this second etch step, grid structure 12 both sides of wanting on the one hand the not removal in etching first etch step to put in place contact second side wall layer 14 of position to preliminary dimension with Semiconductor substrate, also to remove second residual on Semiconductor substrate 11 and the grid structure 12 side wall layer 14 simultaneously, silicon oxide layer in removing part first side wall 13 also rests on the silicon oxide layer in first side wall 13, after second etching, described first side wall layer 13 becomes 13a, and second side wall layer 14 becomes 14a.
But, in technique scheme, the selection ratio that carries out second etching is difficult to control, can't both satisfy grid structure 12 both sides were contacted second side wall layer 14 of position to preliminary dimension with Semiconductor substrate, also to remove second residual on Semiconductor substrate 11 and the grid structure 12 side wall layer 14, on the silicon oxide layer in resting on first side wall 13.In the actual etching technics, understand contact with Semiconductor substrate first side wall layer 13 of position of over etching grid structure 12 both sides usually, as position in the frame of broken lines among Fig. 3.
Provide electronic scanning Electronic Speculum (SEM) test result of the side wall that adopts the technique scheme preparation as Fig. 4, in Fig. 4 in the zone 400 the over etching phenomenon appears, what make the grid structure both sides covers on the Semiconductor substrate the local attenuation of first side wall layer, like this in follow-up formation source/drain electrode technology, can influence source/drain electrode and inject the degree of depth of ion, thereby influence the performance of semiconductor device.
Summary of the invention
The problem that the present invention solves provides a kind of method that forms side wall, avoids the inhomogeneous over etching phenomenon that causes the grid structure both sides of etching in the formation side wall technology of prior art.
For addressing the above problem, the invention provides a kind of formation side wall method, comprise the steps: to provide Semiconductor substrate, be formed with grid structure on the described Semiconductor substrate, be formed at the grid structure both sides and on first side wall layer and second side wall layer, described first side wall layer contains silicon nitride layer; On the etching grid structure and Semiconductor substrate on second side wall layer; Second side wall layer of etching grid structure both sides and Semiconductor substrate intersection is to preliminary dimension; Remove on the grid structure and second side wall layer on the Semiconductor substrate and the silicon nitride layer in first side wall layer.
Alternatively, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate comprise CF
4With CHF
3, CH
2F
2Or CH
3Arbitrary combination among the F.
Alternatively, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate comprise CHF
3With CF
4, its range of flow is respectively 65 to 100sccm and 30 to 50sccm.
Alternatively, described CHF
3With CF
4Volume ratio is 1.6 to 2.5.
Alternatively, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate also comprise Ar, the range of flow of described Ar is 50 to 70sccm.
Alternatively, second side wall layer of described etching grid structure both sides and Semiconductor substrate intersection to the gas of preliminary dimension comprises O
2And CHF
3, its range of flow is respectively 20 to 30sccm and 110 to 140sccm.
Alternatively, described O
2And CHF
3Volume ratio be 1/4.6 to 1/5.5.
Alternatively, on the described removal grid structure and the etching gas of second side wall layer on the Semiconductor substrate comprise CH
3F and O
2, its range of flow is respectively 180 to 220sccm and 100 to 150sccm.
Alternatively, described CH
3F and O
2Volume ratio be 1.4 to 1.8.
Alternatively, second side wall layer of described etching grid structure both sides and Semiconductor substrate intersection is to the gas of preliminary dimension or remove on the grid structure and second side wall layer on the Semiconductor substrate and the etching gas of the silicon nitride layer in first side wall layer also comprise He, and the range of flow of described He is 150 to 250sccm.
Alternatively, described first side wall layer is the composite bed that silica, silicon nitride are formed, and described second side wall layer is a silicon nitride.
Compared with prior art, the technical program has the following advantages: by with second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to the etch step of preliminary dimension with remove on the grid structure and on the Semiconductor substrate residual second side wall layer and the silicon nitride layer step in first side wall layer separate and carry out, reach the purpose of easy control side wall shape.
Simultaneously, the technical program can weaken the physical bombardment effect by the content of reduction Ar on the etching grid structure and in the second side wall layer step on the Semiconductor substrate, thus the final section after the better controlled etching.
The technical program at second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to preliminary dimension and remove on the grid structure and second side wall layer on the Semiconductor substrate and expose and adopt He to replace the Ar of prior art in the first side wall layer step, can weaken the physical bombardment effect, thereby the selection that improves etching is than the purpose that reaches final control etching profile.
Description of drawings
Fig. 1 is the schematic flow sheet of the formation side wall of prior art;
Fig. 2 to Fig. 3 is the structural representation of the formation side wall of prior art;
Fig. 4 is the result who adopts the side wall of electronic scanner microscope test prior art formation;
Fig. 5 is the schematic flow sheet of the formation side wall of a specific embodiment of the present invention;
Fig. 6 to 9 is structural representations of formation side wall of the present invention;
Figure 10 is the electronic scanner microscope test result that adopts the side wall of technology formation of the present invention.
Embodiment
The present invention by with second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to the etch step of preliminary dimension with remove on the grid structure and on the Semiconductor substrate residual second side wall layer and the silicon nitride layer step in first side wall layer separate and carry out, reach the purpose of easy control side wall shape.
Simultaneously, the present invention can weaken the physical bombardment effect by the content of reduction Ar on the etching grid structure and in the second side wall layer step on the Semiconductor substrate, thus the final section after the better controlled etching.
The present invention at second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to preliminary dimension and remove on the grid structure and second side wall layer on the Semiconductor substrate and expose and adopt He to replace the Ar of prior art in the first side wall layer step, can weaken the physical bombardment effect, thereby the selection that improves etching is than the purpose that reaches final control etching profile.
The present invention at first provides a kind of method that forms side wall, as shown in Figure 5, provide the schematic flow sheet of the formation side wall of a specific embodiment of the present invention, comprise: execution in step S11, Semiconductor substrate is provided, be formed with grid structure on the described Semiconductor substrate, be formed at the grid structure both sides and on first side wall layer and second side wall layer, contain silicon nitride layer in described first side wall layer; Execution in step S13, on the etching grid structure and Semiconductor substrate on second side wall layer; Execution in step S15, second side wall layer of etching grid structure both sides and Semiconductor substrate intersection is to preliminary dimension; Execution in step S17 removes on the grid structure and second side wall layer on the Semiconductor substrate and expose first side wall layer.
Fig. 6 to 9 provides the structural representation of formation side wall of the present invention.At first with reference to Fig. 6, being formed with on the described Semiconductor substrate 11 has gate dielectric layer, grid structure 12 that grid constitutes, is formed on the grid structure and first side wall layer 13 and second side wall layer 14 of both sides, contain silicon nitride layer in described first side wall layer 13, also form active/drain extension region in 11 at the bottom of the semiconductor of described grid structure 12 both sides,, not shown at this for simplicity of illustration.
Described first side wall layer 13 and second side wall layer 14 adopt the dielectric material preparation, in practical semiconductor technology, the composite bed (ON) that described first side wall layer 13 generally adopts silica and silicon nitride to form successively, described second side wall layer, the 14 general silicon nitrides that adopt.
With reference to Fig. 7, on the grid structure and Semiconductor substrate on second side wall layer 14 carry out first etching, the gas of described first etching comprises CF
4With CHF
3, CH
2F
2Or CH
3Arbitrary combination among the F.
As an optimization embodiment of the present invention, the gas of described first etching comprises CHF
3With CF
4, its range of flow is respectively 65 to 100sccm and 30 to 50sccm, described CHF
3With CF
4Volume ratio is 1.6 to 2.5.CHF
3Can be for 70,80,90sccm, described CF
4Correspondence can be for 35,45,48sccm.
On the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate also comprise Ar, the range of flow of described Ar is 50 to 70sccm, can be for 55,60,68sccm.
On the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate also comprise O
2, its range of flow is 15 to 40sccm, can be for 25,30,38sccm.In first etching process, the air pressure in the chamber is 25 to 35mTorr (1mTorr=133.3Pa)
As an embodiment of present embodiment, the gas of described first etching is CF
4, CHF
3, O
2And Ar, its range of flow is respectively 45,90,38,50,68sccm.Through after this first etching, remove on the grid structure 12 and second side wall layer 14 of the overwhelming majority on the Semiconductor substrate 11, simultaneously, on etching grid structure 12 and in second side wall layer 14 of the overwhelming majority on the Semiconductor substrate 11, also remove the part of second side wall layer 14 of grid structure 12 both sides, form
The second side wall layer 14a of shape.
Compared with prior art, reduce the flow of Ar in the second side wall layer process of the present invention on the etching grid structure of first etching and on the Semiconductor substrate, thereby can weaken the final section after the physical bombardment better controlled etching.
With reference to Fig. 8, after carrying out first etching, generally speaking, the second side wall layer size h of grid structure both sides and Semiconductor substrate intersection is generally still undesirable, the size of second side wall layer of grid structure both sides and Semiconductor substrate intersection can influence the degree of depth that follow-up ion injects, and therefore need carry out second to second side wall layer of grid structure both sides and Semiconductor substrate intersection is etched to preliminary dimension.
The gas of described second etching comprises O
2And CHF
3, its range of flow is respectively 20 to 30sccm and 110 to 140sccm, described O
2And CHF
3Volume ratio be 1/4.6 to 1/5.5.Described O
2Flow can be for 20,25,28sccm, described CHF
3Flow corresponding can be for 110,125,140sccm.
The gas of described second etching also comprises He, and the range of flow of described He is 150 to 250sccm.Can be for 180,220,230sccm.In second etching, the air pressure in the chamber is 35 to 45mTorr.
Optimize embodiment, the gas CHF of described second etching for one as present embodiment
3, O
2, He flow be respectively 25,125,200sccm.After second etching, second side wall layer of etching grid structure both sides and Semiconductor substrate intersection is to preliminary dimension.
The present invention adopts He to replace the Ar of prior art at second side wall layer 14 of etching grid structure 12 both sides and Semiconductor substrate 11 intersections to preliminary dimension, can weaken the physical bombardment effect, thereby the selection that improves etching is than the purpose that reaches final control etching profile.
With reference to Fig. 9, because in first etching, may not remove fully on the Semiconductor substrate 11 and grid structure 12 on second side wall layer 14 and the silicon nitride layer in first side wall layer 13, therefore need carry out second side wall layer on the etching semiconductor substrate and the 3rd etching step of the silicon nitride layer in first side wall layer.In order to ensure removing second side wall layer on Semiconductor substrate 11 and the gate dielectric layer 12 and the silicon nitride layer in first side wall layer fully, in the 3rd etching, to etch away the silicon nitride layer in first side wall layer 13 always, and etch away partial oxidation silicon layer in first side wall layer 13, after the 3rd etching, first side wall layer 13 becomes the first side wall layer 13a.
The gas of described the 3rd etching comprises CH
3F and O
2, its range of flow is respectively 180 to 220sccm and 100 to 150sccm.Described CH
3F and O
2Volume ratio be 1.4 to 1.8.Described CH
3F can be for 190,200,210sccm, correspondingly, and described O
2Can be for 125,135,145sccm.
The gas of described the 3rd etching also comprises He, and its range of flow is 150 to 250sccm.Described He flow can be for 180,200,230sccm.In the 3rd etching, the air pressure in the chamber is 35 to 45mTorr
Optimize embodiment, the gas CH of described the 3rd etching for one as present embodiment
3F, O
2, He flow be respectively 200,125,200sccm.After the 3rd etching, second side wall layer 14 on removal Semiconductor substrate 11 and the gate dielectric layer 12 and the silicon nitride layer in first side wall layer 13.
Equally, the present invention on removing Semiconductor substrate and grid structure 12 second side wall layer and the silicon nitride layer in first side wall layer and expose in the step of the silicon oxide layer in first side wall layer 13 and adopt He to replace the Ar of prior art, can weaken the physical bombardment effect, thereby the selection that improves etching is than the purpose that reaches final control etching profile.
In the above-described embodiment, by with second side wall layer of etching grid structure both sides and Semiconductor substrate intersection to the etch step of preliminary dimension with remove on the grid structure and on the Semiconductor substrate step of residual second side wall layer and the silicon nitride layer in first side wall layer separate and carry out, reach the purpose of easy control side wall shape.
Figure 10 is electronic scanner microscope (SEM) test result that adopts the side wall of technology formation of the present invention.It is the electronic scanner microscope (SEM) of Compass that electronic scanner microscope (SEM) adopts the model of company of Applied Materials (Applied Materials Co.Ltd.).As can be seen, over etching do not occur in the first side wall layer touching position zone 500 among Figure 10 on the side wall of grid structure both sides and the Semiconductor substrate, the validity of lithographic method of the present invention is described.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. one kind forms the side wall method, comprises the steps:
Semiconductor substrate is provided, be formed with grid structure on the described Semiconductor substrate, be formed at the grid structure both sides and on first side wall layer and second side wall layer, described first side wall layer contains silicon nitride layer;
On the etching grid structure and Semiconductor substrate on second side wall layer;
Second side wall layer of etching grid structure both sides and Semiconductor substrate intersection is to preliminary dimension;
Remove on the grid structure and second side wall layer on the Semiconductor substrate and the silicon nitride layer in first side wall layer.
2. formation side wall method according to claim 1 is characterized in that, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate comprise CF
4With CHF
3, CH
2F
2Or CH
3Arbitrary combination among the F.
3. formation side wall method according to claim 1 is characterized in that, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate comprise CHF
3With CF
4, its range of flow is respectively 65 to 100sccm and 30 to 50sccm.
4. formation side wall method according to claim 3 is characterized in that described CHF
3With CF
4Volume ratio is 1.6 to 2.5.
5. formation side wall method according to claim 4 is characterized in that, on the described etching grid structure and the gas of second side wall layer on the Semiconductor substrate also comprise Ar, the range of flow of described Ar is 50 to 70sccm.
6. formation side wall method according to claim 1 is characterized in that, second side wall layer of described etching grid structure both sides and Semiconductor substrate intersection to the gas of preliminary dimension comprises O
2And CHF
3, its range of flow is respectively 20 to 30sccm and 110 to 140sccm.
7. formation side wall method according to claim 6 is characterized in that described O
2And CHF
3Volume ratio be 1/4.6 to 1/5.5.
8. formation side wall method according to claim 1 is characterized in that, on the described removal grid structure and the etching gas of second side wall layer on the Semiconductor substrate comprise CH
3F and O
2, its range of flow is respectively 180 to 220sccm and 100 to 150sccm.
9. formation side wall method according to claim 8 is characterized in that described CH
3F and O
2Volume ratio be 1.4 to 1.8.
10. according to claim 6 or 8 described formation side wall methods, it is characterized in that, second side wall layer of described etching grid structure both sides and Semiconductor substrate intersection is to the gas of preliminary dimension or remove on the grid structure and second side wall layer on the Semiconductor substrate and the etching gas of the silicon nitride layer in first side wall layer also comprise He, and the range of flow of described He is 150 to 250sccm.
11. according to each described formation side wall method in the claim 1 to 6, it is characterized in that described first side wall layer is the composite bed of being made up of silica, silicon nitride successively, described second side wall layer is a silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101143007A CN101599429B (en) | 2008-06-03 | 2008-06-03 | Method for forming side wall |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101143007A CN101599429B (en) | 2008-06-03 | 2008-06-03 | Method for forming side wall |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101599429A true CN101599429A (en) | 2009-12-09 |
| CN101599429B CN101599429B (en) | 2010-11-10 |
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ID=41420811
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101143007A Expired - Fee Related CN101599429B (en) | 2008-06-03 | 2008-06-03 | Method for forming side wall |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437039A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming side wall by uniformly depositing silicon nitride |
| CN102709167A (en) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Side wall structure construction method |
| CN102768953A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Process for eliminating side wall width load effect |
| CN103632943A (en) * | 2012-08-24 | 2014-03-12 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105789129A (en) * | 2016-05-11 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Method for improving profile of side wall of grid electrode, and semiconductor device manufacturing method |
| CN113471049A (en) * | 2021-06-30 | 2021-10-01 | 北京屹唐半导体科技股份有限公司 | Method for processing workpiece, plasma etching machine and semiconductor device |
-
2008
- 2008-06-03 CN CN2008101143007A patent/CN101599429B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437039A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming side wall by uniformly depositing silicon nitride |
| CN102709167A (en) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Side wall structure construction method |
| CN102768953A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Process for eliminating side wall width load effect |
| CN102768953B (en) * | 2012-07-25 | 2014-12-24 | 上海华力微电子有限公司 | Process for eliminating side wall width load effect |
| CN103632943A (en) * | 2012-08-24 | 2014-03-12 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105789129A (en) * | 2016-05-11 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Method for improving profile of side wall of grid electrode, and semiconductor device manufacturing method |
| CN105789129B (en) * | 2016-05-11 | 2019-09-17 | 上海华虹宏力半导体制造有限公司 | Improve the method and method, semi-conductor device manufacturing method of grid curb wall pattern |
| CN113471049A (en) * | 2021-06-30 | 2021-10-01 | 北京屹唐半导体科技股份有限公司 | Method for processing workpiece, plasma etching machine and semiconductor device |
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|---|---|
| CN101599429B (en) | 2010-11-10 |
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