CN104241115A - Processing method for reducing number of deep trench silicon etching needle-shaped defects - Google Patents

Processing method for reducing number of deep trench silicon etching needle-shaped defects Download PDF

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Publication number
CN104241115A
CN104241115A CN201310234893.1A CN201310234893A CN104241115A CN 104241115 A CN104241115 A CN 104241115A CN 201310234893 A CN201310234893 A CN 201310234893A CN 104241115 A CN104241115 A CN 104241115A
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CN
China
Prior art keywords
deep trench
described step
silicon etching
oxide layer
sacrificial oxide
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Pending
Application number
CN201310234893.1A
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Chinese (zh)
Inventor
梁海慧
陈威
顾姗姗
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201310234893.1A priority Critical patent/CN104241115A/en
Publication of CN104241115A publication Critical patent/CN104241115A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers

Abstract

The invention discloses a processing method for reducing the number of deep trench silicon etching needle-shaped defects. The processing method comprises the steps that an oxidation film is grown on the epitaxial layer of a silicon substrate and serves as a mask layer, photoresist serves as a barrier layer, and the oxidation film is etched to be opened till the silicon substrate is exposed; (2) silicon faces are washed with a photoresist removal solution containing H2SO4 and H2O2 and number one standard liquid with the temperature ranging from 60 degrees to 70 degrees to form a preset opening area of a deep trench; (3) oxidation treatment is carried out, and after a sacrificial oxide layer is formed, the sacrificial oxide layer is removed; (4) deep trench silicon etching is carried out; (5) the oxidation film serving as the mask layer is removed. According to the processing method for reducing the number of the deep trench silicon etching needle-shaped defects, the number of the needle-shaped defects in the deep trench silicon etching process can be reduced, and thus the yield of products is increased, and the reliability of the products is improved.

Description

Reduce the processing method of deep trench silicon etching needle shape flaw
Technical field
The present invention relates to a kind of method improving silicon etching needle shape flaw, particularly relate to a kind of processing method reducing deep trench silicon etching needle shape flaw.
Background technology
Deep trench etching is in order to control the suitable degree of depth, need to make hard mask (Hard mask) with certain thickness oxide-film to stop, and open hard mask and need to do barrier layer with photoresistance, in cleaning step after the operation of removing photoresistance particularly before deep trench etching, if cleaning method is improper or surface treatment inadequate, be easy to form needle shape flaw (as Figure 1-4) after deep trench etching.
Therefore, when deep trench silicon etches, if there is no suitable cleaning step before monocrystalline silicon etching, be very easy to find cause by front layer affects residual after the etching, thus the generation of needle shape flaw can be caused, thus, how to reduce the difficult problem that this defect is deep trench silicon etch process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of processing method reducing deep trench silicon etching needle shape flaw.By the method, needle shape flaw in deep trench silicon etching process can be reduced and produce, to improve yield and the reliability of product.
For solving the problems of the technologies described above, the processing method of minimizing deep trench silicon etching needle shape flaw of the present invention, comprises step:
1) on the epitaxial loayer of silicon substrate, growth oxide-film is as mask layer, and using photoresistance (photoresist) as barrier layer, oxide-film etching is opened to silicon substrate;
2) to contain H 2sO 4and H 2o 2removing photoresistance solution and titer cleaning silicon face of 60 ~ 70 DEG C, form the prodefined opening region of deep trench;
3) carry out oxidation processes, after forming sacrificial oxide layer, remove sacrificial oxide layer;
4) deep trench silicon etching is carried out;
5) oxide-film as mask layer is removed.
In described step 1), the growing method of growth oxide-film is the method for hot oxygen or chemical gaseous phase deposition.
Described step 2) in, containing H 2sO 4and H 2o 2removing photoresistance solution in H 2sO 4: H 2o 2volume ratio be generally 5:1, wherein, H 2sO 4mass fraction is adopted to be the H of 49% 2sO 4;
A titer is by NH 4oH, H 2o 2and H 2o formed, and wherein, the volume range of NH4OH is 1/25 ~ 1/7, H 2o 2volume range be 1/7 ~ 4/25, all the other are H 2o.
In described step 3), the temperature of oxidation processes is higher than 800 DEG C, and the thickness of sacrificial oxide layer is greater than 300 dusts; Remove the method for sacrificial oxide layer, comprising: adopt wet liquid medicine to remove sacrificial oxide layer; Wherein, wet liquid medicine, comprising: conventional wet liquid medicine, HF or the BOE(Buffer of Etchant as dilution) liquid etc.
In described step 4), the degree of depth of deep trench is greater than 10 μm.
In described step 5), the method for removal comprises: adopt wet liquid medicine to remove; Wherein, wet liquid medicine, comprising: conventional wet liquid medicine, as HF or the BOE liquid etc. of dilution.
The present invention is before deep trench etching, increase the cleaning of HAPM and after effects on surface carries out oxidation processes (i.e. the optimization of the front cleaning condition of monocrystalline deep trench silicon etching, surface roughness process), the polymer in oxide-film etching can be removed, after repairing the roughness on surface simultaneously, the polymer produced in silicon etching is just not easy at surface aggregation, thus decreases the generation of needle shape flaw.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is existing process chart;
Fig. 2 is the light microscope figure of the needle shape flaw that existing technique produces;
Fig. 3 is the SEM(scanning electron microscopy of the needle shape flaw that existing technique produces) figure;
Fig. 4 is the EDX(energy dispersion X-ray spectrum of the needle shape flaw that existing technique produces) figure;
Fig. 5 is schematic flow sheet of the present invention;
Fig. 6 is flowage structure schematic diagram of the present invention; Wherein, 1 is substrate, and 2 is epitaxial loayer, and 3 is photoresistance, and 4 is oxide-film, and 5 effectively process position for sacrificial oxide layer, A for sacrifice oxidation processes complete after, B be deep trench etching after;
Fig. 7 is after the present invention increases HAPM, thus reduces the distribution map comparison diagram of needle shape flaw at wafer;
Fig. 8 is that the process of roughness difference more easily produces the distribution map of needle shape flaw at wafer; Wherein, testing one is the wafer that surface roughness is little; Test two is the wafer that surface roughness is larger;
Fig. 9 carries out the distribution map of the defect after sacrificing oxidation processes roughness surface at wafer according to the present invention.
Embodiment
The processing method (as seen in figs. 5-6) of minimizing deep trench silicon etching needle shape flaw of the present invention, comprises step:
1) on the epitaxial loayer 2 of silicon substrate 1, using the growth of the method for hot oxygen or chemical gaseous phase deposition as the oxide-film 4 of mask layer, using photoresistance 3(photoresist) as barrier layer, then oxide-film 4 etching is opened to silicon substrate;
2) to contain H 2sO 4and H 2o 2removing photoresistance solution and titer cleaning silicon face of 60 ~ 70 DEG C, after removing photoresistance, form the prodefined opening region of deep trench;
Wherein, containing H 2sO 4and H 2o 2removing photoresistance solution in H 2sO 4: H 2o 2volume ratio be generally 5:1, wherein, H 2sO 4mass fraction is adopted to be the H of 49% 2sO 4;
A titer (APM solution) is by NH 4oH, H 2o 2and H 2o formed, wherein, and NH 4the volume range of OH is 1/25 ~ 1/7, H 2o 2volume range be 1/7 ~ 4/25, all the other are H 2o;
In addition, the flow process of conventional removing photoresistance is H 2sO 4aMP.AMp.Amp H 2o 2+ number titer, and in this step, adopt H 2sO 4aMP.AMp.Amp H 2o 2a titer of+high temperature (60 ~ 70 DEG C) cleans, to alleviate the generation of deep trench silicon etching needle shape flaw;
3) adopt the temperature higher than 800 DEG C to carry out oxidation processes, after formation thickness is greater than the sacrificial oxide layer of 300 dusts, by the wet liquid medicine of routine, sacrificial oxide layer removed by HF or the BOE liquid etc. as dilution;
4) the deep trench silicon etching that the degree of depth is greater than 10 μm is carried out;
5) oxide-film 4 as mask layer is removed with HF or the BOE liquid of dilution.
Operate according to above-mentioned steps, when the degree of depth of groove is greater than 10 μm, the present invention can reduce the generation of deep trench silicon etching needle shape flaw, and existing common process ratio is easier to produce needle shape flaw.Simultaneously, the present invention also finds through experiment: in removal photoresistance 3 process, when using the APM solution of high temperature can greatly reduce the oxide-film 4 of deep trench etching front opening as mask layer the polymer polymer(that remain as shown in Figure 7), thus reduce the generation probability of the needle shape flaw after deep trench etches.
In addition, in Mechanism Validation, find: surface roughness can worsen needle shape flaw further, as shown in Figure 8; Wherein, in Fig. 8, test two solution that makes surface roughening more a kind of than test more than; In test one, the roughness in wafer zone line and crystal round fringes region is respectively 0.136,0.122; In test two, the roughness in wafer zone line and crystal round fringes region is respectively 0.148,0.139; It can thus be appreciated that the roughness of test one will lower than the roughness of test two.Meanwhile, in Fig. 8, test one is the wafer that surface roughness is little, the defect map after silicon etching, and defect random distribution in this test one, does not almost have needle shape flaw; Test two is the wafer that surface roughness is larger, the defect map after silicon etching, in this test two, has serious needle shape flaw in the middle of wafer.
Therefore, surface oxidation treatment was increased before deep trench etching, can the roughness of optimizing surface further, thus after deep trench etching, the generation (as shown in Figure 9) of needle shape flaw can be reduced further, wherein, in Fig. 9, after sacrificing oxidation processes roughness surface, needle shape flaw is not easy out.
Therefore, according to the method described above, the present invention can reduce the generation of needle shape flaw.

Claims (7)

1. reduce a processing method for deep trench silicon etching needle shape flaw, it is characterized in that, comprise step:
1) on the epitaxial loayer of silicon substrate, growth oxide-film is as mask layer, and using photoresistance as barrier layer, oxide-film etching is opened to silicon substrate;
2) to contain H 2sO 4and H 2o 2removing photoresistance solution and titer cleaning silicon face of 60 ~ 70 DEG C, form the prodefined opening region of deep trench;
3) carry out oxidation processes, after forming sacrificial oxide layer, remove sacrificial oxide layer;
4) deep trench silicon etching is carried out;
5) oxide-film as mask layer is removed.
2. the method for claim 1, is characterized in that: in described step 1), and the growing method of growth oxide-film is the method for hot oxygen or chemical gaseous phase deposition.
3. the method for claim 1, is characterized in that: described step 2) in, containing H 2sO 4and H 2o 2removing photoresistance solution in H 2sO 4: H 2o 2volume ratio be 5:1, wherein, H 2sO 4mass fraction is adopted to be the H of 49% 2sO 4;
A titer is by NH 4oH, H 2o 2and H 2o formed, wherein, and NH 4the volume range of OH is 1/25 ~ 1/7, H 2o 2volume range be 1/7 ~ 4/25, all the other are H 2o.
4. the method for claim 1, is characterized in that: in described step 3), and the temperature of oxidation processes is higher than 800 DEG C, and the thickness of sacrificial oxide layer is greater than 300 dusts.
5. the method for claim 1, is characterized in that: in described step 3), removes the method for sacrificial oxide layer, comprising: adopt wet liquid medicine to remove sacrificial oxide layer;
Wherein, wet liquid medicine, comprising: HF or the BOE liquid of dilution.
6. the method for claim 1, is characterized in that: in described step 4), and the degree of depth of deep trench is greater than 10 μm.
7. the method for claim 1, is characterized in that: in described step 5), and the method for removal comprises: adopt wet liquid medicine to remove;
Wherein, wet liquid medicine, comprising: HF or the BOE liquid of dilution.
CN201310234893.1A 2013-06-14 2013-06-14 Processing method for reducing number of deep trench silicon etching needle-shaped defects Pending CN104241115A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118901A (en) * 2015-07-29 2015-12-02 湘能华磊光电股份有限公司 Deep groove etching method
CN108203074A (en) * 2016-12-19 2018-06-26 中芯国际集成电路制造(上海)有限公司 A kind of preparation method of semiconductor devices
CN111710602A (en) * 2020-06-10 2020-09-25 上海华力集成电路制造有限公司 Manufacturing method of high-K dielectric layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036495A (en) * 1998-07-21 2000-02-02 Nec Corp Manufacture of semiconductor device
CN1469457A (en) * 2002-06-29 2004-01-21 ����ʿ�뵼�����޹�˾ Method for producing semiconductor device
CN1641854A (en) * 2004-01-14 2005-07-20 株式会社瑞萨科技 Method of manufacturing a semiconductor device
CN103137463A (en) * 2011-11-30 2013-06-05 上海华虹Nec电子有限公司 Solution for detect of needle shape in deep groove etching process

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036495A (en) * 1998-07-21 2000-02-02 Nec Corp Manufacture of semiconductor device
CN1469457A (en) * 2002-06-29 2004-01-21 ����ʿ�뵼�����޹�˾ Method for producing semiconductor device
CN1641854A (en) * 2004-01-14 2005-07-20 株式会社瑞萨科技 Method of manufacturing a semiconductor device
CN103137463A (en) * 2011-11-30 2013-06-05 上海华虹Nec电子有限公司 Solution for detect of needle shape in deep groove etching process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118901A (en) * 2015-07-29 2015-12-02 湘能华磊光电股份有限公司 Deep groove etching method
CN105118901B (en) * 2015-07-29 2017-08-25 湘能华磊光电股份有限公司 A kind of deep trouth engraving method
CN108203074A (en) * 2016-12-19 2018-06-26 中芯国际集成电路制造(上海)有限公司 A kind of preparation method of semiconductor devices
CN108203074B (en) * 2016-12-19 2020-07-07 中芯国际集成电路制造(上海)有限公司 Preparation method of semiconductor device
CN111710602A (en) * 2020-06-10 2020-09-25 上海华力集成电路制造有限公司 Manufacturing method of high-K dielectric layer

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