JP2011124354A - Inspection method of soi wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of discriminating impurity metal and stacking fault present in a support substrate layer of an SOI wafer for inspection with ease and at a low cost. <P>SOLUTION: An SIMOX wafer (10) includes an embedded oxide film layer (12) on a support substrate layer (13), and an SOI layer (11) on the embedded oxide film layer (12). In a method of inspecting defect in the support substrate layer (13), the SOI layer (11) and the oxide film layer (12) are removed. Then, the support substrate layer (13) is selectively etched using etching liquid so that a defect present on its surface appears as an etch pit. The size of the etch pit is measured with a counter. If the size measures 1 μm or larger, the cause thereof is determined to be an impurity metal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an SOI wafer inspection method for detecting defects and / or impurity metals in an SOI wafer, and in particular, an SOI wafer for selectively detecting stacking faults and nickel in an SOI wafer obtained by the SIMOX method. This relates to the inspection method.

In recent years, an SOI (Silicon on Insulator) structure has attracted attention for further improvement in device performance. As shown in FIG. 1, a wafer 10 having an SOI structure (hereinafter referred to as “SOI wafer”) 10 includes an oxide film layer 12 made of silicon dioxide (SiO ₂ ) on a support substrate layer 13 made of silicon, and silicon. SOI layers (active layers) 11 are sequentially formed, and parasitic capacitance generated between the element and the substrate in a normal silicon substrate is suppressed. Realization of power consumption can be expected.

  In such an SOI wafer, recently, for example, an electrostatic discharge (ESD) element has been proposed between the oxide film layer 12 and the support substrate layer 13 (see, for example, Patent Document 1). It is expected that opportunities to form elements not only on the surface of the SOI wafer 10 but also in the region below the oxide film layer 12 will increase in the future.

  As a method for manufacturing an SOI wafer, there are mainly a bonding method and a SIMOX (Separation by IM planted Oxygen) method.

  In the bonding method, the surface-oxidized silicon support substrate is bonded to the active substrate for manufacturing the device, and heat treatment is performed at a high temperature of about 1200 ° C. to bond the oxide film of the support substrate and the silicon of the active substrate. This is a method of manufacturing an SOI wafer.

  On the other hand, in the SIMOX method, oxygen ions are implanted into a polished wafer (PW) and then high-temperature annealing is performed to form a buried oxide (BOX) layer at a predetermined depth from the wafer surface. This is a method for manufacturing an SOI wafer. The SIMOX method has a simpler manufacturing process than the bonding method, and is advantageous in terms of cost.

  In an SOI wafer obtained by the SIMOX method (hereinafter referred to as “SIMOX wafer”), stacking faults are formed in the support substrate layer under the BOX layer. Such stacking faults cause inconsistencies in the mask alignment.

  Moreover, in SIMOX wafers, metal contamination such as nickel in the annealing process of the manufacturing process has been a problem for a long time. As described above, when a device is formed below the BOX layer, impurity metal such as nickel or stacking faults in the support substrate layer generates a leakage current, so that device performance is deteriorated. Therefore, it is necessary to improve the quality by reducing metal contamination and stacking faults in the mass production process of SIMOX wafers. To that end, it is possible to inspect the impurity metals present in the SIMOX wafer and stacking faults separately. At the same time, it is desired to establish a method that can be easily and inexpensively inspected.

  Conventionally, inspection of such defects has been performed mainly by a transmission electron microscope (TEM) (see, for example, Patent Document 2).

US Pat. No. 6,074,899 JP 2003-347527 A

  However, in the inspection method using TEM, it is difficult to observe the impurity metal before inspecting the impurity metal such as nickel and stacking faults.

  In addition, in order to inspect defects by TEM, it is necessary to thin the sample necessary for analysis by FIB method, ion milling method, electrolytic polishing method, etc., which requires much time, labor and cost And In fact, since it takes about one week to inspect per sample, it is difficult to say that it is suitable for the inspection method in the mass production process of SIMOX wafers.

  Accordingly, an object of the present invention is to provide a method capable of distinguishing and detecting impurity metals and stacking faults present in a supporting substrate layer in an SOI wafer at a low cost.

  As a result of earnestly examining the inspection method for solving the above problems, the inventor can identify the impurity metal and the stacking fault in the support substrate layer of the SOI wafer based on the size of the etch pit formed by the selective etching. I found out. In addition, stacking faults are localized on the oxide layer side of the support substrate layer, while the impurity metal is found to extend into the support substrate layer, and is selected by removing the support substrate layer to a predetermined depth. The inventors have conceived that selective detection of an impurity metal and a defect is possible by performing an etching process, and the present invention has been completed.

  That is, the method for inspecting an SOI wafer according to the present invention detects an impurity metal and a stacking fault in a support substrate layer in an SOI wafer in which an oxide film layer and an SOI layer are sequentially formed on the support substrate layer. Removing the oxide film layer, then subjecting the support substrate layer to selective etching, measuring the size of the etch pits revealed on the support substrate layer, and detecting impurity metals and stacking faults from the obtained size It is a feature. Thereby, the impurity metal and stacking fault which exist in the support substrate layer of a SIMOX wafer can be distinguished and inspected simply and at low cost.

  The method for inspecting an SOI wafer according to the present invention includes the steps of detecting the impurity metal in the support substrate layer in the SOI wafer in which the oxide film layer and the SOI layer are sequentially formed on the support substrate layer. And then removing the support substrate layer over a thickness of 330 angstroms or more, and then subjecting the support substrate layer to selective etching, measuring the number of etch pits revealed on the support substrate layer, and removing the impurity metal It is characterized by detecting. Thereby, the impurity metal which exists in the support substrate layer of a SIMOX wafer can be test | inspected simply and at low cost.

  In addition, the method for inspecting an SOI wafer according to the present invention includes a first SOI for detecting impurity metals and stacking faults in a support substrate layer in an SOI wafer in which an oxide film layer and an SOI layer are sequentially formed on the support substrate layer. After the SOI layer and the oxide film layer are removed from the wafer, the support substrate layer is selectively etched to measure the number of etch pits that are exposed on the support substrate layer, and then the second SOI wafer. In contrast, after the support substrate layer is removed to a predetermined depth of 330 angstroms or more, the support substrate layer is selectively etched, and the number of etch pits revealed on the support substrate layer is measured. From the number of etch pits on the surface of the support substrate layer of one SOI wafer, at a predetermined depth of the support substrate layer of the second SOI wafer It is characterized in determining the number of stacking faults on the surface of the supporting substrate layer by subtracting the number of Tchipitto. Thereby, the stacking fault which exists in the support substrate layer of a SIMOX wafer can be test | inspected simply and at low cost.

  In the SOI wafer inspection method according to the present invention, the impurity metal is nickel.

  Moreover, it is preferable that the etching solution used for the selective etching is any of a Seco solution, a light solution, a Zirtor solution, and a Sumer solution.

  The SOI layer is preferably removed by any one of alkali etching, SC1 cleaning, cleaning with ozone and hydrofluoric acid.

  The oxide film layer is preferably removed with hydrofluoric acid.

  The support substrate layer is preferably removed by a single wafer washer.

  The number of etch pits is preferably measured by any one of a differential interference microscope, a laser microscope, an atomic force microscope, and a scanning electron microscope.

  According to the present invention, impurity metals and stacking faults present in a support substrate layer of an SOI wafer can be distinguished and inspected easily and at low cost.

It is a figure which shows the structure of an SOI wafer. (A) The photograph of the etch pit obtained by Seco etching, and (b) The figure which shows the size distribution of the obtained etch pit. (A) to (d) are a SIMOX sample that does not have an IG layer, a SIMOX sample that has an IG layer, a PW sample that has undergone an annealing process that does not have an IG layer, and an annealing process that has an IG layer. It is a figure which shows the size distribution of the etch pit in the given PW sample. It is a figure which shows the relationship of (a) depth and the density of an etch pit in the support substrate layer of a SIMOX wafer, and (b) depth and the size distribution of an etch pit. It is a figure which shows the flowchart of the method of distinguishing and inspecting the impurity metal and stacking fault in the support substrate of the SIMOX wafer by the selective etching method of this invention. It is a figure which shows the flowchart of the method of test | inspecting the impurity metal in the support substrate of the SIMOX wafer by the selective etching method of this invention. It is a figure which shows the flowchart of the method of test | inspecting the stacking fault in the support substrate layer of the SIMOX wafer by the selective etching method of this invention.

  Hereinafter, a method for inspecting an SOI wafer according to the present invention will be described with reference to the drawings.

  Here, the experimental results that led to the present invention will be described in detail. First, after removing the SOI layer with 8 mol / l potassium hydroxide aqueous solution, the BOX layer was removed with 10% hydrofluoric acid, and then 0.15 mol / l potassium dichromate, 50% hydrofluoric acid, and pure Etch pits are formed on the surface of the support substrate layer by using a Seco solution mixed with water at a volume ratio of 1: 2: 3 for 30 minutes to form etch pits on the support substrate surface (for example, KS Olympus / Nireco). Automatic defect inspection The number and size of etch pits obtained by the apparatus (counter) were measured.

  FIG. 2A is a photograph of the support substrate layer surface observed with a differential interference microscope, which is one of optical microscopes, after the support substrate layer surface has been subjected to secco etching. As shown in the figure, the etch pits were observed as black dots, and the number and size thereof were measured with a counter.

  FIG. 2B is a histogram showing the relationship between the measured size and number of etch pits. As shown in the figure, a size distribution having a peak at a position of 0.8 to 1.0 μm was obtained. This size distribution has an asymmetric structure with respect to the peak, and since there are many etch pits on the size side smaller than the peak position, two or more types of defects may be involved. There are mainly two types of defects to be measured: stacking faults that occur during the formation of the BOX layer, and nickel that is implanted due to contamination in the annealing process.

  Therefore, an experiment was conducted to identify the above measured defects. That is, FIG. 3 is a diagram showing the relationship between the presence / absence of an intrinsic gettering (IG) layer and the etch pit size distribution. Two samples, a SIMOX wafer sample (hereinafter referred to as “SIMOX sample”) and a polished wafer sample (hereinafter referred to as “PW sample”) were prepared for comparison. Since neither nickel nor stacking faults exist in the PW sample, what size distribution does the defect caused by nickel have when the PW sample is annealed to cause contamination by nickel? Revealed.

  FIGS. 3A to 3D show a SIMOX sample that does not have an IG layer, a SIMOX sample that has an IG layer, a PW sample that has undergone an annealing process that does not have an IG layer, and an annealing that has an IG layer. The size distribution of the etch pit in the processed PW sample is shown. Note that the size distribution of the etch pits in FIG. 3A is the same as that in FIG.

  First, when attention is paid to the result in the PW sample subjected to the annealing treatment not having the IG layer shown in FIG. 3C, it can be seen that a peak exists at a position of 0.8 to 1.0 μm. Since the PW sample in FIG. 3C is contaminated with nickel in the annealing process, this peak is attributed to nickel. This is apparent from the fact that the defect itself disappears in the PW sample having the IG layer of FIG.

  Looking at FIG. 3 (a), the peak located at 0.8 to 1.0 μm identified as being attributable to nickel in FIG. 3 (c) also exists in FIG. 3 (a). Therefore, the peak located at 0.8 to 1.0 μm in the SIMOX sample can be identified as being attributable to nickel.

  Looking at FIG. 3 (b), the defects caused by the nickel present in FIG. 3 (a) have disappeared due to the presence of the IG layer, and instead a new size having a peak at 0.4 to 0.6 μm. Distribution appears. That is, the size distribution of FIG. 3A has only one peak at first glance, but the size distribution having a peak at a position of 0.8 to 1.0 μm and 0.4 to 0.6 μm due to nickel. It turns out that it is what added the size distribution which has a peak in a position. In the newly appearing size distribution, it can be seen that the size of the etch pit is less than 1 μm at the maximum.

  The defect that is the origin of the peak located at 0.4 to 0.6 μm is highly likely to be a stacking fault, but this peak will be examined together with further inspection results.

FIG. 4A is a diagram showing the relationship between the depth from the surface of the support substrate layer and the density of etch pits. Etch pits are detected by removing the SOI layer and the BOX layer from the SIMOX wafer, then etching the support substrate layer in a depth direction from the surface by 330 mm using a single wafer cleaning machine, and then performing seco etching under the above conditions. I have done it after. The figure shows that the allowance for etching of the support substrate layer is 0, that is, the number of etch pits is about 1.2 × 10 ⁷ / cm ³ on the surface of the support substrate layer, while the depth from the interface is In the case of 330 mm, it is about 9.0 × 10 ⁶ / cm ³ , and it can be seen that it is substantially constant even in a deeper region.

  FIG. 4B is a diagram showing the relationship between the depth from the surface of the support substrate layer and the size distribution of the etch pits. FIG. 4B-1 shows the size distribution for the SIMOX sample in the same manner as FIGS. 2B and 3A, but the positions of 0.4 to 0.6 μm and 1.2 to 1.4 μm. Two distinct peaks were observed, and this difference in size distribution is thought to be due to a difference in the amount of nickel contamination in the annealing furnace. 4 and 3, the peak located at 1.2 to 1.4 μm is attributed to nickel, and the peak located at 0.4 to 0.6 μm is considered to be attributable to stacking faults. .

  Paying attention to the peak located at 1.2 to 1.4 μm, as the depth from the surface of the supporting substrate layer increases, the peak size decreases and slightly shifts in the direction of smaller size, and the depth is 1980 mm. In the region, it is located at 0.8 to 1.0 μm. This peak shift is presumably because the nickel cluster size decreases with depth.

  On the other hand, the peak located at 0.4 to 0.6 μm is present at the same position as in FIG. 3B without changing the peak position, and in a region deeper than 330 mm from the support substrate layer surface. Does not exist. That is, it can be seen that the defect that is the origin of the peak located at 0.4 to 0.6 μm exists only in the vicinity of the interface between the BOX layer and the support substrate layer. This peak is likely due to stacking faults, and if so, the results of FIG. 4B can be well explained as follows.

That is, in a stacking fault having a tetrahedral structure or a pyramid structure, partial dislocations (or complete dislocations obtained by synthesis of partial dislocations) are formed at the boundary between the stacking fault region and the complete crystal region. The surrounding silicon lattice is greatly distorted. When a stacking fault that distorts the surrounding silicon lattice exists in the SIMOX wafer, the interface between the BOX layer and the support substrate layer having a strain distribution due to lattice mismatch rather than a deep region of the support substrate layer in which almost no lattice strain exists. It is more energetically stable to be present in a nearby region (although there is a small degree of lattice mismatch between the SiO ₂ and Si interfaces). That is, if the peak located at 0.4 to 0.6 μm is caused by a stacking fault, it matches the result of FIG. Therefore, in the present invention, the peak located at 0.4 to 0.6 μm is considered to be caused by stacking faults.

  To summarize the above results, among the defects formed in the SIMOX wafer, the peak located at 1.2 to 1.4 μm is caused by nickel, and the peak located at 0.4 to 0.6 μm is a stacking fault. It can be identified as the cause. As shown in FIG. 3B, since the size of the etch pit caused by the stacking fault is less than 1 μm at the maximum, nickel and the stacking fault can be distinguished and detected with the etch pit size of 1 μm as a boundary. That is, the size of the etch pit obtained by selective etching is measured, and when the size of the obtained etch pit is 1 μm or more, it can be detected as being caused by the impurity metal. On the other hand, etch pits having a size of less than 1 μm include those caused by stacking faults.

  FIG. 5 is a flowchart of an inspection method for detecting an impurity metal in a support substrate layer of a SIMOX wafer by the Secco etching method of the present invention. First, in step S1, the SOI layer is removed by a predetermined removal method. As the removal method, for example, alkali etching, SC1 cleaning, or cleaning using ozone and hydrofluoric acid can be selected. As the etching solution in alkali etching, for example, potassium hydroxide aqueous solution or sodium hydroxide aqueous solution is used. can do. In order to remove the BOX layer to be applied next, it is preferable to increase the selection ratio with the BOX layer.

  Next, in step S2, the BOX layer is removed by a predetermined removal method. As a removal method in this case, for example, a removal method using hydrofluoric acid is preferably selected.

  Thereafter, in step S3, selective etching is performed on the support substrate layer having nickel to be inspected using a predetermined etching solution. As an etching solution, a Seco solution, a light solution, a Zirtor solution, a Sumerian solution, or the like can be used. Regarding the Seco solution, the concentration and mixing ratio of potassium dichromate, hydrofluoric acid, and pure water can be selected within a range in which the BOX layer can be removed and the etching rate is acceptable in work. For example, 0.15 mol / l potassium dichromate, 50% strength hydrofluoric acid, and pure water mixed at a volume ratio of 1: 2: 3 can be used. Etching treatment of the support substrate layer with an etching solution such as Seco solution for a predetermined time, for example, 30 minutes, reveals defects in the support substrate layer as etch pits.

  In the seco-etching process, when inspecting a plurality of samples, if the etching rate is high, it becomes difficult to make the etching state for each sample constant, so that the etching quality becomes constant. It is preferable to adjust the ratio of pure water in the etching solution.

  Further, in the above etching process, when the removal allowance of the supporting substrate layer by etching is small, the amount of selective etching is reduced, and it becomes difficult to reveal defects caused by nickel, so the allowance is about 2 μm. It is preferable to provide it.

  Thereafter, in step S4, the number and size of etch pits present on the surface of the support substrate layer that has been revealed by Secco etching are measured by a predetermined counter. As the counter, for example, a differential interference optical microscope, a laser microscope, an atomic force microscope (AFM), a scanning electron microscope (Scanning Electron Microscope, SEM), or the like can be used.

  In the size distribution of etch pits obtained in step S4, the size of 1 μm or more is identified as being attributable to nickel.

If the density of etch pits on the surface of the support substrate layer obtained in step S4 is larger than a predetermined threshold value, it is determined that the same batch of wafers as the SIMOX wafer is inappropriate and should be excluded from the manufacturing process. The IG layer can be formed thicker to reduce the nickel concentration.
Thus, the nickel in the support substrate layer of the SIMOX wafer can be inspected quickly from the size of the etch pit.

  Furthermore, when it is desired to inspect nickel and stacking faults more strictly, the following method is advantageously adapted. That is, from the knowledge in the above experimental results, since stacking faults are localized in the region from the support substrate layer surface to 330 mm, for example, after cleaning the support substrate layer surface by 330 mm or more using a single wafer cleaning machine. By performing the seco etching, only nickel in the support substrate layer can be detected without the need to determine the size of the etch pit.

  On the other hand, stacking faults are localized within a depth region of 330 mm from the surface of the support substrate layer, and the density of defects caused by nickel is constant in a region deeper than 330 mm from FIG. In consideration, only the stacking fault in the support substrate layer is obtained by subtracting the number of etch pits caused by nickel in the region deeper than 330 mm from the surface of the support substrate layer from the number of etch pits in the region within 330 mm from the support substrate layer surface. Can be detected.

Hereinafter, a method of detecting and detecting the impurity metal and the stacking fault more strictly will be described. Note that the same etching solution and cleaning method as those described above can be applied, and description thereof will be omitted.
FIG. 6 is a flowchart of an inspection method for detecting an impurity metal in a support substrate layer of a SIMOX wafer by the Secco etching method of the present invention. First, in step S11, the SOI layer is removed by a predetermined removal method.

  Next, in step S12, the BOX layer is removed by a predetermined removal method. As a removal method in this case, for example, a removal method using hydrofluoric acid is preferably selected.

  Next, in step S13, the support substrate layer is cleaned and removed to a predetermined depth of 330 mm or more by a cleaning method capable of precisely controlling the etching amount.

  Thereafter, in step S14, selective etching is performed using a predetermined etching solution on the support substrate layer having nickel to be inspected.

  In the selective etching process, when a plurality of samples are inspected, if the etching rate is high, it becomes difficult to make the etching state for each sample constant, so that the etching quality becomes constant. It is preferable to adjust the ratio of pure water in the etching solution.

Thereafter, in step S15, the number and size of etch pits existing on the surface of the support substrate layer that has been revealed by selective etching are measured by a predetermined counter.
In this way, nickel in the support substrate layer of the SIMOX wafer can be inspected.

Next, a method for inspecting stacking faults in the support substrate layer of the SIMOX wafer will be described.
FIG. 7 is a flowchart of a method for inspecting a stacking fault in a support substrate layer of a SIMOX wafer by the selective etching method of the present invention. First, two SIMOX wafers are prepared, and in step S21, the SOI layer is removed from both the SIMOX wafers by, for example, alkali etching, SC1 cleaning, or cleaning using ozone and hydrofluoric acid.

  Next, in step S22, the BOX layer is removed from both the SIMOX wafers using, for example, hydrofluoric acid.

  In step S23, selective etching is performed on the support substrate layer of the first SIMOX wafer using a predetermined etching solution.

  Subsequently, in step S24, the number and size of etch pits existing on the surface of the support substrate layer of the first SIMOX wafer that has been revealed by selective etching are determined by a predetermined counter, such as a differential interference optical microscope, laser microscope, AFM, SEM. Etc., and is stored in a memory (not shown) as data on the surface of the support substrate layer.

  Thereafter, in step S25, the supporting substrate layer of the second SIMOX wafer is cleaned and removed to a predetermined depth of 330 mm or more by, for example, a single wafer cleaning machine.

  Thereafter, in steps S26 and S27, the processes of steps S23 and S24 are performed, respectively, and the measured number and size of etch pits are used as data in a predetermined depth region of the support substrate layer of the second SIMOX wafer. Store in a memory (not shown).

  Finally, in step S28, from the number of etch pits on the surface of the support substrate layer of the first SIMOX wafer stored in the memory (not shown), at a predetermined depth of the support substrate layer of the second SIMOX wafer. The number of stacking faults is determined by subtracting the number of etch pits.

Prior to step S23, the support substrate layer may be removed to a depth of less than 330 mm by, for example, a single wafer cleaning machine.
Thus, stacking faults in the support substrate layer of the SIMOX wafer can be inspected.

  In this way, by performing the processing shown in FIG. 5 or FIG. 6 and FIG. 7 on the SIMOX wafer to be inspected, impurity metals and stacking faults existing in the support substrate layer under the BOX layer can be easily and reduced. Inspection can be performed at a low cost, and the inspection time required for one week per sample in the conventional TEM inspection can be reduced to 1/30 days. That is, the impurity metal and the stacking fault in the support substrate layer of the SIMOX wafer can be inspected easily and at low cost.

  In the above inspection, a differential interference microscope is used as a counter when measuring the number of etch pits, but other microscopes can also be used. For example, when a laser microscope or an atomic force microscope (AFM) is used, defect detection sensitivity is improved. On the other hand, the differential interference microscope requires about 1 minute per sample, whereas the laser microscope requires about 5 minutes and the atomic force microscope (AFM) requires 20 minutes.

  As described above, when a laser microscope or AFM is used as a counter, it is advantageous with respect to the detection sensitivity of the defect with respect to the differential interference microscope, but is disadvantageous with respect to the detection time of the defect, and in the mass production process of the SIMOX wafer. An optimal counter is appropriately selected based on the allowable inspection conditions.

  Although the present invention has been described in detail with specific examples, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the scope of the claims of the present invention. For example, it is possible to inspect other impurity metals other than nickel. Therefore, the present invention is not limited to the above embodiment.

  According to the present invention, it is possible to easily and inexpensively inspect impurity metals and stacking faults in a support substrate layer of an SOI wafer, which is useful for quality inspection when mass-producing SOI wafers.

10 SOI wafer 11 SOI layer 12 Oxide film layer 13 Support substrate layer

Claims (9)

  In detecting an impurity metal and a stacking fault in a support substrate layer in an SOI wafer in which an oxide film layer and an SOI layer are sequentially formed on the support substrate layer, the SOI layer and the oxide film layer are removed, and then the support substrate layer A method for inspecting an SOI wafer, wherein selective etching is performed on the support substrate layer, the size of etch pits revealed on the support substrate layer is measured, and impurity metals and stacking faults are detected from the obtained sizes.   In detecting the impurity metal in the support substrate layer in the SOI wafer in which the oxide film layer and the SOI layer are sequentially formed on the support substrate layer, the SOI layer and the oxide film layer are removed, and then the support substrate layer is made 330 angstroms or more. The method for inspecting an SOI wafer, wherein the support substrate layer is subjected to selective etching, the number of etch pits exposed on the support substrate layer is measured, and an impurity metal is detected. .   In detecting an impurity metal and a stacking fault in a support substrate layer in an SOI wafer in which an oxide film layer and an SOI layer are sequentially formed on the support substrate layer, the SOI layer and the oxide film layer are detected with respect to the first SOI wafer. Then, the support substrate layer is subjected to selective etching, the number of etch pits that are exposed on the support substrate layer is measured, and then the support substrate layer is formed to have a thickness of 330 Å or more with respect to the second SOI wafer. Then, the support substrate layer is subjected to selective etching, the number of etch pits that are manifested on the support substrate layer is measured, and the surface of the support substrate layer of the first SOI wafer is measured. The support is obtained by subtracting the number of etch pits at a predetermined depth of the support substrate layer of the second SOI wafer from the number of etch pits. Inspection method of an SOI wafer, comprising determining the number of stacking faults in the surface of the plate layer.   The inspection method according to claim 1, wherein the impurity metal is nickel.   The inspection method according to any one of claims 1 to 4, wherein an etching solution used for the selective etching is any one of a Seco solution, a light solution, a Zirtor solution, and a Sumer solution.   The inspection method according to claim 1, wherein the SOI layer is removed by any one of alkali etching, SC1 cleaning, cleaning with ozone and hydrofluoric acid.   The inspection method according to claim 1, wherein the oxide film layer is removed with hydrofluoric acid.   The inspection method according to claim 1, wherein the support substrate layer is removed by cleaning with ozone and hydrofluoric acid or SC1 cleaning.   9. The inspection method according to claim 1, wherein the number of the etch pits is measured by any one of a differential interference microscope, a laser microscope, an atomic force microscope, and a scanning electron microscope. .

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