JP5463884B2 - Crystal defect evaluation method of semiconductor single crystal substrate - Google Patents
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- 239000013078 crystal Substances 0.000 title claims description 161
- 230000007547 defect Effects 0.000 title claims description 107
- 239000000758 substrate Substances 0.000 title claims description 89
- 239000004065 semiconductor Substances 0.000 title claims description 84
- 238000011156 evaluation Methods 0.000 title claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 20
- 229910052739 hydrogen Inorganic materials 0.000 claims description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 19
- 239000001257 hydrogen Substances 0.000 claims description 19
- 238000004140 cleaning Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 229910052785 arsenic Inorganic materials 0.000 claims description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 10
- 238000007689 inspection Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 241000287463 Phalacrocorax Species 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 24
- 230000035945 sensitivity Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000005247 gettering Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
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- 238000003486 chemical etching Methods 0.000 description 1
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Description
本発明は、半導体単結晶基板の欠陥評価に好適な評価方法である。 The present invention is an evaluation method suitable for defect evaluation of a semiconductor single crystal substrate.
近年の半導体素子の高集積化に伴い、半導体単結晶中の結晶欠陥の正確な評価が重要になってきている。 With the recent high integration of semiconductor elements, accurate evaluation of crystal defects in a semiconductor single crystal has become important.
半導体単結晶基板の中でも、低抵抗率基板表面やその内部に存在する欠陥は、ケミカルエッチ法（非特許文献１）や、アングルポリッシュとエッチング法によって顕在化した欠陥を光学顕微鏡により欠陥観察を行う手法、レーザーを使った光学的手法（特許文献１）などによって観察されてきた。このような手法により観察測定される欠陥像は、表面においてはデバイス歩留りに影響するし、内部の欠陥はシリコンウェーハのゲッタリング能力を示す重要なパラメータであり、開発時及び出荷検査時などの品質データとして重要である。 Among semiconductor single crystal substrates, defects present on the surface of the low resistivity substrate or inside thereof are observed by a chemical etching method (Non-patent Document 1) or by an angle polish and etching method. It has been observed by a technique, an optical technique using a laser (Patent Document 1) and the like. The defect image observed and measured by such a method affects the device yield on the surface, and the internal defect is an important parameter indicating the gettering ability of the silicon wafer. It is important as data.
しかし、近年注目されているヒ素やボロン等を高濃度ドープした５ｍΩ・ｃｍ以下といった低抵抗率ウェーハの欠陥については、その欠陥の検出方法が確立されておらず、上記いずれの方法においても検出感度が低く、レーザーを用いた光学的手法においては、レーザー光自身の侵入が妨げられ、観察評価が困難になってきている。
また、ドーパントの種類によっては、ドーパント濃度が高くなるにつれ欠陥サイズが微小となり、検出が困難になることも多く、適切な評価方法が求められてきた。
However, no defect detection method has been established for defects in low-resistivity wafers of 5 mΩ · cm or less that are highly doped with arsenic or boron, which have been attracting attention in recent years. However, in the optical method using a laser, the penetration of the laser beam itself is hindered, making observation evaluation difficult.
In addition, depending on the type of dopant, as the dopant concentration increases, the defect size becomes minute and detection is often difficult, and an appropriate evaluation method has been demanded.
従って、半導体単結晶基板の結晶欠陥を、高感度に検出し精度良く評価することのできる半導体単結晶基板の結晶欠陥評価方法が求められている。 Accordingly, there is a need for a crystal defect evaluation method for a semiconductor single crystal substrate that can detect the crystal defects of the semiconductor single crystal substrate with high sensitivity and accurately evaluate the crystal defects.
本発明は、上記事情に鑑みなされたもので、半導体単結晶基板の結晶欠陥を、高感度に検出し精度良く評価することのできる半導体単結晶基板の結晶欠陥評価方法を提供することを目的としている。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a crystal defect evaluation method for a semiconductor single crystal substrate that can detect a crystal defect of the semiconductor single crystal substrate with high sensitivity and accurately evaluate the crystal defect. Yes.
上記課題を解決するために、本発明によれば、半導体単結晶基板の結晶欠陥評価方法であって、少なくとも、前記半導体単結晶基板を水素雰囲気下８００〜１１００℃で熱処理した後、該熱処理した半導体単結晶基板の表面に顕在化した結晶欠陥の検出を行うことによって、前記半導体単結晶基板の結晶欠陥の評価を行うことを特徴とする半導体単結晶基板の結晶欠陥評価方法を提供する。 In order to solve the above problems, according to the present invention, there is provided a crystal defect evaluation method for a semiconductor single crystal substrate, wherein at least the semiconductor single crystal substrate is heat-treated at 800 to 1100 ° C. in a hydrogen atmosphere, and then the heat treatment is performed. There is provided a crystal defect evaluation method for a semiconductor single crystal substrate, characterized in that the crystal defect of the semiconductor single crystal substrate is evaluated by detecting a crystal defect that is manifested on the surface of the semiconductor single crystal substrate.
このように、半導体単結晶基板を水素雰囲気下８００〜１１００℃で熱処理することによって、半導体単結晶基板の表面に結晶欠陥をピットとして顕在化させることができるため、この顕在化した結晶欠陥を検出することによって、半導体単結晶基板の結晶欠陥の評価を高感度に、精度良く行うことができる。 As described above, by crystallizing the semiconductor single crystal substrate as a pit on the surface of the semiconductor single crystal substrate by heat-treating the semiconductor single crystal substrate at a temperature of 800 to 1100 ° C. in a hydrogen atmosphere, this crystal defect is detected. By doing so, the crystal defect of the semiconductor single crystal substrate can be evaluated with high sensitivity and high accuracy.
また、前記評価する半導体単結晶基板を、低抵抗率のヒ素又はボロンドープシリコンウェーハとすることができる。 The semiconductor single crystal substrate to be evaluated can be a low resistivity arsenic or boron doped silicon wafer.
このように、本発明の半導体単結晶基板の結晶欠陥の評価方法を用いれば、従来の検出方法では感度が低い為に検出方法が確立されていなかったヒ素又はボロンを高濃度ドープした低抵抗率シリコンウェーハの結晶欠陥も、シリコンウェーハ表面にピットとして顕在化させることができるため、精度良く評価することができる。 As described above, by using the crystal defect evaluation method for a semiconductor single crystal substrate according to the present invention, a low resistivity in which arsenic or boron is highly doped, for which the detection method was not established due to low sensitivity in the conventional detection method. Since crystal defects of the silicon wafer can also be manifested as pits on the surface of the silicon wafer, it can be evaluated with high accuracy.
また、前記評価する半導体単結晶基板の表面は、ポリッシュ又は劈開により鏡面とし、その後前記水素雰囲気下８００〜１１００℃での熱処理を行い、前記熱処理した半導体単結晶基板の表面に顕在化した結晶欠陥の検出を行うことが好ましい。 Further, the surface of the semiconductor single crystal substrate to be evaluated is mirror-finished by polishing or cleaving, and then heat treatment is performed at 800 to 1100 ° C. in the hydrogen atmosphere, and crystal defects that are manifested on the surface of the heat-treated semiconductor single crystal substrate It is preferable to detect this.
このように、評価する半導体結晶基板の表面を、ポリッシュ又は劈開により鏡面とすることによって、半導体基板の表面及び内部のいずれをも、より高感度に結晶欠陥を検出することができる。 Thus, by making the surface of the semiconductor crystal substrate to be evaluated a mirror surface by polishing or cleaving, it is possible to detect crystal defects with higher sensitivity on both the surface and the inside of the semiconductor substrate.
また、前記評価する半導体単結晶基板に前記鏡面を形成した後、洗浄を行い、その後前記熱処理を行うことが好ましい。 Moreover, it is preferable that after the mirror surface is formed on the semiconductor single crystal substrate to be evaluated, cleaning is performed, and then the heat treatment is performed.
このように、半導体単結晶基板に鏡面を形成後に洗浄を行い、その後熱処理を行うことによって、異物の除去をすることができるとともに、評価する半導体単結晶基板表面に存在していた結晶欠陥に加えて、表面直下に存在していた結晶欠陥もピットとして顕在化させることができるため、好ましい。 In this way, foreign substances can be removed by performing cleaning after forming a mirror surface on the semiconductor single crystal substrate and then performing heat treatment, and in addition to crystal defects existing on the surface of the semiconductor single crystal substrate to be evaluated. In addition, crystal defects that existed immediately below the surface can be manifested as pits, which is preferable.
また、前記顕在化した結晶欠陥を、走査型電子顕微鏡又は表面欠陥検査装置を用いて検出することが好ましい。 Moreover, it is preferable to detect the manifested crystal defect using a scanning electron microscope or a surface defect inspection apparatus.
このように、顕在化した結晶欠陥を、走査型電子顕微鏡を用いて検出することによって、結晶欠陥の形状、サイズ、組成、結晶欠陥密度等の評価をすることができ、また、表面欠陥検査装置を用いて検出することによって、結晶欠陥密度や分布を短時間で正確に評価することができる。 Thus, by detecting the crystal defects that have become apparent using a scanning electron microscope, the shape, size, composition, crystal defect density, etc. of the crystal defects can be evaluated, and a surface defect inspection apparatus. By detecting using, the crystal defect density and distribution can be accurately evaluated in a short time.
また前記評価する半導体単結晶基板として、エピタキシャル成長用の半導体単結晶基板を評価することができる。 Further, a semiconductor single crystal substrate for epitaxial growth can be evaluated as the semiconductor single crystal substrate to be evaluated.
本発明を用いることにより、低抵抗率の基板が多く用いられるエピタキシャル成長用の半導体単結晶基板を評価すれば、エピタキシャル成長時に形成されるエピタキシャル欠陥を生む積層欠陥核を顕在化させることができる。このため、本発明により評価され、品質基準を満たした半導体単結晶基板は、エピタキシャル成長用の半導体単結晶基板として有用であり、エピタキシャルウェーハの高品質化に資する。 By using the present invention, if a semiconductor single crystal substrate for epitaxial growth in which a low resistivity substrate is often used is evaluated, stacking fault nuclei that cause epitaxial defects formed during epitaxial growth can be made obvious. For this reason, the semiconductor single crystal substrate that is evaluated according to the present invention and satisfies the quality standard is useful as a semiconductor single crystal substrate for epitaxial growth, and contributes to the improvement of the quality of the epitaxial wafer.
以上説明したように、本発明の結晶欠陥評価方法を用いれば、半導体単結晶基板の表面に結晶欠陥をピットとして顕在化させることができるため、この顕在化した結晶欠陥を検出することによって、半導体単結晶基板の結晶欠陥の評価を精度良く行うことができる。特に、従来結晶欠陥検出感度が低い為に検出方法が確立されていなかったヒ素又はボロンを高濃度ドープした低抵抗率シリコンウェーハの結晶欠陥を評価するために本発明は有効である。 As described above, if the crystal defect evaluation method of the present invention is used, crystal defects can be manifested as pits on the surface of the semiconductor single crystal substrate, so that the semiconductor can be detected by detecting the manifested crystal defects. The crystal defects of the single crystal substrate can be accurately evaluated. In particular, the present invention is effective for evaluating crystal defects of a low resistivity silicon wafer doped with a high concentration of arsenic or boron, for which a detection method has not been established due to low crystal defect detection sensitivity.
以下、本発明についてより具体的に説明する。
前述のように、例えば５ｍΩ・ｃｍ以下といった低抵抗率基板表面及び内部に存在する結晶欠陥は、ケミカルエッチ法や光学的手法により観察されてきたが、ヒ素やボロン等を高濃度ドープしたウェーハの結晶欠陥については、結晶欠陥の検出方法が確立されていなかった。従って、半導体単結晶基板の結晶欠陥を高感度に顕在化させることのできる欠陥評価方法が求められていた。
Hereinafter, the present invention will be described more specifically.
As described above, for example, crystal defects existing on the surface and inside of a low resistivity substrate of 5 mΩ · cm or less have been observed by a chemical etch method or an optical method. However, a wafer having a high concentration of arsenic, boron, or the like has been observed. For crystal defects, a method for detecting crystal defects has not been established. Accordingly, there has been a demand for a defect evaluation method capable of revealing crystal defects of a semiconductor single crystal substrate with high sensitivity.
そこで、本発明者は、半導体単結晶基板（特に、５ｍΩ・ｃｍ以下の低抵抗率基板）の結晶欠陥を顕在化させることができる結晶欠陥の評価方法について、以下の検討を行った。
そして、本発明者は鋭意検討を重ねたところ、例え低抵抗率の半導体単結晶基板であっても水素雰囲気下８００〜１１００℃で熱処理することによって、半導体単結晶基板の表面に結晶欠陥をピットとして顕在化させることができ、評価する半導体単結晶基板の表面を、予めポリッシュ（アングルポリッシュを含む）あるいは劈開しておくことで、熱処理後顕在化した結晶欠陥の検出を行うことによって、半導体単結晶基板の表面のみならず内部の結晶欠陥の評価をも行うことができることを見出した。
In view of this, the present inventor conducted the following investigation on a crystal defect evaluation method capable of revealing crystal defects of a semiconductor single crystal substrate (particularly, a low resistivity substrate of 5 mΩ · cm or less).
As a result of extensive studies, the inventor pits crystal defects on the surface of the semiconductor single crystal substrate by performing heat treatment at 800 to 1100 ° C. in a hydrogen atmosphere even if the semiconductor single crystal substrate has a low resistivity. The surface of the semiconductor single crystal substrate to be evaluated is polished (including angle polish) or cleaved in advance to detect crystal defects that have become apparent after heat treatment, thereby allowing the semiconductor single crystal substrate to be revealed. It has been found that not only the surface of the crystal substrate but also internal crystal defects can be evaluated.
以下、本発明の半導体単結晶基板の結晶欠陥評価方法について図１を参照して詳細に説明するが、本発明はこれらに限定されるものではない。 Hereinafter, the crystal defect evaluation method for a semiconductor single crystal substrate of the present invention will be described in detail with reference to FIG. 1, but the present invention is not limited to these.
本発明に係る半導体単結晶基板の結晶欠陥評価方法は、図１に示すように、評価する半導体単結晶基板（図１（Ａ））に、水素雰囲気下８００〜１１００℃の熱処理を行う（図１（Ｄ））ことを特徴とする結晶欠陥評価方法である。このように、評価する半導体単結晶基板を、水素雰囲気下８００〜１１００℃で熱処理することにより、半導体単結晶基板の表面に結晶欠陥をピットとして顕在化させることができる。尚、本発明において半導体単結晶基板の表面とは、半導体単結晶基板の主表面だけではなく、例えば後述するような劈開により現れる表面も含まれる。 In the crystal defect evaluation method for a semiconductor single crystal substrate according to the present invention, as shown in FIG. 1, the semiconductor single crystal substrate to be evaluated (FIG. 1A) is subjected to heat treatment at 800 to 1100 ° C. in a hydrogen atmosphere (FIG. 1). 1 (D)), which is a crystal defect evaluation method. In this way, by subjecting the semiconductor single crystal substrate to be evaluated to heat treatment at 800 to 1100 ° C. in a hydrogen atmosphere, crystal defects can be manifested as pits on the surface of the semiconductor single crystal substrate. In the present invention, the surface of the semiconductor single crystal substrate includes not only the main surface of the semiconductor single crystal substrate but also a surface that appears by cleavage as described later, for example.
従って、半導体単結晶基板表面のみならず内部に存在していた結晶欠陥を検出することができ、評価する半導体単結晶基板の持つゲッタリング能力などに代表されるウェーハの特性評価を詳細に得ることができる。 Therefore, it is possible to detect crystal defects existing inside as well as the surface of the semiconductor single crystal substrate, and to obtain detailed evaluation of the characteristics of the wafer represented by the gettering ability of the semiconductor single crystal substrate to be evaluated. Can do.
評価する半導体単結晶基板としては、特に限定されないが、５ｍΩ・ｃｍ以下といった低抵抗率のヒ素又はボロンドープシリコンウェーハを用いることができる。このような従来の検出方法では感度が低い為に検出方法が確立されていなかった低抵抗率のヒ素又はボロンドープシリコンウェーハについても、本発明の結晶欠陥評価方法を用いれば、結晶欠陥を高感度に検出することができ、精度良く評価することができる。 The semiconductor single crystal substrate to be evaluated is not particularly limited, and an arsenic or boron-doped silicon wafer having a low resistivity of 5 mΩ · cm or less can be used. Even in the case of low resistivity arsenic or boron-doped silicon wafers for which the conventional detection method has not been established due to low sensitivity, the crystal defect evaluation method of the present invention can be used to detect crystal defects with high sensitivity. And can be evaluated with high accuracy.
また、図１に示すように、図１（Ｄ）の水素雰囲気下８００〜１１００℃の熱処理の前に、評価する半導体単結晶基板の表面をポリッシュ（アングルポリッシュを含む）又は劈開により鏡面とすることが好ましい（図１（Ｂ））。半導体単結晶基板の表面を、ポリッシュ又は劈開により鏡面とすることで、基板の表面・内部ともにより高感度に結晶欠陥を検出することができる。 Further, as shown in FIG. 1, before the heat treatment at 800 to 1100 ° C. in the hydrogen atmosphere of FIG. 1D, the surface of the semiconductor single crystal substrate to be evaluated is made into a mirror surface by polishing (including angle polishing) or cleavage. It is preferable (FIG. 1B). By making the surface of the semiconductor single crystal substrate a mirror surface by polishing or cleaving, it is possible to detect crystal defects with high sensitivity both on the surface and inside of the substrate.
また、前記評価する半導体単結晶基板に前記鏡面を形成した後、洗浄を行うことが好ましい（図１（Ｃ））。
ここで行う洗浄としては、過酸化水素をベースとした、Ｈ２Ｏ／Ｈ２Ｏ２／ＮＨ４ＯＨ（ＳＣ−１洗浄）、Ｈ２Ｏ／Ｈ２Ｏ２／ＨＣｌ（ＳＣ−２洗浄）による２段階洗浄を行うことができる。このような洗浄をすることによって、半導体単結晶基板表面がエッチングされ、確実に異物が除去されるとともに、評価する半導体単結晶基板表面に存在していた結晶欠陥に加えて、表面直下に存在していた結晶欠陥も、熱処理した半導体単結晶基板の表面に顕在化させることができるため、より精度良く半導体単結晶基板の評価をすることができる。また、自然酸化膜除去のためにフッ酸を用いた洗浄も行うことができる。
Moreover, it is preferable to perform cleaning after forming the mirror surface on the semiconductor single crystal substrate to be evaluated (FIG. 1C).
As cleaning performed here, hydrogen peroxide based H 2 O / H 2 O 2 / NH 4 OH (SC-1 cleaning), H 2 O / H 2 O 2 / HCl (SC-2 cleaning) Can be performed in two steps. By performing such cleaning, the surface of the semiconductor single crystal substrate is etched and foreign matter is surely removed, and in addition to the crystal defects existing on the surface of the semiconductor single crystal substrate to be evaluated, it exists directly under the surface. Since the crystal defects that have been present can be made visible on the surface of the heat-treated semiconductor single crystal substrate, the semiconductor single crystal substrate can be evaluated with higher accuracy. In addition, cleaning with hydrofluoric acid can be performed to remove the natural oxide film.
その後、図１（Ｄ）の水素雰囲気下８００〜１１００℃の熱処理を行う。使用する熱処理炉については特に限定されず、熱処理条件としては、１００％Ｈ２ガス、又はＨ２を含むＮ２やＡｒとの混合ガス雰囲気下で行うことができ、熱処理時間は２０秒〜３時間とすることができるが、これに限られない。 After that, heat treatment is performed at 800 to 1100 ° C. in a hydrogen atmosphere of FIG. The heat treatment furnace to be used is not particularly limited, and the heat treatment conditions can be performed in a mixed gas atmosphere with 100% H 2 gas or N 2 or Ar containing H 2 , and the heat treatment time is 20 seconds to 3 seconds. It can be time, but is not limited to this.
水素雰囲気下８００〜１１００℃で熱処理することにより、基板表面もしくは表層の欠陥とその他の領域とのエッチングレートの差を利用し、欠陥部のシリコンに結晶方位に沿ったピットが形成されることで、結晶欠陥を高感度に顕在化させることができる。 By performing heat treatment at 800 to 1100 ° C. in a hydrogen atmosphere, a difference in etching rate between the substrate surface or surface layer defects and other regions is used to form pits along the crystal orientation in the silicon of the defect portions. The crystal defects can be revealed with high sensitivity.
そして、該熱処理した半導体単結晶基板の表面に顕在化した結晶欠陥の検出を行うことによって（図１（Ｅ））、前記半導体単結晶基板の結晶欠陥の評価を行うものである（図１（Ｆ））。
この顕在化した結晶欠陥は、走査型電子顕微鏡や表面欠陥検査装置等を用いて検出することができる。走査型電子顕微鏡を用いて検出することによって、結晶欠陥の形状、サイズ、組成、結晶欠陥密度等の分析をすることができ、半導体単結晶基板の持つ品質特性を詳細に評価することができる。また、表面欠陥検査装置（例えば、ＭＡＧＩＣＳ、ＳＰ１、ＳＰ２等）に適合する形状の試料にあっては、このような表面欠陥検査装置を用いることによって、結晶欠陥密度や分布を短時間で正確に分析することができ、ゲッタリング能力等に代表されるウェーハの特性を評価することができる。
Then, the crystal defects of the semiconductor single crystal substrate are evaluated by detecting the crystal defects that are manifested on the surface of the heat-treated semiconductor single crystal substrate (FIG. 1E) (FIG. 1 ( F)).
The actual crystal defects can be detected using a scanning electron microscope, a surface defect inspection apparatus, or the like. By detecting using a scanning electron microscope, the shape, size, composition, crystal defect density, etc. of crystal defects can be analyzed, and the quality characteristics of the semiconductor single crystal substrate can be evaluated in detail. Further, in the case of a sample having a shape suitable for a surface defect inspection apparatus (for example, MAGICS, SP1, SP2, etc.), by using such a surface defect inspection apparatus, the crystal defect density and distribution can be accurately determined in a short time. It is possible to analyze the characteristics of the wafer represented by gettering ability and the like.
また、本発明の結晶欠陥評価方法を用いて顕在化させた結晶欠陥は、エピタキシャル成長時に積層欠陥核となり、エピタキシャル欠陥を生む可能性が高いことが判った。従って、本発明により評価され、品質基準を満たした半導体単結晶基板は、エピタキシャル成長用の半導体単結晶基板として有用であり、また、本発明の評価方法を用いることによりこの積層欠陥核の原因究明にも有用である。 Further, it has been found that the crystal defects revealed by using the crystal defect evaluation method of the present invention are likely to cause a stacking fault nucleus during epitaxial growth and cause an epitaxial defect. Therefore, the semiconductor single crystal substrate that is evaluated according to the present invention and satisfies the quality standard is useful as a semiconductor single crystal substrate for epitaxial growth, and the cause of this stacking fault nucleus is investigated by using the evaluation method of the present invention. Is also useful.
以下、実施例と比較例を示して本発明を具体的に説明するが、本発明はこれらに限定されるものではない。 EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated concretely, this invention is not limited to these.
（実施例１）
評価する半導体単結晶基板として、直径１５０ｍｍ、抵抗率１．５ｍΩ・ｃｍ、＜１００＞のＮ型ヒ素ドープシリコンウェーハを用いた。
このシリコンウェーハをポリッシュ加工し、シリコンウェーハ表面を鏡面とし、その後ＳＣ１洗浄、ＳＣ２洗浄、ＨＦ洗浄を行った。その後水素雰囲気下９００℃で１０分間熱処理を施した。
Example 1
As a semiconductor single crystal substrate to be evaluated, an N-type arsenic doped silicon wafer having a diameter of 150 mm, a resistivity of 1.5 mΩ · cm, and <100> was used.
This silicon wafer was polished and the silicon wafer surface was made into a mirror surface, and then SC1 cleaning, SC2 cleaning, and HF cleaning were performed. Thereafter, heat treatment was performed at 900 ° C. for 10 minutes in a hydrogen atmosphere.
この熱処理したシリコンウェーハを高分解能走査型電子顕微鏡ＳＵ−８００（日立製）を用いて観察し、検出された欠陥像を図２に示す。
更に、上記と同様のポリッシュ加工、洗浄を行い、それぞれ水素雰囲気下８５０℃で６０分、水素雰囲気下９００℃で１０分熱処理を施したＮ型ヒ素ドープシリコンウェーハを、高分解能走査型電子顕微鏡ＳＵ−８００により観察し、検出された欠陥像をもとに欠陥個数を計測し、密度換算したものを図３に示す。
また、上記と同様のポリッシュ加工、洗浄を行い、水素雰囲気下９００℃で１０分熱処理を施したＮ型ヒ素ドープシリコンウェーハをＭＡＧＩＣＳ Ｍ５６４０（レーザーテック社製）を用いて観察し、検出された欠陥分布を図４に示す。
This heat-treated silicon wafer was observed using a high-resolution scanning electron microscope SU-800 (manufactured by Hitachi), and the detected defect image is shown in FIG.
Further, an N-type arsenic-doped silicon wafer, which has been polished and cleaned in the same manner as described above and heat-treated at 850 ° C. for 60 minutes in a hydrogen atmosphere and at 900 ° C. for 10 minutes in a hydrogen atmosphere, is applied to a high-resolution scanning electron microscope SU. FIG. 3 shows a result of measuring the number of defects based on the defect image detected by -800 and converting the density.
Also, the defect distribution detected by observing an N-type arsenic-doped silicon wafer that has been polished and cleaned in the same manner as above and heat-treated at 900 ° C. for 10 minutes in a hydrogen atmosphere using MAGICS M5640 (manufactured by Lasertec). Is shown in FIG.
図２〜図４から明らかのように、評価する半導体単結晶基板を水素雰囲気下で８００〜１１００℃で熱処理することによって、結晶欠陥がピットとして顕在化され、走査型電子顕微鏡や表面欠陥装置等を用いて顕在化した欠陥を高感度に検出することができた。 As apparent from FIGS. 2 to 4, the semiconductor single crystal substrate to be evaluated is heat-treated at 800 to 1100 ° C. in a hydrogen atmosphere, so that crystal defects are manifested as pits, and a scanning electron microscope, surface defect device, etc. It was possible to detect with high sensitivity the defects revealed by using.
（比較例１）
評価する半導体単結晶基板として、実施例と同様のヒ素ドープシリコンウェーハを用い、水素雰囲気下での熱処理を行わずに、シリコンウェーハ表面からレーザー光を入射して結晶欠陥による散乱光を検出したところ、感度が低く結晶欠陥の検出をすることができなかった。
(Comparative Example 1)
As the semiconductor single crystal substrate to be evaluated, the same arsenic-doped silicon wafer as in the example was used, and laser light was incident from the surface of the silicon wafer and the scattered light due to crystal defects was detected without performing heat treatment in a hydrogen atmosphere. The sensitivity was low and the crystal defects could not be detected.
（実施例２〜７、比較例２〜４）
評価する半導体単結晶基板として、直径１５０ｍｍ、抵抗率１．５ｍΩ・ｃｍ、＜１００＞のＮ型ヒ素ドープシリコンウェーハを用いた。
このシリコンウェーハをポリッシュ加工し、シリコンウェーハ表面を鏡面とし、その後ＳＣ１洗浄、ＳＣ２洗浄、ＨＦ洗浄を行った。その後水素雰囲気下で下記表１の熱処理条件で熱処理を施した。各条件で熱処理したＮ型ヒ素ドープシリコンウェーハを、高分解能走査型電子顕微鏡ＳＵ−８００により観察した結果を表１に示す。
(Examples 2-7, Comparative Examples 2-4)
As a semiconductor single crystal substrate to be evaluated, an N-type arsenic doped silicon wafer having a diameter of 150 mm, a resistivity of 1.5 mΩ · cm, and <100> was used.
This silicon wafer was polished and the silicon wafer surface was made into a mirror surface, and then SC1 cleaning, SC2 cleaning, and HF cleaning were performed. Thereafter, heat treatment was performed in a hydrogen atmosphere under the heat treatment conditions shown in Table 1 below. Table 1 shows the results of observation of the N-type arsenic-doped silicon wafer heat-treated under each condition with a high-resolution scanning electron microscope SU-800.
表１により、評価する半導体単結晶基板を水素雰囲気下で８００〜１１００℃で熱処理することによって、結晶欠陥がピットとして顕在化され、走査型電子顕微鏡を用いて顕在化した欠陥を高感度に検出することができた。一方、比較例２〜４では、欠陥を検出することができなかった。 According to Table 1, the crystal single defects are manifested as pits by heat-treating the semiconductor single crystal substrate to be evaluated at 800 to 1100 ° C. in a hydrogen atmosphere, and the defects manifested with a scanning electron microscope are detected with high sensitivity. We were able to. On the other hand, in Comparative Examples 2 to 4, no defect could be detected.
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に含有される。 The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. It is contained in the technical range.
Claims (5)
Examples semiconductor single crystal substrate to be evaluated, according to claim 1 or crystal defect evaluation method of a semiconductor single crystal substrate according to any one of claims 4 and evaluating the semiconductor single crystal substrate for epitaxial growth.
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