JP6713493B2 - Epitaxial silicon wafer manufacturing method and epitaxial silicon wafer - Google Patents

Description

The present invention relates to an epitaxial silicon wafer manufacturing method and an epitaxial silicon wafer.

Conventionally, it is known that transition metals such as Fe, Ni, and Cu inside the epitaxial silicon wafer deteriorate the electrical characteristics of the semiconductor device. Therefore, when handling a silicon wafer, various measures for reducing the pollution source, such as purification of chemicals and gas used and purification of the environment, are being studied.

Further, in addition to these measures against contamination, many studies have been conducted on a gettering technique for preventing a transition metal from entering the device active region.

The intrinsic gettering method (IG method) uses, for example, oxygen dissolved in a CZ silicon wafer (silicon wafer manufactured by the Czochralski method) in a heat treatment in a device manufacturing process to form oxygen precipitate nuclei and oxygen precipitates. The transition metal and the like are captured by growing and using oxygen precipitates (BMD: Bulk Micro Defect) generated inside the silicon wafer (bulk).

The extrinsic gettering method (EG method) traps transition metals and the like due to damage applied to the back surface of a silicon wafer, a polycrystalline film, or the like.

However, with the intrinsic gettering method (IG method), the growth of BMDs formed in bulk is suppressed due to the recent low temperature and short time of the device manufacturing process, and the gettering ability may be insufficient. there were.

Further, in the extrinsic gettering method (EG method), the gettering ability may be reduced due to the reduction of the gettering layer accompanying the thinning of the silicon wafer.

On the other hand, there is a technique of gettering by using a substrate in which an epitaxial layer is grown on a substrate heavily doped with impurities and segregating a transition metal in the highly doped substrate. In particular, it is well known that a p+ substrate heavily doped with a p-type dopant can obtain a sufficient gettering ability (see, for example, Patent Document 1). Further, in the p+ substrate, BMD tends to occur in a large amount in the epitaxial layer growth process, and the gettering ability can be further improved.

JP 2005-317853 A

However, in an n+ substrate heavily doped with an n-type dopant, the generation of BMD is suppressed in the epitaxial layer growth process, and thus the gettering ability sufficient for the latest semiconductor device is not obtained.

Therefore, the present invention can improve the gettering ability and suppress bulk defects caused by precipitates, and a method for producing an epitaxial silicon wafer provided with an n+ substrate, and the gettering ability can be improved. It is an object of the present invention to provide an epitaxial silicon wafer provided with an n+ substrate in which bulk defects caused by precipitates are suppressed.

The gist of the present invention is as follows.
The method for manufacturing an epitaxial silicon wafer according to the present invention,
a silicon wafer preparation step of preparing a silicon wafer having a dopant concentration of the n-type dopant of 1.0×10 ¹⁹ atoms/cm ³ or more;
A rapid thermal annealing step in which the silicon wafer is heat-treated at a heat treatment temperature of 900 to 1300° C. for a heat treatment time of 1 to 300 sec in a gas atmosphere inert to the oxidation of the silicon wafer;
Growing an epitaxial layer on the silicon wafer after performing the rapid thermal annealing step, including an epitaxial growth step,
The dopant concentration of the epitaxial layer is less than 1.0×10 ¹⁹ atoms/cm ³ .

In the method for manufacturing an epitaxial silicon wafer of the present invention, it is preferable that the n-type dopant is one or more dopants of P, As, and Sb.

In the method for manufacturing an epitaxial silicon wafer according to the present invention, the n-type dopant is preferably P.

In the method for manufacturing an epitaxial silicon wafer according to the present invention, the dopant contained in the epitaxial layer is preferably an n-type dopant.

In the method for producing an epitaxial silicon wafer of the present invention, in the rapid thermal annealing step, the purity of the gas inert to the oxidation of the silicon wafer in the gas atmosphere inert to the oxidation of the silicon wafer is 99. It is preferably 999% by volume or more.

In the method for manufacturing an epitaxial silicon wafer according to the present invention, the gas inert to the oxidation of the silicon wafer is preferably any of rare gas, H ₂ gas and N ₂ gas.

In the method for manufacturing an epitaxial silicon wafer according to the present invention, the gas inert to the oxidation of the silicon wafer is preferably Ar gas.

In the method for manufacturing an epitaxial silicon wafer according to the present invention, the thickness of the epitaxial layer grown by the epitaxial growth step is preferably 1 to 150 μm.

The epitaxial silicon wafer of the present invention,
An epitaxial silicon wafer having an epitaxial layer on a silicon wafer,
The dopant concentration of the n-type dopant of the silicon wafer is 1.0×10 ¹⁹ atoms/cm ³ or more,
The dopant concentration of the epitaxial layer is less than 1.0×10 ¹⁹ atoms/cm ³ .

ADVANTAGE OF THE INVENTION According to this invention, the gettering ability can be improved and the bulk defect resulting from a deposit can be suppressed, the manufacturing method of the epitaxial silicon wafer provided with the n+ substrate, and the gettering ability improved. It is also possible to provide an epitaxial silicon wafer provided with an n+ substrate, in which bulk defects caused by precipitates are suppressed.

It is a flow figure of a manufacturing method of an epitaxial silicon wafer concerning one embodiment of the present invention. It is a figure which shows the relationship between a dopant concentration and gettering efficiency with respect to Cu. It is a figure which shows the relationship between a dopant concentration and the density and scattering intensity of Cu precipitates. It is a figure which shows the relationship between a dopant concentration and the density of Cu deposits.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Method of manufacturing epitaxial silicon wafer>
FIG. 1 is a flow chart of a method for manufacturing an epitaxial silicon wafer according to an embodiment of the present invention.
As shown in FIG. 1, in the present embodiment, first, a silicon wafer having a dopant concentration of an n-type dopant of 1.0×10 ¹⁹ atoms/cm ³ or more is prepared (silicon wafer preparation step: step S101).

Here, the silicon wafer can be prepared by using a silicon wafer manufactured by a known method. Although not particularly limited, for example, a single crystal silicon wafer obtained by slicing a single crystal ingot grown by the Czochralski method (CZ method) can be used. The oxygen concentration of the silicon wafer is not particularly limited, but may be, for example, 5×10 ^{17 to} 20×10 ¹⁷ atoms/cm ³ (ASTM F-121-1976). The carbon concentration of the silicon wafer is not particularly limited, but may be, for example, 1×10 ^{15 to} 3×10 ¹⁷ atoms/cm ³ (ASTM F123-1981). Further, the nitrogen concentration of the silicon wafer is not particularly limited, but may be, for example, 1×10 ¹¹ to 1×10 ¹⁵ atoms/cm ³ .

Here, in the present embodiment, the n-type dopant contained in the silicon wafer is preferably one or more of P, As, and Sb, and particularly preferably P. When the silicon wafer has such an n-type dopant with a dopant concentration of 1.0×10 ¹⁹ atoms/cm ³ or more, the resistivity of the silicon wafer can be set to, for example, 0.006 Ω·cm or less. The dopant concentration of the dopant contained in the silicon wafer is preferably 1.0×10 ²⁰ atoms/cm ³ or less.

Next, in the present embodiment, as shown in FIG. 1, a silicon wafer is subjected to a heat treatment for 1 to 300 seconds at a heat treatment temperature of 900 to 1300° C. in a gas atmosphere inert to the oxidation of the silicon wafer. Heat treatment is performed for a time (rapid thermal annealing step: step S102).

Here, in the rapid thermal annealing step (step S102), the heat treatment temperature can be 900 to 1300°C, and preferably 1150 to 1200°C. The heat treatment time can be set to 1 to 300 sec, and is preferably set to 30 to 80 sec.

Further, as the gas inert to the oxidation of the silicon wafer, any of a rare gas, H ₂ gas and N ₂ gas can be used. This is because these gases do not oxidize a silicon wafer to form a silicon oxide film. Furthermore, it is particularly preferable that the gas inert to the oxidation of the silicon wafer is Ar gas. This is because it is inert to silicon itself.
Further, in the rapid thermal annealing step (step S102), the purity of the gas inert to the oxidation of the silicon wafer in the gas atmosphere inert to the oxidation of the silicon wafer is 99.999% by volume or more. Is preferred.

The rapid thermal annealing step (step S102) can be performed using a known rapid thermal annealing device.

Next, in the present embodiment, as shown in FIG. 1, an epitaxial layer is grown on the silicon wafer after the rapid thermal annealing step (step S102) (epitaxial growth step: step S103).

The epitaxial growth can be performed by a known method, for example, a vapor phase growth method. In this case, the growth temperature is not particularly limited, but may be 1000 to 1300° C., for example. The thickness (film thickness) of the epitaxial layer grown by the epitaxial growth process is not particularly limited, but is preferably 1 to 150 μm.

Here, the dopant concentration of the epitaxial layer is less than 1.0×10 ¹⁹ atoms/cm ³ and preferably 5.0×10 ¹⁶ atoms/cm ³ or less. On the other hand, the dopant concentration of the epitaxial layer is preferably 4.0×10 ¹² atoms/cm ³ or more.

Here, in the present embodiment, the dopant included in the epitaxial layer is an n-type dopant. The n-type dopant is preferably any one or more of P, As, and Sb, and particularly preferably P. The resistivity of the epitaxial layer is preferably 0.1 to 1000 Ω·cm. This can ensure the function as a device layer.

Regarding the conductivity type of the epitaxial layer, it is preferable that the epitaxial layer has an epitaxial layer having an n-type dopant. Therefore, the epitaxial layer having an n-type dopant is provided on a silicon wafer having an n-type dopant. It is preferable.
Hereinafter, the function and effect of the method for manufacturing an epitaxial silicon wafer according to this embodiment will be described.

According to the method for manufacturing the epitaxial silicon wafer of the present embodiment, first, the thermal equilibrium concentration of the vacancies inside the n-type silicon wafer is increased by the rapid thermal annealing step (step S102), so that more vacancies are formed inside the wafer. It is possible to improve the gettering ability by causing segregation type gettering due to the reaction between the Cu that has been generated in the vacancy and has entered the holes and the dopant. Further, in the present embodiment, the rapid thermal annealing step (step S102) is performed in a gas atmosphere inert to the oxidation of the silicon wafer, so that a silicon oxide film is not formed on the silicon wafer, and It is possible to suppress the injection of interstitial silicon atoms into the holes. As a result, since the vacancy concentration can be maintained high, the effect of the segregation type gettering can be sufficiently obtained. Therefore, the Cu concentration of the epitaxial layer that is the device layer can be further reduced.
In general, Cu nuclei are negatively charged in n-type silicon, and Cu _i ⁺ aggregates due to Coulomb force, resulting in an increase in precipitate size. However, in the present embodiment, the dopant concentration of the n-type dopant of the silicon wafer is set to 1.0×10 ¹⁹ atoms/cm ³ or more, and the segregation type gettering due to the reaction between Cu and the dopant is used, so that the gettering is performed. Cu is a solid solution in silicon. Therefore, it is possible to suppress excessive Cu precipitation inside the silicon wafer and suppress the generation of bulk defects.
Since the above-described segregation type gettering is not gettering caused by BMD, the effect of process changes such as low temperature/short time heat treatment of the heat treatment process of the device manufacturing process does not affect the gettering ability. Further, the pretreatment (growth heat treatment) in the device manufacturing process for controlling the BMD nucleus and the BMD density becomes unnecessary.
As described above, according to the method for manufacturing an epitaxial silicon wafer of the present embodiment, it is possible to suppress bulk defects caused by precipitates and improve the gettering ability.

In the method for manufacturing an epitaxial silicon wafer of the present invention, as described above, in the rapid thermal annealing step (step S102), the silicon wafer is inert to oxidation in a gas atmosphere which is inert to oxidation. The purity of such a gas is preferably 99.999% by volume or more. This is because the formation of the silicon oxide film is further suppressed and the effect of segregation type gettering can be more reliably and sufficiently obtained by the inert gas being dominant.

<Epitaxial silicon wafer>
An epitaxial wafer according to an embodiment of the present invention has an epitaxial layer on a silicon wafer, and the dopant concentration of the n-type dopant of the silicon wafer is 1.0×10 ¹⁹ atoms/cm ³ or more. The dopant concentration is less than 1.0×10 ¹⁹ atoms/cm ³ .

Here, the n-type silicon wafer is not particularly limited, but may be manufactured by a known method. For example, a single crystal silicon wafer can be obtained by slicing a single crystal ingot grown by the Czochralski method (CZ method). As described above, the oxygen concentration of the silicon wafer is not particularly limited, but may be, for example, 5×10 ^{17 to} 20×10 ¹⁷ atoms/cm ³ (ASTM F-121-1976). The carbon concentration of the silicon wafer is not particularly limited, but may be, for example, 1×10 ^{15 to} 3×10 ¹⁷ atoms/cm ³ (ASTM F123-1981). Further, the nitrogen concentration of the silicon wafer is not particularly limited, but may be, for example, 1.0×10 ^{11 to} 1.0×10 ¹⁵ atoms/cm ³ .

Here, in the present embodiment, the n-type dopant contained in the silicon wafer is preferably any one or more of P, As, and Sb, and particularly preferably P. When the silicon wafer has such an n-type dopant with a dopant concentration of 1.0×10 ¹⁹ atoms/cm ³ or more, the resistivity of the silicon wafer can be set to, for example, 0.006 Ω·cm or less. The dopant concentration of the dopant contained in the silicon wafer is preferably 1.0×10 ²⁰ atoms/cm ³ or less.

As described above, the thickness (film thickness) of the epitaxial layer is not particularly limited, but is preferably 1 to 150 μm. Here, the dopant concentration of the epitaxial layer is less than 1.0×10 ¹⁹ atoms/cm ³ and preferably 5.0×10 ¹⁶ atoms/cm ³ or less. On the other hand, the dopant concentration of the epitaxial layer is preferably 4.0×10 ¹² atoms/cm ³ or more.

Here, in the present embodiment, the dopant included in the epitaxial layer is an n-type dopant. The n-type dopant is preferably one or more of P, As, and Sb, and particularly preferably P. The resistivity of the epitaxial layer is preferably 0.1 to 1000 Ω·cm. Thereby, the function as a device layer can be secured.
In the present embodiment, the dopant contained in the epitaxial layer is an n-type dopant, but the dopant contained in the epitaxial layer may be a p-type dopant in the present invention. In this case, the p-type dopant is preferably one or more of B, Al, and Ga, and particularly preferably B. Also in this case, the resistivity of the epitaxial layer is preferably 0.1 to 1000 Ω·cm.
Regarding the conductivity types of the silicon wafer and the epitaxial layer, it is most preferable that the silicon wafer having the n-type dopant and the epitaxial layer having the n-type dopant are provided on the silicon wafer.

According to the epitaxial silicon wafer of the present embodiment, bulk defects caused by precipitates can be suppressed and gettering ability can be improved.

Hereinafter, examples of the present invention will be described, but the present invention is not limited to the following examples.

Nine types of 200 mm n-type silicon wafers having different dopant species and dopant concentrations were prepared. The specifications of each silicon wafer are shown in Table 1 below.
Each silicon wafer was subjected to a rapid thermal annealing treatment at 1150° C. for 1 min in an Ar atmosphere to remove the BMD nuclei formed during crystal growth.
Next, the silicon wafer surface was made a hydrophilic surface by HF cleaning and HCl/H ₂ O ₂ cleaning with respect to each silicon wafer subjected to the rapid thermal annealing treatment.
Further, 1000 ppm of the metal standard solution was diluted to 10 ppm with 68% HNO ₃ and ultrapure water to prepare a Cu contaminated solution. Each silicon wafer was intentionally contaminated by spin coating contamination method (surface contamination concentration: 1.7×10 ¹³ cm ⁻² ), introduced into a horizontal furnace under a nitrogen atmosphere, and held at 900° C. for 30 minutes to obtain silicon. Heat was diffused inside the wafer.

<<Example 1>> Evaluation of BMD density <Evaluation method>
In order to reveal BMD, the silicon wafer after the rapid thermal annealing treatment was put into a horizontal furnace held at 900° C., heated to 1000° C., and held for 16 hours. After the heat treatment, the sample was cleaved into strips, etched by 2 μm with a light etching solution, and the cross-section etch pit density was measured by observation with an optical microscope.
<Results>
Table 2 below shows the measurement results of the BMD density after the rapid thermal annealing treatment. As shown in Table 2, it was below the lower limit of detection for all silicon wafers. The IG capability of a BMD depends on the density and size of the BMD. Therefore, the BMD surface area was calculated from the measurement result of the etch pit density, and the IG ability of Cu was confirmed. As the mechanism of BMD growth, oxygen diffusion-controlled growth was assumed. The initial radius of BMD was assumed to be 1 nm, and the BMD radius after the rapid thermal annealing treatment was calculated from the oxygen concentration of the silicon wafer used. Table 2 below shows values of 4πNR ² d calculated from the etch pit density (N), the BMD radius (R), and the wafer thickness (d=725 μm). Usually, when the value of 4πNR ² d is 1.0×10 ⁻⁴ or less, it is considered that there is almost no effect on gettering. From these results, it is found that in any silicon wafer, gettering due to BMD occurs. It turned out that there was no effect.
Since the epitaxial growth process is also a kind of rapid thermal annealing process, it was determined that there was no difference in BMD density, Cu gettering efficiency, and Cu precipitation before and after the epitaxial growth process.

<<Example 2>> Cu gettering efficiency <Evaluation method>
The amount of metallic impurities on the surface of the silicon wafer, the surface layer and the bulk was measured by a chemical analysis technique. A drop etching method using a mixed solution of 2% HF/2% H ₂ O ₂ : DE (Drop Etching) was used to recover Cu on the surface of the silicon wafer, and its concentration was measured by Inductively Coupled Plasma Mass Spectrometry (ICP-MS). It was measured. The surface layer of the silicon wafer was etched by a liquid phase etching method: DSE (Drop Sandwich Etching) to a region up to 5 μm of the surface layer using an etching solution in which 38% HF and 68% HNO ₃ were mixed, and then an atomic absorption spectroscopy (AAS) was formed. Then, the Cu concentration was measured. The bulk was evaluated by the total dissolution method: WD (Wafer Digestion) using a mixed solution of 38% HF and 68% HNO ₃ , and the Cu concentration was measured by ICP-MS. The above evaluations were carried out on each of the three silicon wafers shown in Table 1 for every three wafers.
<Results>
The amount of Cu detected from the surface layer and bulk of the silicon wafer does not re-diffuse on the front and back surfaces of the silicon wafer in the process of taking out the silicon wafer from the horizontal furnace at 900°C and cooling it at a rate of 50°C/min, and remains in the bulk. The amount of Cu (amount of remaining bulk). The gettering efficiency was calculated from the following (Equation 1) assuming that the amount of remaining bulk is Cu captured by some gettering site.
(Equation 1) Gettering efficiency (%)=bulk remaining amount/intentional contamination amount×100
Here, the intentional contamination amount indicates the total amount of Cu detected from the front and back surfaces of the silicon wafer, the surface layer, and the bulk.
Table 3 and FIG. 2 show the gettering efficiency of each silicon wafer. High gettering efficiency was obtained with a silicon wafer having a dopant concentration of 1.0×10 ¹⁹ atoms/cm ³ or more. In particular, the gettering efficiency is rapidly increased in a silicon wafer having a dopant concentration of 3.0×10 ¹⁹ atoms/cm ³ or more.

Example 3 Resistivity Dependence of Cu Deposition <Evaluation Method>
The resistivity dependence of Cu precipitation was investigated using a P-doped sample in which the dopant concentration was widely changed to 1.0×10 ¹⁴ −1.0×10 ¹⁹ atoms/cm ³ . Since there is a positive correlation between the scattering intensity and the precipitate size, the density and scattering intensity of the deposit confirmed in the bulk by the infrared scattering tomography were measured after the Cu diffusion heat treatment. In the case of infrared scattering tomography, if the defect density becomes high (1.0×10 ⁸ atoms/cm ³ or more), it becomes difficult to measure the size and density of the defect accurately, so that the spatial resolution becomes higher and the defect density becomes higher. The measurement was carried out by a measurable two-dimensional measurement. The measurement was performed under the conditions of a laser intensity of 100 mW and a scan distance of 500 μm, and a precipitate having a wafer depth of 88.4 to 348.4 μm was observed. However, if the dopant concentration is high, infrared rays cannot be obtained because the infrared rays are absorbed by the silicon wafer. Therefore, the sample after the diffusion heat treatment was etched by 2 μm with a light etching solution, the etch pit density of the cross section was measured by observation with an optical microscope, and the precipitate density by selective etching was also evaluated.
<Results>
FIG. 3 shows the results of the density and scattering intensity of Cu precipitates measured by the infrared scattering tomography. It can be seen that as the dopant concentration increases, the density of Cu precipitates tends to increase and the size of the precipitates tends to decrease. However, at a dopant concentration of 1.0×10 ¹⁸ atoms/cm ³ or higher, no precipitate was detected by infrared scattering tomography measurement because it was affected by infrared absorption. The measurement results of the etch pit density by selective etching are shown in Table 4 and FIG. Similar to the measurement result by the infrared scattering tomography, it was confirmed that the density of Cu precipitates increased in the range of the dopant concentration of 1.0×10 ¹⁴ −1.0×10 ¹⁸ atoms/cm ³ . Further, at a dopant concentration of 1.0×10 ¹⁹ atoms/cm ³ or more, no Cu precipitate was observed even by selective etching.

ADVANTAGE OF THE INVENTION According to this invention, the gettering ability can be improved and the bulk defect resulting from a deposit can be suppressed, the manufacturing method of the epitaxial silicon wafer provided with the n+ substrate, and the gettering ability improved. It is possible to provide an epitaxial silicon wafer provided with an n+ substrate, in which bulk defects caused by precipitates are suppressed.

Claims (6)

a silicon wafer preparing step of preparing a silicon wafer having a dopant concentration of the n-type dopant of 1.0×10 ¹⁹ atoms/cm ³ or more;
Subsequent to the silicon wafer preparation step, the silicon wafer prepared with the silicon wafer is subjected to a heat treatment at a heat treatment temperature of 900 to 1300° C. for a heat treatment time of 1 to 300 seconds in an Ar gas atmosphere, a rapid thermal annealing step. When,
After performing the rapid thermal annealing step, on the silicon wafer on the back surface of which no polysilicon is formed, without polishing the silicon wafer, an epitaxial layer is grown, including an epitaxial growth step,
The method of manufacturing an epitaxial silicon wafer, wherein the dopant concentration of the epitaxial layer is less than 1.0×10 ¹⁹ atoms/cm ³ . The method for producing an epitaxial silicon wafer according to claim 1, wherein the n-type dopant is one or more dopants selected from P, As, and Sb. The method for manufacturing an epitaxial wafer according to claim 1, wherein the n-type dopant is P. The method for manufacturing an epitaxial wafer according to claim 1, wherein the dopant contained in the epitaxial layer is an n-type dopant. The method for producing an epitaxial silicon wafer according to claim 1, wherein in the rapid thermal annealing step, a purity of the Ar gas in an Ar gas atmosphere is 99.999% by volume or more. The method for manufacturing an epitaxial silicon wafer according to claim 1, wherein the epitaxial layer grown by the epitaxial growth step has a thickness of 1 to 150 μm.

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