CN101599429B - Method for forming side wall - Google Patents

Method for forming side wall Download PDF

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CN101599429B
CN101599429B CN 200810114300 CN200810114300A CN101599429B CN 101599429 B CN101599429 B CN 101599429B CN 200810114300 CN200810114300 CN 200810114300 CN 200810114300 A CN200810114300 A CN 200810114300A CN 101599429 B CN101599429 B CN 101599429B
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spacer layer
semiconductor substrate
gate structure
etching
layer
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CN 200810114300
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Chinese (zh)
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CN101599429A (en )
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孙武
王新鹏
韩宝东
韩秋华
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中芯国际集成电路制造(北京)有限公司
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Abstract

The invention relates to a method for forming a side wall, which comprises the following steps: providing a semiconductor liner, wherein the semiconductor liner is provided with a grid structure, and first side wall layers and second side wall layers formed on two sides of the grid structure and on the grid structure; etching the second side wall layers on the grid structure and the semiconductorliner; etching the second side wall layer at the joint of two sides of the grid structure and the semiconductor liner to a preset size; and removing the second side wall layers on the grid structure and the semiconductor liner. The invention achieves the purpose of easily controlling the shape of the side wall through etching the second side wall layer at the joint of two sides of the grid structure and the semiconductor liner to the preset size and removing the second side wall layers remained on the grid structure and the semiconductor liner.

Description

形成侧墙方法 The method of forming spacers

技术领域 FIELD

[0001] 本发明涉及半导体技术领域,特别涉及一种形成侧墙方法。 [0001] The present invention relates to semiconductor technology, and more particularly to a method of forming a spacer. 背景技术 Background technique

[0002] 在1微米以下的半导体生产工艺中一般都会使用侧墙的结构,侧墙一般用来环绕多晶硅栅极,防止更大剂量的源/漏注入过于接近的沟道从而导致发生源/漏穿通(punch through)ο [0002] The spacers generally used in less than 1 micron semiconductor manufacturing processes structures surrounding polysilicon gate spacer is generally used to prevent a larger dose source / drain implant is too close to the channel leading to the occurrence of source / drain through (punch through) ο

[0003] 现有技术公开了一种形成侧墙的方法,参照图1给出形成侧墙的方法的流程示意图,包括: [0003] The prior art discloses a method of forming spacers, a schematic flowchart of a method of forming spacers is given with reference to FIG, comprising:

[0004] 第一步,在硅片表面生长二氧化硅薄膜;第二步,在二氧化硅薄膜上面生长氮化硅薄膜;第三步,侧墙刻蚀;第四步,重复步骤二和三,分别进行第二次生长氮化硅薄膜和第二次侧墙刻蚀,直至获得宽度为500-800埃的“D”形状的侧墙。 [0004] The first step, the silicon dioxide film grown on the wafer surface; the second step, the silicon dioxide film grown above a silicon nitride film; a third step of etching the spacer; a fourth step of repeating steps two and three, respectively, a second silicon nitride film growth and etching the second side wall, until the width "D" shaped spacers 500-800 angstroms.

[0005] 在申请号为200610071764的中国专利申请中还可以发现更多与上述技术方案相 [0005] In the Chinese patent application No. 200 610 071 764 Application can also be found in the above-described technical solutions with more

关的信息。 Related information.

[0006] 在上述技术方案中,所述二氧化硅薄膜和第一次生长的氮化硅薄膜构成第一侧墙层,第二次生长的氮化硅薄膜构成第二侧墙层,即在生长第一侧墙层、第二侧墙层后,每次进行第一步刻蚀和第二步刻蚀,一方面增加了工艺步骤,同时不能很好的控制各步刻蚀的停止层以及刻蚀的最后剖面形状。 [0006] In the above aspect, the silicon oxide film and a silicon nitride film constituting the first growing a first spacer layer, a second silicon nitride film constituting the second spacer layer is grown, i.e. after growing a first spacer layer, a second spacer layer, each first step and second step of etching the etching, an aspect of the process steps increases, while not well controlled in each step of the etch stop layer and Finally, cross-sectional shape of the etching.

[0007] 现有技术还公开一种形成侧墙的技术方案,参照图2至3所示。 [0007] The prior art also discloses a method of forming spacers technical solution, as shown with reference to FIGS. 2-3. 首先参照图2,提供半导体衬底11,所述半导体衬底U上形成有栅介质层、栅极构成的栅极结构12、形成于栅极结构上和两侧的第一侧墙层13和第二侧墙层14,所述栅极结构12两侧的半导体底11 中还形成有源/漏延伸区,在此为了简化图示,未示出。 Referring first to FIG. 2, a semiconductor substrate 11, gate dielectric layer is formed on the semiconductor substrate U, constituting a gate structure of the gate 12 is formed on the gate structure and the first spacer layer 13 on both sides and the second spacer layer 14, 12 in the semiconductor substrate on both sides of the gate structure 11 is formed further active / drain extension regions, here for simplicity of illustration, it is not shown. 所述第一侧墙层13和第二侧墙层14采用绝缘介质材料制备,在实际半导体工艺中所述第一侧墙层13 —般依次采用氧化硅和氮化硅组成的复合层(ON),所述第二侧墙层14 一般采用氮化硅。 The first spacer layer 13 and the second spacer layer 14, an insulating dielectric material were prepared, in an actual semiconductor process, the first spacer layer 13 - as sequentially composite layer of silicon oxide and silicon nitride (ON ), the second spacer layer 14 is typically silicon nitride.

[0008] 参照图3,对第二侧墙层14和第一侧墙层13进行刻蚀,该刻蚀步骤包括两个步骤: 首先,采用第一刻蚀气体进行第一刻蚀,所述第一刻蚀气体为CF4、CHF3, O2和Ar,体积比为40 : 80 : 20 : 250,该步骤中主要刻蚀半导体衬底11和栅极结构12上的第二侧墙层14, 一般情况下,该步骤不会把导体衬底11和栅极结构12上的第二侧墙层14完全去除干净, 栅极结构12两侧的第二侧墙层形成“D”形状;接着,采用第二刻蚀气体进行第二刻蚀,所述第二刻蚀气体为CH3F、O2和Ar,体积比为20 : 80 : 100。 [0008] Referring to FIG 3, a second spacer layer 14 and the first spacer layer 13 is etched, the etching step comprises two steps: first, a first etching using a first etching gas, the the first etching gas is CF4, CHF3, O2 and Ar, a volume ratio of 40: 80: 20: 250, this step primarily etching the semiconductor substrate 11 and the second gate structure on the spacer layer 1214, generally case, the second step is not the spacer layer 12 on the semiconductor substrate 11 and the gate structure 14 is completely removed completely, the second spacer layer 12 is formed on both sides of the gate structure "D" shape; next, the second etching gas for the second etching, the second etching gas is CH3F, O2 and Ar, a volume ratio of 20: 80: 100. 该第二刻蚀步骤中,一方面要刻蚀第一刻蚀步骤中的未去除到位的栅极结构12两侧与半导体衬底相接触位置处的第二侧墙层14至预定尺寸,同时还要除去半导体衬底11和栅极结构12上残留的第二侧墙层14, 直至去除部分第一侧墙13中的氧化硅层并停留在第一侧墙13中的氧化硅层上,经过第二刻蚀后,所述第一侧墙层13变成13a,第二侧墙层14变成14a。 The second etching step, on the one hand to a first etching step of etching 14 the second spacer layer to a predetermined size with the semiconductor substrate 12 on both sides of the gate structure in place at the contact position is not removed, while also the semiconductor substrate 11 is removed and the second spacer layer 12 remaining on the gate structure 14, until the first spacer portions of the silicon oxide layer 13 is removed and remains on the side wall 13 in the first silicon oxide layer, after the second etching, the first layer 13 into spacer 13a, the second layer 14 into spacer 14a.

[0009] 但是,在上述技术方案中,进行第二刻蚀的选择比难以控制,无法既满足将栅极结构12两侧与半导体衬底相接触位置处的第二侧墙层14至预定尺寸,还要除去半导体衬底11和栅极结构12上残留的第二侧墙层14,直至停留在第一侧墙13中的氧化硅层上。 [0009] However, in the above aspect, the second etching selection ratio is difficult to control, not only to meet the 14 second spacer layer to a predetermined size to both sides of the gate structure 12 in contact with the semiconductor substrate at a position , but also to remove the semiconductor substrate 11 and the second spacer layer 12 remaining on the gate structure 14, until it rests on the first sidewall 13 in the silicon oxide layer. 实际刻蚀工艺中,通常会过刻蚀栅极结构12两侧与半导体衬底相接触位置处的第一侧墙层13, 如图3中虚线框内位置。 The actual etching process, over-etching is usually in contact with both sides of the gate structure 12 at a position of the first spacer layer and the semiconductor substrate 13, the position of the dashed box in FIG. 3.

[0010] 如图4给出采用上述技术方案制备的侧墙的电子扫描电镜(SEM)测试结果,在图4 中区域400内出现过刻蚀现象,使得栅极结构两侧的覆盖在半导体衬底上第一侧墙层局部变薄,这样在后续形成源/漏极工艺中,会影响源/漏极注入离子的深度,从而影响半导体器件的性能。 [0010] FIG. 4 shows a sidewall prepared using the above technical solutions of the scanning electron microscope (SEM) test results, over-etching phenomenon occurs in the region 400 of Figure 4, so as to cover sides of the gate structure in a semiconductor substrate a first spacer layer on the bottom locally thinned, so that the subsequent formation of the source / drain process, will affect the depth of the source / drain ion implantation, which could affect performance of the semiconductor device.

发明内容 SUMMARY

[0011] 本发明解决的问题是提供一种形成侧墙的方法,避免现有技术的形成侧墙工艺中刻蚀不均勻导致栅极结构两侧的过刻蚀现象。 [0011] The present invention solves the problem is to provide a method of forming spacers, spacer formation process avoiding the prior art results in uneven etching over etching phenomenon on both sides of the gate structure.

[0012] 为解决上述问题,本发明提供一种形成侧墙方法,包括如下步骤:提供半导体衬底,所述半导体衬底上形成有栅极结构、形成于栅极结构两侧及其上的第一侧墙层和第二侧墙层,所述第一侧墙层含有氮化硅层;刻蚀栅极结构上和半导体衬底上的第二侧墙层; 刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸;去除栅极结构上和半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层。 [0012] In order to solve the above problems, the present invention provides a method of forming sidewall spacers, comprising the steps of: providing a semiconductor substrate, a gate structure is formed on the semiconductor substrate, formed on both sides of the gate structure and on a first spacer layer and the second spacer layer, the spacer layer comprises a first layer of silicon nitride; a second spacer layer over the gate structure and etching the semiconductor substrate; etching both sides of the gate structure a second spacer layer and the semiconductor substrate at the intersection to a predetermined size; removing the silicon nitride layer, a second spacer layer over the gate structure and the semiconductor substrate and the first spacer layer.

[0013] 可选地,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体包括CF4与CHF3> CH2F2或CH3F中的任一组合。 [0013] Alternatively, the gas in the second spacer layer over the gate structure and the semiconductor substrate etching comprises CF4> CH2F2 and CHF3, or any combination of CH3F.

[0014] 可选地,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体包括CHF3与CF4,其流量范围分别为65至IOOsccm和30至50sccm。 [0014] Alternatively, the gas in the second spacer layer over the gate structure and the semiconductor substrate comprises etching CHF3 and CF4, the flow ranges are 65 to 30 and to IOOsccm of 50sccm.

[0015] 可选地,所述CHF3与CF4体积比为1. 6至2. 5。 [0015] Alternatively, the volume ratio of CF4 and CHF3 1.6 to 2.5.

[0016] 可选地,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体还包括Ar,所述Ar的流量范围为50至70SCCm。 [0016] Alternatively, the gas in the second spacer layer over the gate structure and the semiconductor substrate further comprises etching Ar, the Ar flow rate range of 50 to 70 sccm.

[0017] 可选地,所述刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的气体包括O2和CHF3,其流量范围分别为20至30sccm和110至140sccm。 [0017] Alternatively, the etch gate structure and the semiconductor substrate on both sides of the intersection of the second spacer layer to a predetermined size gas comprises O2 and CHF3, the flow ranges of 20 to 110 to 140sccm and 30sccm .

[0018] 可选地,所述O2和CHF3的体积比为1/4. 6至1/5. 5。 [0018] Alternatively, the O2 and CHF3 volume ratio of 1/4 6 to 1/5. 5.

[0019] 可选地,所述去除栅极结构上和半导体衬底上的第二侧墙层的刻蚀气体包括CH3F 和O2,其流量范围分别为180至220sccm和100至150sccm。 [0019] Alternatively, the etching gas is removed from the second spacer layer and the gate structure on a semiconductor substrate comprising CH3F and O2, the flow rate range of 180 to 220sccm, respectively, and is 100 to 150sccm.

[0020] 可选地,所述CH3F和O2的体积比为1. 4至1. 8。 [0020] Alternatively, the CH3F and O2 volume ratio of 1.4 to 1.8.

[0021] 可选地,所述刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的气体、或者去除栅极结构上和半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层的刻蚀气体还包括He,所述He的流量范围为150至250sccm。 [0021] Alternatively, the second spacer layer is etched to a predetermined size of the gas gate structure and the semiconductor substrate on both sides at the intersection, or the removal of the second sidewall gate structure on a semiconductor substrate and etching the first spacer layer and a gas layer further comprises a silicon nitride layer is He, He is the flow rate in the range of 150 to 250sccm.

[0022] 可选地,所述第一侧墙层为氧化硅、氮化硅组成的复合层,所述第二侧墙层为氮化娃。 [0022] Alternatively, the first spacer layer is a silicon oxide, composite layers of silicon nitride, the second spacer layer is a nitride baby.

[0023] 与现有技术相比,本技术方案具有以下优点:通过将刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的刻蚀步骤与去除栅极结构上和半导体衬底上残留的第二侧墙层和第一侧墙层中的氮化硅层步骤分开进行,达到容易控制侧墙形状的目的。 [0023] Compared with the prior art, the present solution has the following advantages: By the second spacer layer is etched on both sides of the gate structure and the semiconductor substrate to a predetermined size at the intersection of the etching step and removal of the gate structure remaining on the semiconductor substrate and on the second spacer layer and the spacer layer, the first silicon nitride layer separate steps, the purpose of easily controlling the shape of the spacer.

[0024] 同时,本技术方案通过在刻蚀栅极结构上和半导体衬底上的第二侧墙层步骤内降低Ar的含量,可以减弱物理轰击效果,从而很好的控制刻蚀后的最终剖面。 After [0024] Meanwhile, the present technical solution and the second spacer layer on the semiconductor substrate step of reducing the content of Ar in the etching of the gate structure, can be weakened physical bombardment effect, so that a good control of etching final profile. [0025] 本技术方案在刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸、 以及去除栅极结构上和半导体衬底上的第二侧墙层并暴露出第一侧墙层步骤中采用He代替现有技术的Ar,可以减弱物理轰击效果,从而改善刻蚀的选择比达到最终控制刻蚀剖面图的目的。 [0025] The second aspect of the present spacer layer on the gate structure on the second spacer layer to a predetermined size on both sides of the gate structure and the semiconductor substrate is etched at the intersection, and removing the semiconductor substrate and is exposed and He and Ar in place of the prior art employed in the first spacer layer step, physical bombardment effect can be weakened, thereby improving the object of the etching selection ratio to a final control of the etching cross-sectional view of FIG.

附图说明 BRIEF DESCRIPTION

[0026] 图1是现有技术的形成侧墙的流程示意图; [0026] FIG. 1 is a schematic flow diagram of a prior art spacer is formed;

[0027] 图2至图3是现有技术的形成侧墙的结构示意图; [0027] FIG. 2 through FIG. 3 is a schematic diagram of the prior art spacer is formed;

[0028] 图4是采用电子扫描显微镜测试现有技术形成的侧墙的结果; [0028] Figure 4 is a scanning electron microscope test results of the prior art spacer is formed;

[0029] 图5是本发明的一个具体实施方式的形成侧墙的流程示意图; [0029] FIG. 5 is a schematic flow diagram of a particular embodiment of spacers formed embodiment of the present invention;

[0030] 图6至9是本发明的形成侧墙的结构示意图; [0030] FIG. 6-9 is a schematic view of the formation of spacers according to the invention;

[0031] 图10是采用本发明的技术形成的侧墙的电子扫描显微镜测试结果。 [0031] FIG. 10 is a scanning electron microscope test results using the spacer technique of the present invention is formed.

具体实施方式 detailed description

[0032] 本发明通过将刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的刻蚀步骤与去除栅极结构上和半导体衬底上残留的第二侧墙层和第一侧墙层中的氮化硅层步骤分开进行,达到容易控制侧墙形状的目的。 [0032] The present invention will remain on the second spacer layer is etched sides of the gate structure and the semiconductor substrate to a predetermined size at the intersection of the etching step and removal of the gate structure on a semiconductor substrate and a second spacer layer and the first spacer layer is a silicon nitride layer for a separate step, easily controlled to achieve the purpose of the sidewall shape.

[0033] 同时,本发明通过在刻蚀栅极结构上和半导体衬底上的第二侧墙层步骤内降低Ar 的含量,可以减弱物理轰击效果,从而很好的控制刻蚀后的最终剖面。 [0033] Also, by the present invention and a second spacer layer on the semiconductor substrate step of reducing the content of Ar in the etching of the gate structure, can be weakened physical bombardment effect, so that good control of the final cross-section after etching .

[0034] 本发明在刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸、以及去除栅极结构上和半导体衬底上的第二侧墙层并暴露出第一侧墙层步骤中采用He代替现有技术的Ar,可以减弱物理轰击效果,从而改善刻蚀的选择比达到最终控制刻蚀剖面图的目的。 [0034] On the gate structure on the second spacer layer to a predetermined size on both sides of the gate structure and the semiconductor substrate is etched at the intersection, and removing the semiconductor substrate and a second spacer layer of the present invention is to expose He instead of a prior art spacer layer Ar steps employed may be attenuated physical bombardment effect, so the purpose of improving the etching selection ratio to a final control of the etching cross-sectional view of FIG.

[0035] 本发明首先提供一种形成侧墙的方法,如图5所示,给出本发明的一个具体实施方式的形成侧墙的流程示意图,包括:执行步骤S11,提供半导体衬底,所述半导体衬底上形成有栅极结构、形成于栅极结构两侧及其上的第一侧墙层和第二侧墙层,所述第一侧墙层中含有氮化硅层;执行步骤S13,刻蚀栅极结构上和半导体衬底上的第二侧墙层;执行步骤S15,刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸;执行步骤S17, 去除栅极结构上和半导体衬底上的第二侧墙层并暴露出第一侧墙层。 [0035] First, the present invention provides a method of forming spacers, as shown in flow schematic form sidewall spacers 5 are given a specific embodiment of the present invention, FIG comprising: performing step S11, the semiconductor substrate is provided, the step; gate structure formed on both sides of the gate structure and the first spacer layer and a second spacer layer on said first spacer layer comprises a silicon nitride layer is formed on said semiconductor substrate S13, the second spacer layer is etched and the gate structure on a semiconductor substrate; performing step S15, the second spacer layer is etched to a predetermined size of the gate structure and the semiconductor substrate on both sides of the intersection; step S17 is executed removing the second spacer layer over the gate structure and the semiconductor substrate and exposing the first spacer layer.

[0036] 图6至9给出本发明的形成侧墙的结构示意图。 Schematic structural diagram of [0036] Figures 6 to 9 of the present invention is given in forming sidewall spacers. 首先参照图6,所述半导体衬底11上形成有有栅介质层、栅极构成的栅极结构12、形成于栅极结构上和两侧的第一侧墙层13和第二侧墙层14,所述第一侧墙层13中含有氮化硅层,所述栅极结构12两侧的半导体底11中还形成有源/漏延伸区,在此为了简化图示,未示出。 Referring first to FIG. 6, there is formed a gate dielectric layer, gate electrode 12 composed of a gate structure, formed on the gate structure and the first spacer layer 13 and the second sides of the spacer layer 11 on the semiconductor substrate 14, the first spacer layer 13 comprises silicon nitride layer 12 in the semiconductor substrate on both sides of the gate structure 11 is formed further active / drain extension regions, here for simplicity of illustration, it is not shown.

[0037] 所述第一侧墙层13和第二侧墙层14采用绝缘介质材料制备,在实际半导体工艺中,所述第一侧墙层13 —般依次采用氧化硅和氮化硅组成的复合层(ON),所述第二侧墙层14 一般采用氮化硅。 [0037] The first spacer layer 13 and the second spacer layer 14, an insulating dielectric material were prepared, in an actual semiconductor process, the first spacer layer 13 - as silicon oxide and silicon nitride are sequentially composed of composite layer (ON), the second spacer layer 14 is typically silicon nitride.

[0038] 参照图7,对栅极结构上和半导体衬底上的第二侧墙层14进行第一刻蚀,所述第一刻蚀的气体包括CF4与CHF3、CH2F2或CH3F中的任一组合。 [0038] Referring to FIG 7, a second spacer layer over the gate structure on the semiconductor substrate 14 and the first etching, the first etching gas includes CF4 and CHF3, CH3F CH2F2 or either a combination.

[0039] 作为本发明的一个优化实施例,所述第一刻蚀的气体包括CHF3与CF4,其流量范围 [0039] As a refinement of the embodiment of the invention, the first etching gas includes CHF3 and CF4, which flow range

5分别为65至IOOsccm和30至50sccm,所述CHF3与CF4体积比为1. 6至2. 5。 5 respectively, to 30 and 65 to IOOsccm 50sccm, CHF3 and CF4 the volume ratio of 1.6 to 2.5. CHF3可以为70、80、90sccm,所述CF4 对应可以为35、45、48sccm。 CHF3 may 70,80,90sccm, the correspondence may be CF4 35,45,48sccm.

[0040] 所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体还包括Ar,所述Ar的流量范围为50至70sccm,可以为55、60、68sccm。 [0040] The etching gas of the second spacer layer over the gate structure and the semiconductor substrate further comprises a flow range of Ar, the Ar 50 to 70sccm, may 55,60,68sccm.

[0041] 所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体还包括02,其流量范围为15至40SCCm,可以为25、30、38sCCm。 [0041] The gas from the second spacer layer is etched and the gate structure 02 further includes a semiconductor substrate, which is in the range of 15 to 40 sccm of flow, may be 25,30,38sCCm. 第一刻蚀过程中,腔室内的气压为25至35mTorr(ImTorr = 133. 3Pa) A first etching process, the chamber pressure of 25 to 35mTorr (ImTorr = 133. 3Pa)

[0042] 作为本实施方式的一个实施例,所述第一刻蚀的气体为CF4、CHF3、02和Ar,其流量范围分别为45、90、38、50、68sCCm。 [0042] As an embodiment of the present embodiment, the first etching gas is CF4, CHF3,02 and Ar, respectively, which flow range 45,90,38,50,68sCCm. 经过该第一刻蚀后,去除栅极结构12上和半导体衬底11上的绝大部分的第二侧墙层14,同时,在刻蚀栅极结构12上和半导体衬底11上的绝大 After the first etching, a gate structure 12 is removed and most of the second spacer layer 11 on the semiconductor substrate 14 while, in the etching of the gate insulating structure 12 and the semiconductor substrate 11 Big

部分的第二侧墙层14的同时,也去除栅极结构12两侧的第二侧墙层14的部分,形成 While the second portion of the spacer layer 14 is also removed portions of the second spacer layer 12 on both sides of the gate structure 14 is formed

状的第二侧墙层14a。 Shaped second spacer layer 14a.

[0043] 与现有技术相比,本发明在第一刻蚀的刻蚀栅极结构上和半导体衬底上的第二侧墙层过程中降低Ar的流量,可以减弱物理轰击从而很好的控制刻蚀后的最终剖面。 [0043] Compared with the prior art, the present invention and a second spacer layer on the semiconductor substrate, the process of reducing the flow rate of Ar in the first etch etching the gate structure, can be reduced so that good physical bombardment control the final cross-section after etching.

[0044] 参照图8,在进行第一刻蚀之后,一般情况下,栅极结构两侧与半导体衬底相交处的第二侧墙层尺寸h —般仍然不符合要求,栅极结构两侧与半导体衬底相交处的第二侧墙层的尺寸会影响后续离子注入的深度,因此需要对栅极结构两侧与半导体衬底相交处的第二侧墙层进行第二刻蚀至预定尺寸。 [0044] Referring to FIG 8, after performing the first etching, in general, the second spacer layer dimension h sides of the gate structure and the semiconductor substrate at the intersection of - generally still does not meet the requirements, both sides of the gate structure size of the second spacer layer and the semiconductor substrate can affect the depth of the intersection at the subsequent ion implantation, and therefore need to be etched to a predetermined size on a second sidewall of the second layer of the gate structure and the semiconductor substrate on both sides of the intersection .

[0045] 所述第二刻蚀的气体包括O2和CHF3,其流量范围分别为20至30sCCm和110至140sccm,所述02和(:冊3的体积比为1/4. 6至1/5. 5。所述O2的流量可以为20、25、28sccm, 所述CHF3的流量相应可以为110、125、140sccm。 [0045] The second etching gas includes O2 and CHF3, the flow ranges of 20 to 110 and 30sCCm to 140sccm, and the 02 (: volume ratio of 3 volumes of 1/4 to 6 1/5 flow 5. the O2 may be 20,25,28sccm, a respective flow rate of the CHF3 may 110,125,140sccm.

[0046] 所述第二刻蚀的气体还包括He,所述He的流量范围为150至250sCCm。 [0046] The second etching gas further comprises He, He is the flow rate in the range of 150 to 250 sccm. 可以为180、220、230sccm。 Can 180,220,230sccm. 第二刻蚀中,腔室内的气压为35至45mTorr。 A second etching, the chamber pressure of 35 to 45mTorr.

[0047] 作为本实施方式的一个优化实施例,所述第二刻蚀的气体CHF3、02、He的流量分别为25、125、200sCCm。 [0047] As an optimal embodiment of the present embodiment, the flow rate of the second etching gas CHF3,02, He, respectively 25,125,200sCCm. 经过第二刻蚀后,刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸。 After the second etching, etching the second spacer layer to a predetermined size of the gate structure and the semiconductor substrate on both sides of the intersection.

[0048] 本发明在刻蚀栅极结构12两侧与半导体衬底11相交处的第二侧墙层14至预定尺寸中采用He代替现有技术的Ar,可以减弱物理轰击效果,从而改善刻蚀的选择比达到最终控制刻蚀剖面图的目的。 [0048] The present invention in place of the prior art using a He Ar 14 to a predetermined size in the second spacer layer 11 is etched at an intersection of the gate structure and the semiconductor substrate 12 on both sides, it can be weakened physical bombardment effect, thereby improving carved etching selection ratio to achieve the ultimate purpose of the control of the etching cross-sectional view of FIG.

[0049] 参照图9,由于在第一刻蚀中,未必能够完全去除半导体衬底11上和栅极结构12 上的第二侧墙层14和第一侧墙层13中的氮化硅层,因此需要进行刻蚀半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层的第三刻蚀步骤。 [0049] Referring to FIG. 9, since the first etching, the semiconductor substrate may not completely remove the silicon nitride layer 13 on the second spacer layer 11 on the structure 12 and the gate 14 and the first spacer layer , hence the need for etching the second spacer layer on the substrate and a third step of etching the silicon nitride layer, a first spacer layer of the semiconductor. 为了确保完全去除半导体衬底11 和栅介质层12上的第二侧墙层和第一侧墙层中的氮化硅层,在该第三刻蚀中,一直要刻蚀掉第一侧墙层13中的氮化硅层,并刻蚀掉第一侧墙层13中的部分氧化硅层,经过第三刻蚀后,第一侧墙层13变成第一侧墙层13a。 To ensure complete removal of the semiconductor substrate 11 and the second spacer layer and the spacer layer, the first silicon nitride layer on the gate dielectric layer 12, the third etching, to etch away the first sidewall spacer has the layer of silicon nitride layer 13, and etching away the first spacer layer 13 in the portion of the silicon oxide layer, after the third etching, the first spacer layer 13 becomes a first spacer layer 13a.

[0050] 所述第三刻蚀的气体包括CH3F和02,其流量范围分别为180至220sCCm和100至150sccm。 [0050] The third etching gas comprising CH3F and 02, respectively, the flow rate range of 180 to 100 and to 150sccm is 220sCCm. 所述CH3F禾口O2的体积比为1. 4至1.8。 The CH3F Wo port O2 volume ratio of 1.4 to 1.8. 所述CH3F可以为190、200、210sccm,相应地,所述O2可以为125、135、145sccm。 The CH3F may 190,200,210sccm, correspondingly, the O2 may 125,135,145sccm.

6[0051] 所述第三刻蚀的气体还包括He,其流量范围为150至250sCCm。 6 [0051] The third etching gas further comprises He, the flow rate in the range of 150 to 250 sccm. 所述He流量可以为180、200、230sccm。 The He flow may be 180,200,230sccm. 第三刻蚀中,腔室内的气压为35至45mTorr The third etching, the chamber pressure of 35 to 45mTorr

[0052] 作为本实施方式的一个优化实施例,所述第三刻蚀的气体CH3F、02、He的流量分别为200、125、200sCCm。 [0052] As an optimal embodiment of the present embodiment, the third etching gas CH3F, 02, respectively, the flow rate of He 200,125,200sCCm. 经过第三刻蚀后,去除半导体衬底11和栅介质层12上的第二侧墙层14和第一侧墙层13中的氮化硅层。 After the third etching, the semiconductor substrate 11 is removed and the second spacer layer 13 on the gate dielectric layer 12, a first spacer layer 14 and the silicon nitride layer.

[0053] 同样,本发明在去除半导体衬底和栅极结构12上的第二侧墙层和第一侧墙层中的氮化硅层并暴露出第一侧墙层13中的氧化硅层的步骤中采用He代替现有技术的Ar,可以减弱物理轰击效果,从而改善刻蚀的选择比达到最终控制刻蚀剖面图的目的。 [0053] Similarly, in removing the semiconductor substrate and the gate structure 12 of the second spacer layer and the first spacer layer and exposing the silicon nitride layer of the present invention, the first spacer layer 13 in the silicon oxide layer He instead of the prior art employed in the step of Ar, can be weakened physical bombardment effect, so the purpose of improving the etching selection ratio to a final control of the etching cross-sectional view of FIG.

[0054] 在上述实施方式中,通过将刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的刻蚀步骤与去除栅极结构上和半导体衬底上残留的第二侧墙层和第一侧墙层中的氮化硅层的步骤分开进行,达到容易控制侧墙形状的目的。 [0054] In the above-described embodiment, to a predetermined size by the second spacer layer is etched on both sides of the gate structure and the semiconductor substrate and the intersection of the etching step and removal of the gate structure on the semiconductor substrate remaining and a first spacer layer in the second step of the silicon nitride layer spacer layer is separated, the purpose of easily controlling the shape of the sidewall.

[0055] 图10是采用本发明的技术形成的侧墙的电子扫描显微镜(SEM)测试结果。 [0055] FIG. 10 is a spacer employed in the art of the present invention is formed of a scanning electron microscope (SEM) results. 电子扫描显微镜(SEM)采用美国应用材料(Applied Materials Co. Ltd.)公司的型号为Compass 的电子扫描显微镜(SEM)。 Scanning electron microscopy (SEM) used by the US Applied Materials (Applied Materials Co. Ltd.) company Compass model of a scanning electron microscope (SEM). 可以看出,图10中栅极结构两侧的侧墙与半导体衬底上的第一侧墙层相接触处区域500内没有出现过刻蚀,说明本发明的刻蚀方法的有效性。 As can be seen, the first spacer layer on the sidewall of the semiconductor substrate on both sides of the gate structure 10 does not occur at the contact region 500 through etching, the etching method to illustrate the effectiveness of the present invention.

[0056] 虽然本发明已以较佳实施例披露如上,但本发明并非限定于此。 [0056] While the present invention has been disclosed above with reference to preferred embodiments, but the present invention is not limited thereto. 任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。 Anyone skilled in the art, without departing from the spirit and scope of the present invention, various changes or modifications may be made, and therefore the scope of the present invention reference should be made to the scope defined by the claims.

Claims (9)

  1. 一种形成侧墙方法,包括如下步骤:提供半导体衬底,所述半导体衬底上形成有栅极结构、形成于栅极结构两侧及其上的第一侧墙层和第二侧墙层,所述第一侧墙层含有氮化硅层;刻蚀栅极结构上和半导体衬底上的第二侧墙层;刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸,所述刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的气体包括O2和CHF3,其流量范围分别为20至30sccm和110至140sccm;去除栅极结构上和半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层,所述去除栅极结构上和半导体衬底上的第二侧墙层的刻蚀气体包括CH3F和O2,其流量范围分别为180至220sccm和100至150sccm。 Forming a sidewall spacer method, comprising the steps of: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, is formed on the sides of the gate structure and the first spacer layer and the second spacer layer said first spacer layer comprises a silicon nitride layer; a second spacer layer over the gate structure and etching the semiconductor substrate; a second sidewall etching both sides of the gate structure and the semiconductor substrate at the intersection of layer to a predetermined size, the etch gate structure and the semiconductor substrate on both sides of the intersection of the second spacer layer to a predetermined size gas comprises O2 and CHF3, the flow ranges of 20 to 140 sccm and 110 to 30sccm; removed a silicon nitride layer over the gate structure and the second spacer layer on the semiconductor substrate and the first spacer layer, said second spacer layer etching gas is removed from the gate structure and the semiconductor substrate comprising CH3F and O2, the flow rate range of 180 to 220sccm, respectively, and is 100 to 150sccm.
  2. 2.根据权利要求1所述的形成侧墙方法,其特征在于,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体包括CF4与CHF3、CH2F2或CH3F中的任一组合。 The spacer forming method according to claim 1, characterized in that the gas of the second spacer layer over the gate structure and the semiconductor substrate comprises any one of CF4 and the etching CHF3, CH2F2 or CH3F of a combination.
  3. 3.根据权利要求1所述的形成侧墙方法,其特征在于,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体包括CHF3与CF4,其流量范围分别为65至lOOsccm和30至50sccmo 3. The method of forming spacers according to claim 1, characterized in that the gas of the second spacer layer and the gate structure on the semiconductor substrate comprises etching with CHF3 CF4, flow rate ranges were 65 to lOOsccm and 30 to 50sccmo
  4. 4.根据权利要求3所述的形成侧墙方法,其特征在于,所述CHF3与CF4体积比为1. 6至2 · 5 ο 4. The method of forming spacers according to claim 3, wherein the volume ratio of CF4 and CHF3. 6 to 1. to 2 · 5 ο
  5. 5.根据权利要求4所述的形成侧墙方法,其特征在于,所述刻蚀栅极结构上和半导体衬底上的第二侧墙层的气体还包括Ar,所述Ar的流量范围为50至70sCCm。 5. The method of forming spacers according to claim 4, characterized in that the gas of the second spacer layer over the gate structure and the semiconductor substrate further comprises etching said Ar, the Ar flow rate range is 50 to 70sCCm.
  6. 6.根据权利要求1所述的形成侧墙方法,其特征在于,所述刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸工艺中所述O2和CHF3的体积比为1/4. 6至1/5. 5。 The spacer forming method according to claim 1, wherein said etching the second spacer layer of the gate structure and the semiconductor substrate on both sides of the intersection of the said process to a predetermined size of CHF3 and O2 a volume ratio of 1/4 6 to 1/5. 5.
  7. 7.根据权利要求1所述的形成侧墙方法,其特征在于,所述去除栅极结构上和半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层工艺中所述CH3F和O2的体积比为1. 4至1. 8。 The spacer forming method according to claim 1, wherein said silicon nitride layer removal process of the second spacer layer over the gate structure and the semiconductor substrate and the first spacer layer the CH3F and O2 volume ratio of 1.4 to 1.8.
  8. 8.根据权利要求1所述的形成侧墙方法,其特征在于,所述刻蚀栅极结构两侧与半导体衬底相交处的第二侧墙层至预定尺寸的气体、或者去除栅极结构上和半导体衬底上的第二侧墙层和第一侧墙层中的氮化硅层的刻蚀气体还包括He,所述He的流量范围为150至250sccmo The spacer forming method according to claim 1, wherein said second spacer layer etching gas to a predetermined size of the sides of the gate structure and the semiconductor substrate at the intersection, or the removal of the gate structure a second spacer layer and the etching gas for the first silicon nitride layer on the spacer layer and the semiconductor substrate further comprises a He, He is the flow rate in the range of 150 to 250sccmo
  9. 9.根据权利要求1至5中任一项所述的形成侧墙方法,其特征在于,所述第一侧墙层为依次由氧化硅、氮化硅组成的复合层,所述第二侧墙层为氮化硅。 9. The method of forming spacers according to any one of claim 15, wherein said first spacer layer is a composite layer are formed of silicon oxide, silicon nitride, and the second side wall layer of silicon nitride.
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