CN103026460A - 用于制备多层式晶体结构的方法 - Google Patents

用于制备多层式晶体结构的方法 Download PDF

Info

Publication number
CN103026460A
CN103026460A CN201080064913XA CN201080064913A CN103026460A CN 103026460 A CN103026460 A CN 103026460A CN 201080064913X A CN201080064913X A CN 201080064913XA CN 201080064913 A CN201080064913 A CN 201080064913A CN 103026460 A CN103026460 A CN 103026460A
Authority
CN
China
Prior art keywords
layer
implanted
ions
donor
donor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201080064913XA
Other languages
English (en)
Chinese (zh)
Inventor
D·A·维特
J·L·利伯特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SunEdison Inc
Original Assignee
SunEdison Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SunEdison Inc filed Critical SunEdison Inc
Publication of CN103026460A publication Critical patent/CN103026460A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24174—Structurally defined web or sheet [e.g., overall dimension, etc.] including sheet or component perpendicular to plane of web or sheet

Landscapes

  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
CN201080064913XA 2009-12-30 2010-12-22 用于制备多层式晶体结构的方法 Pending CN103026460A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US29096109P 2009-12-30 2009-12-30
US61/290,961 2009-12-30
PCT/US2010/061858 WO2011082079A1 (en) 2009-12-30 2010-12-22 Method for the preparation of a multi-layered crystalline structure

Publications (1)

Publication Number Publication Date
CN103026460A true CN103026460A (zh) 2013-04-03

Family

ID=43587555

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080064913XA Pending CN103026460A (zh) 2009-12-30 2010-12-22 用于制备多层式晶体结构的方法

Country Status (8)

Country Link
US (2) US8367519B2 (https=)
EP (2) EP2519965B1 (https=)
JP (2) JP5591949B2 (https=)
KR (1) KR20120117843A (https=)
CN (1) CN103026460A (https=)
SG (1) SG181986A1 (https=)
TW (2) TW201330062A (https=)
WO (1) WO2011082079A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
US8796054B2 (en) * 2012-05-31 2014-08-05 Corning Incorporated Gallium nitride to silicon direct wafer bonding
JP6024400B2 (ja) 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
US9281233B2 (en) * 2012-12-28 2016-03-08 Sunedison Semiconductor Limited Method for low temperature layer transfer in the preparation of multilayer semiconductor devices
TWI509681B (zh) * 2013-11-15 2015-11-21 All Ring Tech Co Ltd Method and apparatus for processing on wafers
US9496128B1 (en) 2015-10-15 2016-11-15 International Business Machines Corporation Controlled spalling utilizing vaporizable release layers
SG11202009989YA (en) 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040077184A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
CN1773677A (zh) * 2004-11-11 2006-05-17 硅电子股份公司 半导体基材及其制造方法
WO2008107751A1 (en) * 2007-03-06 2008-09-12 S.O.I.Tec Silicon On Insulator Technologies Process for fabricating a substrate comprising a deposited buried oxide layer

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
JPH11145438A (ja) * 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
FR2773261B1 (fr) * 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7076042B1 (en) 2000-09-06 2006-07-11 Cisco Technology, Inc. Processing a subscriber call in a telecommunications network
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2819099B1 (fr) 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
US6686630B2 (en) * 2001-02-07 2004-02-03 International Business Machines Corporation Damascene double-gate MOSFET structure and its fabrication method
JP2004537161A (ja) 2001-04-11 2004-12-09 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 高抵抗率ｃｚシリコンにおけるサーマルドナー生成の制御
TW550681B (en) 2001-06-22 2003-09-01 Memc Electronic Materials Process for producing silicon on insulator structure having intrinsic gettering by ion implantation
JPWO2003046993A1 (ja) * 2001-11-29 2005-04-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US20040224482A1 (en) * 2001-12-20 2004-11-11 Kub Francis J. Method for transferring thin film layer material to a flexible substrate using a hydrogen ion splitting technique
WO2004061944A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
FR2876841B1 (fr) * 2004-10-19 2007-04-13 Commissariat Energie Atomique Procede de realisation de multicouches sur un substrat
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US20070117350A1 (en) 2005-08-03 2007-05-24 Memc Electronic Materials, Inc. Strained silicon on insulator (ssoi) with layer transfer from oxidized donor
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
EP1763069B1 (en) 2005-09-07 2016-04-13 Soitec Method for forming a semiconductor heterostructure
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
FR2906078B1 (fr) * 2006-09-19 2009-02-13 Commissariat Energie Atomique Procede de fabrication d'une structure micro-technologique mixte et une structure ainsi obtenue
FR2917235B1 (fr) * 2007-06-06 2010-09-03 Soitec Silicon On Insulator Procede de realisation de composants hybrides.
JP5386856B2 (ja) * 2008-06-03 2014-01-15 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
SG159484A1 (en) * 2008-09-05 2010-03-30 Semiconductor Energy Lab Method of manufacturing soi substrate
JP5364345B2 (ja) * 2008-11-12 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8679942B2 (en) * 2008-11-26 2014-03-25 Soitec Strain engineered composite semiconductor substrates and methods of forming same
US20100216295A1 (en) * 2009-02-24 2010-08-26 Alex Usenko Semiconductor on insulator made using improved defect healing process
US8198172B2 (en) * 2009-02-25 2012-06-12 Micron Technology, Inc. Methods of forming integrated circuits using donor and acceptor substrates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040077184A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
CN1773677A (zh) * 2004-11-11 2006-05-17 硅电子股份公司 半导体基材及其制造方法
WO2008107751A1 (en) * 2007-03-06 2008-09-12 S.O.I.Tec Silicon On Insulator Technologies Process for fabricating a substrate comprising a deposited buried oxide layer

Also Published As

Publication number Publication date
US20130137241A1 (en) 2013-05-30
JP2013516767A (ja) 2013-05-13
JP5591949B2 (ja) 2014-09-17
KR20120117843A (ko) 2012-10-24
TW201330062A (zh) 2013-07-16
SG181986A1 (en) 2012-08-30
WO2011082079A1 (en) 2011-07-07
JP2013175787A (ja) 2013-09-05
US20110159665A1 (en) 2011-06-30
TWI430339B (zh) 2014-03-11
US8367519B2 (en) 2013-02-05
EP2733735A2 (en) 2014-05-21
TW201140662A (en) 2011-11-16
EP2733735A3 (en) 2014-07-23
EP2519965A1 (en) 2012-11-07
EP2519965B1 (en) 2014-10-01

Similar Documents

Publication Publication Date Title
JP5770767B2 (ja) ターゲット基板に結合される少なくとも一の薄層を備えた積層構造の作製方法
CN101419911B (zh) 具有精细隐埋绝缘层的soi衬底
TWI492275B (zh) The method of manufacturing the bonded substrate
KR101335713B1 (ko) 접합 기판의 제조방법 및 접합 기판
JP2008021971A (ja) 電子工学、光学または光電子工学に使用される２つの基板を直接接合する方法
CN103038863A (zh) 制备用于结合的表面的氧等离子体转化方法
US8367519B2 (en) Method for the preparation of a multi-layered crystalline structure
JP2010538459A (ja) 熱処理を用いる剥離プロセスにおける半導体ウエハの再使用
JP2013516767A5 (https=)
JP2018085536A (ja) 多層半導体デバイス作製時の低温層転写方法
JP2007227415A (ja) 貼り合わせ基板の製造方法および貼り合わせ基板
WO2010137683A1 (ja) Ｓｏｉ基板の製造方法
JP7275438B2 (ja) 剥離可能な構造及び前記構造を使用する剥離プロセス
CN114787968A (zh) 接合两个半导体衬底的方法
US12473198B2 (en) Method for preparing the remainder of a donor substrate, substrate produced by said method, and use of such a substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130403